Magnus Danielson magnus@... writes:
Hi,
Darn, not reading all the notes. Again.
Well, in that case, scaling should be done... then you get average of
198,5075 ns and 149,8 ps RMS jitter, with 1,1 ns peak-to-peak.
The jitter is okish then, but a little better would indeed be nice.
Hi
Today I did the same test without these 2 oscillators. The stddev on
20141228 data is 149ps. The stddev of today is 97ps. According to the new
datasheet, stddev will be lower if set to 45ps resolution mode. I did that
and got 76ps stddev. The datasheet does not lie to me :).
Data is
Hi Neil
Just now, I disconnected TPS79333 from board and used LR6 battery for
the analog part of TDC. The result does not show improvement. So I think
LDO might not be the primary noise contributor.
Thanks for the suggestion.
2015-01-03 22:01 GMT+08:00 Neil Schroeder gign...@gmail.com:
I
Charles Steinmetz csteinmetz@... writes:
Actually, I dont want to ask my colledge for help. Everytime ,for
each
guy I ask for help, I need expain the entire system and principle of
a
frequency counter to him. They just keep asking questions instead of
answering mine.
In defense of
Hi
On Jan 5, 2015, at 6:33 PM, Li Ang lll...@gmail.com wrote:
Hi Bob,
There are 2 oscillator on board, one 8MHz for MCU one 125MHz for FPGA.
I've took it down from the board, and changed MCU to use internal RC
oscillator for MCU and PLL to mutilply refclk to 200MHz for FPGA.
I will try
Hi,
If you have a stable delay of 198 ns, and we can't figure out why it is
bad, bad, bad, then just calibrate it and compensate for it.
I would be curious to figure out where it is. I don't have the full
system insight right now. It sounds like you need two coarse count
cycles (I think you
Hi
On Jan 5, 2015, at 6:26 PM, Li Ang lll...@gmail.com wrote:
Hi
I've confirmed that it's 198ns between start and stop with my racal dana
1992. I've spent days to learn how to compensate this 2ns in Quartus.
However, it's not something easy for me to do.
It’s not something that anybody
Actually, I dont want to ask my colledge for help. Everytime ,for each
guy I ask for help, I need expain the entire system and principle of a
frequency counter to him. They just keep asking questions instead of
answering mine.
In defense of the hardware guys, there are a lot of questions
Hi Magnus
You are right, I could compensate it in the software. I've tried that.
The software sets sig=ref=10MHz and measures start-to-stop time t1. Then,
it sets sig=ref=5MHz and measures time t2. With t1 t2, I could get the
time difference between the start path and the stop path. Repeat it
Hi Bob,
Actually, I dont want to ask my colledge for help. Everytime ,for each
guy I ask for help, I need expain the entire system and principle of a
frequency counter to him. They just keep asking questions instead of
answering mine. :(
The 2 MV89As are powered by the same power supply
Hi
I've confirmed that it's 198ns between start and stop with my racal dana
1992. I've spent days to learn how to compensate this 2ns in Quartus.
However, it's not something easy for me to do. I will ask some
hardware colleague for help.
Two days ago, I assembled my 2 mv89a to PCB ,put them
Hi Bob,
There are 2 oscillator on board, one 8MHz for MCU one 125MHz for FPGA.
I've took it down from the board, and changed MCU to use internal RC
oscillator for MCU and PLL to mutilply refclk to 200MHz for FPGA.
I will try do the same test tonight thanks.
2014-12-29 4:35 GMT+08:00 Bob Camp
hi Neil,
TPS79333 is quite cheap and adm7150 is 60 times the price of it. These 2
ldo has different package, it not easy to replace it directly. I have tried
power the system with 18650 battery, the performace is almost the same with
5v from laptop USB port. So I think psrr might not be a issue.
I would reconsider the LDOs while you have some time to play with them.
The TPS79333DBVR is not even remotely ultralow noise at most offsets,
despite what TI may say.
For 5V5 and under up to about 600ma, I would suggest you take a look at the
ADM7155 (adjustable) or ADM7154 (fixed). If you need
Hi Magnus
Thanks for the detailed information.
btw, I've found an easier way to get histogram : sort tdc_test.txt |
uniq -c
2014-12-31 23:37 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org:
Hi,
First I did a statistical histogram simply by counting how many times a
Hi,
Yes, that is a much quicker approach.
Bit of warning, I might have an error in the details of re-creating the
expected histogram, that was done in haste. I might have to correct that
eventually, but it shows the principle.
I also did not add plots of the histogram, estimated histogram
Hi Magnus,
I'm not familar with error analysis and statistics, can you tell me how
to calculate the jitter with my data? Can you tell me some articles or
tutorials about the calculation that a time-nut usually use? I want to
learn stuffs. :)
Thanks.
2014-12-29 21:58 GMT+08:00 Magnus
Hi,
First I did a statistical histogram simply by counting how many times a
particular delay measure occurred, thus creating bins of occurrence
count for each value. I did this by doing
grep 1.987 tdc_test.txt | wc -l
648
So, the 1.987 bin has a count of 648.
I sent you the full histogram
Hi,
Some quick statistic-processing.
Histogram of your data:
1.979 0
1.980 2
1.98146
1.982 173
1.983 523
1.984 1031
1.985 1301
1.986 1131
1.987 648
1.988 236
1.989 8
1.990 1
1.991 0
The total sample count is 5100 (wc -l only gives 5099 since there is a
Hi Magnus,
The unit of these data is not ns but reference clock cycles (100ns).
TDC_GP22 measures the time between the edge of tdc_start and
tdc_stop1, then it measures the reference clock automaticly. The result you
get from it is the ratio of them.
2014-12-29 19:58 GMT+08:00 Magnus Danielson
Hi,
Darn, not reading all the notes. Again.
Well, in that case, scaling should be done... then you get average of
198,5075 ns and 149,8 ps RMS jitter, with 1,1 ns peak-to-peak.
The jitter is okish then, but a little better would indeed be nice.
Cheers,
Magnus
On 12/29/2014 01:55 PM, Li Ang
Hi
On Dec 29, 2014, at 7:55 AM, Li Ang lll...@gmail.com wrote:
Hi Magnus,
The unit of these data is not ns but reference clock cycles (100ns).
TDC_GP22 measures the time between the edge of tdc_start and
tdc_stop1, then it measures the reference clock automaticly. The result you
get
One way to somewhat decouple the channels cross-talk could be do delay
one of them with a coax cable.
This will make the cross-talk of the early channel die out pretty much
before the next edge come.
With two asynchronous sources you will sweep over the repeating pattern
of cross-talk and
Hi
On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
Hi Bob,
I did some test according to your suggestions. DUT is a symmetricom x72
rb oscillator. Also, I've tried signal generator as the DUT. RS SMY01 is
not as good as HP8662A but that the best I've got. The signal geneator
Hi,
On 12/28/2014 09:35 PM, Bob Camp wrote:
Hi
On Dec 28, 2014, at 9:19 AM, Li Ang lll...@gmail.com wrote:
There 2 issues from the test:
1) As we can see from the data, the number is around 1.98x not 2.00x. So
there is about 2ns delay between tdc_start and tdc_stop1 for this simple
test
Hi Bob,
You are right. My analog circuit skill is so limited, I need to be
realistic. I will make some modification to the circuit according to the
suggestions from you guys when new board is going to make. I've sent the
MV89A board to the factory and got 2 3db attenuators from minicircuit.
Hi Charles,
In my circuit, the VCC is 5v. I've noticed my bias and emitter resistor
is something need to be changed. I will play with the resistors and see if
it improves. Thanks.
2014-12-27 6:42 GMT+08:00 Charles Steinmetz csteinm...@yandex.com:
Li Ang wrote:
RF pnp transistor is harder
Hi Bob,
Here is the data and test scheme.
It does not show much difference.
2014-12-26 22:12 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
Don’t go to crazy on the front end. You can spend a year optimizing
something like this. The objective is to see if the front end is a big
problem now. It’s
Hi
(In reply to several posts. It’s easier for me this way)
Ok, that’s good news !!! (and useful data)
Your counter performance degraded a bit when you put in 5 db and not much when
you put in 8 db.
It’s also maybe *too* good news. I suspect that cross talk between the channels
may be
Hi
Thanks for the suggestion. I will do some experiments with the front
end :)
2014-12-25 4:32 GMT+08:00 Bob Camp kb...@n1k.org:
Hi
Very interesting !! Thanks for sharing.
As you can see from the Fluke schematics, the input amplifiers on counters
can get quite complex. I would
Hi Charles Bruce
I'm not good at analog circuits. My circuit is modified from wenzel's,
since RF pnp transistor is harder to get. I would like the front end works
at 300MHz.
My questions:
1) why the difference of DC bias of the 2 NPN matters? I thought only the
frequency part is useful to a
Hi,
On 12/26/2014 02:38 PM, Li Ang wrote:
Hi Charles Bruce
I'm not good at analog circuits. My circuit is modified from wenzel's,
since RF pnp transistor is harder to get. I would like the front end works
at 300MHz.
My questions:
1) why the difference of DC bias of the 2 NPN matters? I
Hi
Don’t go to crazy on the front end. You can spend a year optimizing something
like this. The objective is to see if the front end is a big problem now. It’s
very easy to get to many things going on in a project. That makes it hard to
complete.
All front end circuits will work better with
Hi
On Dec 26, 2014, at 9:21 AM, Magnus Danielson mag...@rubidium.dyndns.org
wrote:
Hi,
On 12/26/2014 02:38 PM, Li Ang wrote:
Hi Charles Bruce
I'm not good at analog circuits. My circuit is modified from wenzel's,
since RF pnp transistor is harder to get. I would like the front
Li Ang wrote:
RF pnp transistor is harder to get. I would like the front end works
at 300MHz.
My questions:
1) why the difference of DC bias of the 2 NPN matters? I thought only the
frequency part is useful to a counter, amplitude information is useless
right?
You want the circuit to switch
http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf this is my current board.
I'm not a hardware guy, feel free to correct my mistakes. :)
http://assets.fluke.com/manuals/6690smeng.pdf schematic of cnt90
aka pm6690
Happy holidays
Li Ang
___
Li
I had not been following the thread and for some reason followed your links.
Very nice to see your work.
Regards
Paul
WB8TSL
On Wed, Dec 24, 2014 at 11:19 AM, Li Ang lll...@gmail.com wrote:
http://www.qsl.net/bi7lnq/freqcnt_bi7lnq_v4.pdf this is my current board.
I'm not a hardware guy,
Hi
Very interesting !! Thanks for sharing.
As you can see from the Fluke schematics, the input amplifiers on counters can
get quite complex. I would definitely recommend playing a bit with the input
channels on your board. Here’s what I would do, there are many other approaches:
1) Set up a
The CLK1 input circuit produces an output incompatiblr with the 3.3V CMOS deice
it drives.A pair of pnp transistors in an otherwise similar circuit is capable
of producing a 3.3V CMOS compatible output signal.
Using independent voltage dividers to bias the transistor bases is a bad idea
in that
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