Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
--
It is vain to do with more that which can be done with less.
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Von: Stephen Farthing squir...@gmail.com
Betreff: [time-nuts] what is the best way to multiply a 10 Mhz signal?
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
I did 5 MHz * 7 = 35 which is about the same, with CMOS gates and
I'm certainly not the expert but can't you place a divide by 7 counter
in the feedback loop of a phase lock loop. There is a fast version
of the 4046 PPL chip that does 100Mhz and a divide by 7 is easy to
rig with TTL.
On Tue, Dec 21, 2010 at 8:35 AM, Stephen Farthing squir...@gmail.com
On 21/12/10 16:35, Stephen Farthing wrote:
Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
What is the application? What will the DDS output frequency be?
Maybe you could use a 70MHz (or whatever
I used to be in the synthesizer business (Zeta Labs)
in a previous life. I learned to ask the customers:
what you are trying to accomplish as the end goal,
before tackling a messy problem like multiplying by
7. Maybe you don't need to multiply by 7, but we
can't tell from your question.
Rick
Interesting. When I used to use and build DDSs back in the early 70's, we
typically used 2.56 times the maximum required frequency for a clock, to get
above Nyquist and allow adequate filtering stop-band rejection. At the time
we could not go much higher due to limitations in device speeds,
This might explain a way to do it
http://physics.eou.edu/courses/phys345/lab14_pll.pdf
What this is doing is simple. It is a 70Mhz voltage controlled oscillator
who's frequency is controlled such that every 7th cycle the phase matches
your 10MHz reference. The example above does divide by 10 or
You may want to check out the 10MHz locked 1GHz clock I did
(using ADF4107 and a 1GHz Crystek CVCO)
http://www.qslnet.de/member/on4iy/1gclock/xlock-1g.html
and associated DDS to generate oddbal frequencies.
http://www.qslnet.de/member/on4iy/9912.html
Includes some PN measurements.
Xtof.
On
Christophe Huygens wrote:
I'll bet your DDS will run at 80 MHz at room temp.
Since this a one-off project, test it to see if it
works to 80 MHz with some design margin. Now you
can cascade 3 doublers. The reconstruction filter
is now stop 50, pass 30 instead of stop 40 pass 30.
That is WAY
