Re: [time-nuts] Thunderbolt tuning DAC theory of operation
On a later version, the Trimble/Nortel 45k, there are a few obvious HW differences (lousy Rx, bigger FPGA - XC5204, second Flash EEPROM). The PWM is generated differentially (better CMR) in the FPGA (output on pins 12, 13) registered, synchronously with the squared OCXO output signal to reduce jitter, in the 74AC174 on D0, and D1 (input on pins 3, 4), which is being supplied with a stabilized voltage from the LT1021-5 reference through one section of the quad Op Amp LT1014, and a series transistor. Those operations (jitter minimization and clean supply voltage) are crucial to the quality of the PWM signal. While the operation is obviously by PWM modulating the 102.4us period (10MHz/2^10) signal by the 10MSBs, the processing of the 10LSBs is less so. The PWM signal is dithered, by a ripple minimizing pattern, with a periodicity of 1024 pulses (104.8576ms = 1/10MHz/10^20), giving the DAC a full 20bit monotonic resolution. On 11/2/2013 10:41 AM, Stewart Cobb wrote: While poking around the Thunderbolt to determine whether -5V could be used in place of -12V, I discovered how the OCXO tuning DAC works. Apologies if this is old news, but I haven't seen it documented before. The 10MHz sine wave from the OCXO is squared up and used to clock the Xilinx 5200 CPLD (U22) and a 74AC174 hex D flip-flop (U14). Inside the CPLD (apparently) the 10 MHz clock is divided by 1024, giving a square wave with a period of 102.4 us (about 9.7 kHz). The duty cycle of that square wave is modulated by the 10 MSBs of the commanded DAC value. The LSBs are used to offset the falling edge of the square wave one clock cycle (100 ns) later, during a fraction of the 9.7 kHz square waves proportional to the LSBs value. On a modern digital scope, you can zoom in on the falling edge of the square wave, set the display to average, and see that the averaged height of that clock cycle is proportional to the DAC LSBs. There appear to be at least 8 LSBs, perhaps as many as 10, giving a total DAC resolution of 18 to 20 bits. (If the DAC value is averaged over one second, there are 10^7 clock cycles which can be controlled, giving a theoretical maximum resolution of 23+ bits. Trimble may have chosen a shorter averaging time and fewer bits.) The PWM square wave travels from pin 13 of the CPLD (U22) to pin 4, the D1 input of the 74AC174 (U14). The flip-flops in this chip are also clocked by the squared-up 10 MHz from the OCXO. The Q1 output, pin 5 of U14, goes to one side of R83 in the circuitry around the LT1014 op-amp. The other five inputs and outputs of U14 are constantly high or low. They may also be fed to the op-amp circuits, to help it handle the square wave in a purely ratiometric manner. The inputs and outputs of the Xilinx CPLD can be programmed for many different I/O standards. Unfortunately, this makes their output pin drivers far from ideal. The purpose of the 74AC174 is presumably to drive the analog circuitry with a input that is as close as possible to a mathematically ideal digital signal. Outputs in the 74AC logic family can source or sink 24 mA and have relatively balanced raise and fall times. This was probably the most ideal digital output available to the Thunderbolt's designers in the late '90s. This DAC implementation is guaranteed monotonic, an important consideration. There is exactly one rising edge and one falling edge per cycle, so that any difference between rise and fall times will have a constant effect which can be tuned out. Unlike a sigma-delta DAC, this PWM DAC produces strong spectral lines at multiples of the 9.7 kHz square wave frequency. On the one hand, it is comparatively easy to design filters to remove a single frequency (and its harmonics). On the other hand, this signal is strong enough that it may appear in phase noise plots anyway. If you want to view the 9.7 kHz square wave for yourself, it appears on a small square test point next to the silkscreen designator for C78, very close to the 6-pin power input jack. This test point is part of the connection from the Xilinx CPLD to the hex D flip-flop. Probing it does not affect the OCXO tuning. Hope this helps. Cheers! --Stu ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Thunderbolt 1pps
I may have posted this link before. It is on topic, even though I was using coax cable: http://ko4bb.com/Test_Equipment/CoaxCableMatching.php It would be easy to do the same experiment with cat-5 cable. I would expect the pictures to look somewhat similar. Didier KO4BB Tom Van Baak t...@leapsecond.com wrote: Pulse quality of single-ended RS232 over unbalanced twisted pair is going to be pretty bad beyond a few feet. If you want to transport the 1pps over twisted pair there are a couple of options: Hi Brian, I suspect this is true at one level, but what would be helpful to to *quantify* it. What is pretty bad? What is few feet? You are implying that 1PPS timing is dependent in cable quality and cable length. I would agree. But please provide some numbers, even rough numbers, because what is important for modern TF applications (picoseconds and nanoseconds) can be irrelevant for NTP, which still lives in the millisecond and microsecond world. What I'd like to see, and what would be educational for the group, is if you could take some 'scope traces at a few inches, at a few feet, and at a few meters or tens of feet to graphically demonstrate your pont. My gut tells me 1 ns or 10 ns or 100 ns or 1 us or 10 us makes no measureable difference to the quality of NTP/PC timekeeping. /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Sent from my Motorola Droid Razr 4G LTE wireless tracker while I do other things. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Trimble Studio, what is it?
05/01/2014 10:57 I see occasional references to Trimble Studio here. What is it please? An alternative to Lady Heather for Thunderbolts, or have I missed the plot entirely? Thanks. -- Best Regards, Chris Wilson. mailto: ch...@chriswilson.tv ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Studio, what is it?
On Sun, Jan 5, 2014 at 4:58 AM, Chris Wilson ch...@chriswilson.tv wrote: 05/01/2014 10:57 I see occasional references to Trimble Studio here. What is it please? An alternative to Lady Heather for Thunderbolts, or have I missed the plot entirely? Thanks. I just picked up a copy based on a posting here a few days ago. It appears to be an updated replacement for Tboltmon but works for all of their products. Grab a copy from Trimble and run it to see if you like it. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 br...@lloyd.com +1.916.877.5067 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Studio, what is it?
Hi Chris, I see occasional references to Trimble Studio here. What is it please? For a list of features, see: http://www.wavedigm.com/xe/studio That page also has a Users Guide and the application itself. regards Zim ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Studio, what is it?
I found it here and the FTDI USB serial bus driver and the manuals. http://www.sectron.eu/products/3-results-of-finding/1558-trimble-gps-studio-for-download.html I haven't tried it yet. Dave - Original Message - From: Graeme Zimmer To: Chris Wilson ; Discussion of precise time and frequency measurement Sent: Sunday, January 05, 2014 7:49 AM Subject: Re: [time-nuts] Trimble Studio, what is it? Hi Chris, I see occasional references to Trimble Studio here. What is it please? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Studio, what is it?
I found it here and the FTDI USB serial bus driver and the manuals. http://www.sectron.eu/products/3-results-of-finding/1558-trimble-gps-studio-for-download.html I haven't tried it yet. Dave 05/01/2014 16:21 Thanks Graeme, Bryan and Dave, I have it downloaded, will have a play with it later, much appreciated. -- Best Regards, Chris Wilson. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] WWV/WWVH audio simulator?
Hi, Wow, those recordings are very interesting! Late in that series, there's one which sounds like a direct feed of WWVH for a few minutes. This really points out what all is lost by the time the signal gets to air. The phone services aren't much better, since everything above 4KHZ is lost, and at least the WWV phone number (+1 303-499-7111) has some sort of highpass filter on it or something so you don't get the full fidelity of the broadcast, in particular, you don't hear much of the 100HZ timecode. Jayson On 1/5/2014 2:05 AM, Peter Monta wrote: Hi Jayson, You may already be aware of it, but there's a set of historical recordings of WWV and WWVH, covering 1955 to 2005: http://www.myke.me/atthetone/ As for the simulation, I'm sure it would be easy to do the tones and clicks, but the voice announcements would need a considerable amount of cut-and-paste from high-quality recordings. One possibility is to find someone in Boulder, send that person a platform consisting of a shortwave receiver and a recorder with Internet connectivity (e.g. Raspberry Pi plus a cellphone stick), set the device on a rooftop, have it acquire a few days of audio, then upload the audio back to you. Cheers, Peter ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] WWV/WWVH audio simulator?
Replicating the WWV/WWVB audio is impractical given the various weather and other timely messages. One could use the Linux festival voice syntheses package, which gives a choice of voices. On 01/05/2014 07:50 AM, Jayson Smith wrote: Hi, Wow, those recordings are very interesting! Late in that series, there's one which sounds like a direct feed of WWVH for a few minutes. This really points out what all is lost by the time the signal gets to air. The phone services aren't much better, since everything above 4KHZ is lost, and at least the WWV phone number (+1 303-499-7111) has some sort of highpass filter on it or something so you don't get the full fidelity of the broadcast, in particular, you don't hear much of the 100HZ timecode. Jayson On 1/5/2014 2:05 AM, Peter Monta wrote: Hi Jayson, You may already be aware of it, but there's a set of historical recordings of WWV and WWVH, covering 1955 to 2005: http://www.myke.me/atthetone/ As for the simulation, I'm sure it would be easy to do the tones and clicks, but the voice announcements would need a considerable amount of cut-and-paste from high-quality recordings. One possibility is to find someone in Boulder, send that person a platform consisting of a shortwave receiver and a recorder with Internet connectivity (e.g. Raspberry Pi plus a cellphone stick), set the device on a rooftop, have it acquire a few days of audio, then upload the audio back to you. Cheers, Peter ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Chuck Forsberg WA7KGX c...@omen.com www.omen.com Developer of Industrial ZMODEM(Tm) for Embedded Applications Omen Technology Inc The High Reliability Software 10255 NW Old Cornelius Pass Portland OR 97231 503-614-0430 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] HP 5065A serial number list
Corby, my 5065A has s/n 2816A01605 John W Cress K0GCJ -- Original Message -- From: cdel...@juno.com To: time-nuts@febo.com Subject: [time-nuts] HP 5065A serial number list Date: Tue, 31 Dec 2013 10:57:33 -0800 As promised here is a list of all the HP 5065A units I have come across. I believe there should be a 08xx prefix out there as the units first came out in the middle of 1968. I also think that the 2816A prefix is the last prefix used. Anyone have any others I can add to the list? Another tidbit, the latest optical unit warrenty date I have seen is 1993. Known HP5065A serial numbers 0916-00181 2816A01556 0928-2816A01554 0940-00203 2816A01565 0960A00285 2816A01566 0960A00312 2816A01567 0960A00313 2816A01591 0968A00312 2816A01596 1104A00376 2816A01617 1220A00422 2816A01618 1220A00426 2816A01636 1220A00444 2816A01640 1220A00448 2816A01645 1220A00463 2816A01652 1320A00492 2816A01658 1340A00519 2816A01666 1340A00521 2816A01674 1340A00528 2816A01677 1416A 2816A01688 1420A00613 2816A01693 1420A00651 2816A01697 1532A00725 1736A 1908A00853 1908A00910 2112A01035 2144A01088 2216A01121 2232A01149 2320A01200 2340A01200 2340A01235 2340A01290 2432A01332 2432A01338 2432A01380 2432A01400 2432A01430 2614A01514 2632A01463 2644A01471 2740A01547 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Do THIS before eating carbs #40;every time#41; 1 EASY tip to increase fat-burning, lower blood sugar decrease fat storage http://thirdpartyoffers.juno.com/TGL3131/52c9ad6aa55822d6a5365st01duc ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] WWV/WWVH audio simulator?
This is by design The POTS (Plain Old Telephone System) specifies a bandwidth of 300Hz to 3,400Hz. http://en.wikipedia.org/wiki/Plain_old_telephone_service They are trying to cram as many channels into as little bandwidth as possible and the greater the frequency response they provide, the more bandwidth it takkes and the fewer channels they can provide. T1 lines were originally developed to bring 16 voice channels into a building that didn't have enough copper circuits. Dave -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Jayson Smith Sent: Sunday, January 05, 2014 07:51 To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] WWV/WWVH audio simulator? Hi, Wow, those recordings are very interesting! Late in that series, there's one which sounds like a direct feed of WWVH for a few minutes. This really points out what all is lost by the time the signal gets to air. The phone services aren't much better, since everything above 4KHZ is lost, and at least the WWV phone number (+1 303-499-7111) has some sort of highpass filter on it or something so you don't get the full fidelity of the broadcast, in particular, you don't hear much of the 100HZ timecode. Jayson On 1/5/2014 2:05 AM, Peter Monta wrote: Hi Jayson, ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] WWV/WWVH audio simulator?
The US POTS is digitized at 8KHz sample rate, so Nyquist says the highest frequency you can accurately digitize is 4KHz. Allow some for a (fancy digital) filter and 3400Hz is about the best you can expect. As for T1, almost right. The 8K samples per second are u-law processed to 8 bits each for transmission down the line, at 1.544 Mb/s a T1 line handles 24 streams, plus 8K bits per second of supervisory data. Yes, a nice round 193 bits per frame. Bob LaJeunesse From: DaveH i...@blackmountainforge.com To: 'Discussion of precise time and frequency measurement' time-nuts@febo.com Sent: Sunday, January 5, 2014 1:53 PM Subject: Re: [time-nuts] WWV/WWVH audio simulator? This is by design The POTS (Plain Old Telephone System) specifies a bandwidth of 300Hz to 3,400Hz. http://en.wikipedia.org/wiki/Plain_old_telephone_service They are trying to cram as many channels into as little bandwidth as possible and the greater the frequency response they provide, the more bandwidth it takkes and the fewer channels they can provide. T1 lines were originally developed to bring 16 voice channels into a building that didn't have enough copper circuits. Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] WWV/WWVH audio simulator?
DERP -- you are right. T1 does 24 voice channels, not 16. Thanks for the heads up! Dave -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Robert LaJeunesse Sent: Sunday, January 05, 2014 11:33 To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] WWV/WWVH audio simulator? The US POTS is digitized at 8KHz sample rate, so Nyquist says the highest frequency you can accurately digitize is 4KHz. Allow some for a (fancy digital) filter and 3400Hz is about the best you can expect. As for T1, almost right. The 8K samples per second are u-law processed to 8 bits each for transmission down the line, at 1.544 Mb/s a T1 line handles 24 streams, plus 8K bits per second of supervisory data. Yes, a nice round 193 bits per frame. Bob LaJeunesse From: DaveH i...@blackmountainforge.com To: 'Discussion of precise time and frequency measurement' time-nuts@febo.com Sent: Sunday, January 5, 2014 1:53 PM Subject: Re: [time-nuts] WWV/WWVH audio simulator? This is by design The POTS (Plain Old Telephone System) specifies a bandwidth of 300Hz to 3,400Hz. http://en.wikipedia.org/wiki/Plain_old_telephone_service They are trying to cram as many channels into as little bandwidth as possible and the greater the frequency response they provide, the more bandwidth it takkes and the fewer channels they can provide. T1 lines were originally developed to bring 16 voice channels into a building that didn't have enough copper circuits. Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Trimble Thunderbolt 1pps
att...@kinali.ch said: Also keep in mind that RS-232 relies on the voltage going negative to encode a 1. I.e. getting 0V is not enough and might only work by chance with some RS-232 receivers. I think there are 2 parts to this discussion. What do the specs say, and what actually happens in the real world? I think the specs say that -3 to +3 is no mans land. A valid signal must be over +3 or under -3. In practice, the receiver chip only has one power supply. It would take extra work to make the switching threshold below ground. There is an additional quirk in here. The original Motorola MC1489 had a switching threshold of a diode drop (and some hysteresis). That chip was very popular and turned into a defacto standard. If you built a RS-232 receiver chip that required a negative input voltage, all sorts of obscure things would break and anybody who used it would have support nightmares. [1] The typical RS-232 receiver chips actually have good specs. In particular they spec the transition voltages in each direction. TI Data sheet for MC1489(A) and SN75189(A) http://www.ti.com/lit/ds/symlink/mc1489a.pdf TI Data sheet for MAX232 http://www.ti.com/lit/ds/symlink/max232.pdf --- Many years ago (early 1980s?), there was a popular brand of modems that sent out a TTL level rather than real RS-232 levels. Yes, we found that the hard way when we cut a corner. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 'CPLDs for clock dividers' Thread
Hello All, I was looking at the archives - what was the outcome of this: Thanks to everyone for their advice. I bought a CoolRunner II development board (only $39!) and will let you know how it goes. Matt On Wed, Feb 3, 2010 at 10:59 AM, Matt Ettus boyscout at gmail.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts wrote: * Does anyone have any experience using CPLDs for very low phase noise ** dividers? You can get an XC9536XL from Xilinx for around $1, and I ** thought it would make a good divide by 2 through 10 device. ** Matt* A lot of the discussion focused on the difficulties of downloading the tools for Altera or Xilinx - the Max II family from Altera was recommended - but there was no apparent outcome or resolution to this thread - seemingly. Does anyone have that CPLD recommendation? Thanks, John Westmoreland ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 'CPLDs for clock dividers' Thread
I was looking at the archives - what was the outcome of this: What level of nuttiness are you interested in? CPLDs or FPGAs are neat because you can toss all sorts of stuff into them. If you do that, you introduce opportunities for power supply level noise coupling. If you have something simple like a divide by 2 or divide by 10 with no other logic in the chip, I'd expect the output to be clean. If you want to do a divide by 2 AND 10, I'll bet you will see some coupling. (at least if you look hard enough) Fine print: One buzzword to look for is SSO - Simultaneous Switching Output. The basic idea is that there is slight inductance/resistance in the power/ground connections and on chip power/ground distribution. If 2 signals switch at the same time, they share that and will be slightly slower than only one signal switching. You will probably get better results if your output PIN is next to pwr/gnd pins. (lower on-chip resistance) You may be able to help things by setting up nearby pins as outputs and wiring those pins to pwr/gnd and driving them with the appropriate logic level. The idea is to add semi-pwr pins. The resitance through the driver transistors is small enough so that it helps. It would be fun to measure some of that stuff. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 'CPLDs for clock dividers' Thread
I am working on a PLL design that uses the Lattice MX02-256 for the dividers and XOR phase detector. I have not made any measurements on it yet but will report back when it happens. On 1/5/2014 7:37 PM, Hal Murray wrote: I was looking at the archives - what was the outcome of this: What level of nuttiness are you interested in? CPLDs or FPGAs are neat because you can toss all sorts of stuff into them. If you do that, you introduce opportunities for power supply level noise coupling. If you have something simple like a divide by 2 or divide by 10 with no other logic in the chip, I'd expect the output to be clean. If you want to do a divide by 2 AND 10, I'll bet you will see some coupling. (at least if you look hard enough) Fine print: One buzzword to look for is SSO - Simultaneous Switching Output. The basic idea is that there is slight inductance/resistance in the power/ground connections and on chip power/ground distribution. If 2 signals switch at the same time, they share that and will be slightly slower than only one signal switching. You will probably get better results if your output PIN is next to pwr/gnd pins. (lower on-chip resistance) You may be able to help things by setting up nearby pins as outputs and wiring those pins to pwr/gnd and driving them with the appropriate logic level. The idea is to add semi-pwr pins. The resitance through the driver transistors is small enough so that it helps. It would be fun to measure some of that stuff. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 'CPLDs for clock dividers' Thread
Hello Tom, Thanks for replying. I will be interested to see what you end up with for jitter, phase noise, and propagation delay; to name a few. Looks like an interesting part from the datasheet. Thanks, John W. On Sun, Jan 5, 2014 at 8:29 PM, Tom Minnis tom_min...@att.net wrote: I am working on a PLL design that uses the Lattice MX02-256 for the dividers and XOR phase detector. I have not made any measurements on it yet but will report back when it happens. On 1/5/2014 7:37 PM, Hal Murray wrote: I was looking at the archives - what was the outcome of this: What level of nuttiness are you interested in? CPLDs or FPGAs are neat because you can toss all sorts of stuff into them. If you do that, you introduce opportunities for power supply level noise coupling. If you have something simple like a divide by 2 or divide by 10 with no other logic in the chip, I'd expect the output to be clean. If you want to do a divide by 2 AND 10, I'll bet you will see some coupling. (at least if you look hard enough) Fine print: One buzzword to look for is SSO - Simultaneous Switching Output. The basic idea is that there is slight inductance/resistance in the power/ground connections and on chip power/ground distribution. If 2 signals switch at the same time, they share that and will be slightly slower than only one signal switching. You will probably get better results if your output PIN is next to pwr/gnd pins. (lower on-chip resistance) You may be able to help things by setting up nearby pins as outputs and wiring those pins to pwr/gnd and driving them with the appropriate logic level. The idea is to add semi-pwr pins. The resitance through the driver transistors is small enough so that it helps. It would be fun to measure some of that stuff. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 'CPLDs for clock dividers' Thread
John, I have tried to incorporate the digital dividers of a linear phase comparator into a CPLD. While it worked in principle as planned I had lots of problems when the slopes of the input signals came close to each other, this being due to CPLDs or FPGAs are neat because you can toss all sorts of stuff into them. If you do that, you introduce opportunities for power supply level noise coupling. The power supply coupling may change the point of time when ONE slope appears at the outpuit of the divider in dependence of when the SECOND slope appears. Of couse this effect is not in the order of microseconds, not even nanaoseconds but say a few hundred picoseconds and thus some orcders of magnitude worse than phase comparator was expected to work. A normal digital designer would not care about it only time nuts do. I am working on a PLL design that uses the Lattice MX02-256 for the dividers and XOR phase detector. I have not made any measurements on it yet but will report back when it happens. A PLL design will give you much less trouble with the following justification: The low pass filter following the XOR phase comparator must have a cut off frequency that is suited to supress the XOR's output frequency (double the PLL's frequency) well enough. ANY kind of disturbance that is superimposed to the XOR's output (jitter, you name it) has basically a higher frequency than the XOR's output itself. SO it will even be better filtered out by the low pass filter. I have done some PLLs in CPLDs without ever getting in trouble. Get yourself the data sheet of the AD9901 frequency/phase comparator. It will show you how to improve the simple XOR with circuitry that makes the comparator also frequency dependend. With this the lock-in range will be the same as the lock range, a feature that is not common for XOR based PLLs. Best regards Ulrich -Ursprungliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John C. Westmoreland, P.E. Gesendet: Montag, 6. Januar 2014 06:17 An: tom_min...@att.net; Discussion of precise time and frequency measurement Betreff: Re: [time-nuts] 'CPLDs for clock dividers' Thread Hello Tom, Thanks for replying. I will be interested to see what you end up with for jitter, phase noise, and propagation delay; to name a few. Looks like an interesting part from the datasheet. Thanks, John W. On Sun, Jan 5, 2014 at 8:29 PM, Tom Minnis tom_min...@att.net wrote: I am working on a PLL design that uses the Lattice MX02-256 for the dividers and XOR phase detector. I have not made any measurements on it yet but will report back when it happens. On 1/5/2014 7:37 PM, Hal Murray wrote: I was looking at the archives - what was the outcome of this: What level of nuttiness are you interested in? CPLDs or FPGAs are neat because you can toss all sorts of stuff into them. If you do that, you introduce opportunities for power supply level noise coupling. If you have something simple like a divide by 2 or divide by 10 with no other logic in the chip, I'd expect the output to be clean. If you want to do a divide by 2 AND 10, I'll bet you will see some coupling. (at least if you look hard enough) Fine print: One buzzword to look for is SSO - Simultaneous Switching Output. The basic idea is that there is slight inductance/resistance in the power/ground connections and on chip power/ground distribution. If 2 signals switch at the same time, they share that and will be slightly slower than only one signal switching. You will probably get better results if your output PIN is next to pwr/gnd pins. (lower on-chip resistance) You may be able to help things by setting up nearby pins as outputs and wiring those pins to pwr/gnd and driving them with the appropriate logic level. The idea is to add semi-pwr pins. The resitance through the driver transistors is small enough so that it helps. It would be fun to measure some of that stuff. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] sand9 TCMO
Hello All, I thought this may be of interest to the group - a start-up company - Sand9 - has developed a temperature controlled MEMS oscillator (TCMO): http://www.sand9.com/product/tcmo/ . Best Regards, John Westmoreland ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
