[time-nuts] more teensy timer stuff

[Jim Lux]

Got the Rb hooked up.
1E-8, 1E-9 kind of AVAR (after linear trend removal) for 10 minute run.


next, we'll try running it clocked at 96 MHz
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Re: [time-nuts] teensy as time capture device

[Poul-Henning Kamp]

In message <5602f65b.6050...@earthlink.net>, Jim Lux writes:

>I've got a teensy3.1 hooked up to a 33120 function generator (not 
>exactly a super stable device) and generating period data for a 1 Hz 
>square wave.

That is actually a particularly bad way of doing it, because the
33120 will generate a sine and run it through a zero-detector.

You get much better performance by defining a ARB function which is
a square.


-- 
Poul-Henning Kamp   | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
FreeBSD committer   | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bill Hawkins]

Perhaps I can do this in words, as I have no schematic software.

Start with the input to your favorite microprocessor's A/D converter.
Connect it to a suitable (more later) capacitor to analog ground.
Connect a cmos switch across the cap and call it S2. When S2 is on, it
discharges the cap.

Now build or buy a constant current generator connected from a suitable
positive voltage to another cmos switch called S1.
When S1 is on, all of the current generated flows to analog ground.

To make it all work, connect the anode of a diode from the junction of
the current source and S1 to the cap and analog input.

When S1 is on, no current gets to the cap. When S1 is off, all of the
current gets to the cap, if S2 is off. This causes a linear buildup of
voltage across the cap, for a suitable time.

When 1 PPS pulses are compared, suitable means one second to charge to
almost the maximum that the micro A/D supports.
The value of I is chosen to overwhelm diode leakage and A/D input
current. The value of C follows.

All that remains for a working system is a pair of flip-flops to control
S1 and S2.
FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
FF1 is on, S1 is off.
FF 2 is set by PPS 1 and cleared by an output from the micro when the
A/D conversion is done. When FF2 is on, S2 is off.

And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
conversion occurs, and be reset to zero volts when the micro is done
processing the input.

This gives the micro a linear conversion of pulse difference time rather
than an RC exponential value.

Feedback controllers do better with linear error signals.

But all of this is wasted if the PPS signals are not accurate due to
things that affect pulse rise and fall times.

If the above was not adequately clear, please ask for clarification. Or
do a schematic and ask for corrections.

Bill Hawkins

P.S. This will not work well for small differences between PPS 1 and 2.
It will work if the goal is 50% difference, or 90 degrees phase shift.


-Original Message-
From: Can Altineller
Sent: Wednesday, September 23, 2015 2:56 AM

%< --

4. I think an analog solution like Bill Hawkins described, would be best
suited for this task. But I have not understood it enough to build it.

Best Regards,
C.A.


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Re: [time-nuts] Z380XA The saga of the aging 10811

[Attila Kinali]

On Tue, 22 Sep 2015 23:49:25 -0400
"Bob Benward"  wrote:

> Continuing this discussion, I have included a PDF showing the past 30days of
> EFC.  Amazingly, the drift has reversed direction!  Anyone have any insights
> into this behavior?  Each data point represents 10 seconds.

Vig and Meeker have written a good paper on aging of quartz crystals[1],
which lists quite of few of the aging mechanisms and references papers
that have studied them. If you cannot access it, a (very short) summary
can be found in Vig's Crystal Oscillator Tutorial [2].


Attila Kinali


[1] "The Agin of Bulk Acoustic Wave Resonators, Filters and Oscillators",
by Vig, Meker, 1991

[2] 
http://ko4bb.com/manuals/index.php?dir=02_GPS_Timing/John_Vig_Tutorials_on_Crystal_Oscillators

-- 
Reading can seriously damage your ignorance.
-- unknown
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[time-nuts] Z3801A expert?

[Ben Hall]

Hey guys,

I suspect we may have a Z3801A expert on the list.

A couple of nights ago, we had a power failure.  GPSCON says that my 
Z3801A has failed self-test, but everything else looks fine:


Self Test: Err
Int Pwr:  OK
Oven Pwr:  OK
OCXO:  OK
EFC:  OK
GPS Rcv:  OK

The whole screen can be seen here:



When I command a self test via *TST? command, it returns 0, which is no 
error.


Not sure why GPSCON is reporting a self test error.  Any advice?  It 
seems to be functioning normally in all respects.  :)


thanks much and 73,
ben, kd5byb
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[time-nuts] Value of parts for the RC network of "GPSDO with 1ns res TIC"

[Can Altineller]

Hello,

I got some 4046 plls and I decided to implement the schematic given on:

https://www.febo.com/pipermail/time-nuts/attachments/20140211/8bdbc232/attachment-0004.jpg

in the drawing phase comparator 3 output is connected to a diode, which
then is fed to a network, and then read from an adc. I see a 1nF capacitor,
but the other 2 parts I can not identify. (I am guessing one is a 1M
resistor, and the other above is some inductor maybe?

Best regards,
C.A.
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Re: [time-nuts] time-nuts Digest, Vol 134, Issue 23

[Bob Benward]

Hi Dan,
I would love to see your data.  3E-12 is very impressive (I assume an
inferred drift from the EFC counts?).  I am really surprised at the
oscillator turn around, nothing changed in my house or in the setup, so I
was surprised to see the sudden dip.  At first I thought the oscillator was
aging in and settling down.  Now I am curious to see what happens in the
next thirty days.

Bob

>>> -Original Message-
>>> From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Dan
>>> Kemppainen
>>> Sent: Wednesday, September 23, 2015 11:02 AM
>>> To: time-nuts@febo.com
>>> Subject: Re: [time-nuts] time-nuts Digest, Vol 134, Issue 23
>>> 
>>> Hi Bob,
>>> 
>>> I have a similar oscillator tied to a GPSDO that another list member is
>>> developing. I have not seen the EFC turn around! That's seems very
unusual.
>>> 
>>> If you are interested, I may be able to give you a plot of my EFC over
the last
>>> ~3000 hours. Pretty boring decay curve, with the oscillator sitting at
around
>>> 3e-12 per day drift. (The oscillator was on for about
>>> 6 months prior to being hooked to the GPSDO...)
>>> 
>>> 
>>> 
>>> Dan
>>> 
>>> 
>>> On 9/23/2015 3:10 AM, time-nuts-requ...@febo.com wrote:
>>> > Date: Tue, 22 Sep 2015 23:49:25 -0400
>>> > From: "Bob Benward"
>>> 
>>> > Continuing this discussion, I have included a PDF showing the past
>>> > 30days of EFC.  Amazingly, the drift has reversed direction!  Anyone
>>> > have any insights into this behavior?  Each data point represents 10
>>> seconds.
>>> >
>>> > Bob
>>> ___
>>> time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
>>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>> and follow the instructions there.
>>> -
>>> No virus found in this message.
>>> Checked by AVG - www.avg.com
>>> Version: 2015.0.6140 / Virus Database: 4419/10665 - Release Date:
>>> 09/19/15

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[time-nuts] Symmetricom experts?

[G1FEF]

Do we have any Symmetricom experts on this list?

I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock running for 
several years until we had a power cut and the UPS battery failed, on powering 
back up it won't boot at all.

I suspect the flash is corrupt but they protect it in some way, so one can't 
just copy the o/s onto a new card, and the company want 's to fix it for me!

Thanks in advance,
Chris


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Re: [time-nuts] Symmetricom experts?

[Anders Wallin]

FWIW our SyncServer S250 has a PSU with an electrolytic cap that has failed
at least twice over the years:
http://www.anderswallin.net/2015/08/psu-electrolytic-cap-fix/

Anders

On Thu, Sep 24, 2015 at 10:21 AM, G1FEF  wrote:

> Do we have any Symmetricom experts on this list?
>
> I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock running
> for several years until we had a power cut and the UPS battery failed, on
> powering back up it won't boot at all.
>
> I suspect the flash is corrupt but they protect it in some way, so one
> can't just copy the o/s onto a new card, and the company want 's to fix
> it for me!
>
> Thanks in advance,
> Chris
>
>
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Re: [time-nuts] first teensy3.1 data

[Jim Lux]

On 9/23/15 2:50 PM, Magnus Danielson wrote:

Jim,

There is some systematic bumps in there which make me wonder what
happens here. Care to share data/plots for phase?


Sure..
This is just the part sitting on my desk with the source hooked up with 
clip leads. The run is very short (5-10 minutes) so there's, at the 
least, some thermal effects.



Over that 10 minutes, with the Rb, the frequency slowly decreases (about 
0.1 ppm over that time span).


This thing is also powered off the USB from the computer it's hooked up 
to, and the environment is hardly quiet.


I'll get some data files and a better test setup.



You want to understand the systematics when it looks like that.

Cheers,
Magnus

On 09/23/2015 09:09 PM, Jim Lux wrote:

a bit more than 5 minutes of data.

Now to go get a real 1pps source that's decent.


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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bob Camp]

Hi

Simple approach:

Use a pair of tri-state buffers. 

Both have their outputs hooked to the cap through resistors.

One (call it A) has its signal input grounded. The other (call it B) has
its signal input tied high. Both of the tri-state controls normal sit in the 
“off” (= output is tri-state) condition. 

When I turn A on, the cap discharges. If instead, I turn B on, the cap 
charges. If neither is on, the cap changes voltage only due to leakage
current. 

Let’s say I have a long R/C on A and simply use it to discharge the cap 
to zero. It’s there only to set a starting value on the cap. The R/C could be
just about anything. 

Let’s also say that I feed a variable width pulse into B. While the pulse has
the gate control “on” the cap charges. The voltage on the cap is proportional to
the well known R/C time constant formula and the width of the pulse. 

Once the pulse is gone, I fire up the A/D and read the voltage. After I have
the voltage I put the cap back to ground with A. 



So what can go wrong?

1) I have the cap in the “both gates off” state to long and all I’m 
reading is the impact of leakage current.

2) My pulse is to wide and the R/C maxes out.

3) My pulse is long enough that my resolution goes below my desired
resolution target. 

4) The resistance is low enough that the gate output R gets into the 
act.

5) The C is so small that trace stray C (and input C’s) get into the act. 

6) The current into the R is so high that the gate current limits at the 
start of the charge cycle. 

7) The caps or resistors are not stable so the system is not repeatable. 

8) Your ADC has some pathogenic thing it does when it converts that shorts
the cap to ground. ( = you have a really weird ADC). 

Except for leakage current, everything is controllable in the design. Some
of the stuff above can be modeled (or measured) to minimize it’s impact. There
are more subtle issues like the fact that the gate has a different propagation 
delay
low to high than high to low. That will stretch the pulse a bit. If you get 
really fast
on the pulse, the output of the gate gets into the act a couple of ways. 

Bob


> On Sep 24, 2015, at 2:31 AM, Bill Hawkins  wrote:
> 
> Perhaps I can do this in words, as I have no schematic software.
> 
> Start with the input to your favorite microprocessor's A/D converter.
> Connect it to a suitable (more later) capacitor to analog ground.
> Connect a cmos switch across the cap and call it S2. When S2 is on, it
> discharges the cap.
> 
> Now build or buy a constant current generator connected from a suitable
> positive voltage to another cmos switch called S1.
> When S1 is on, all of the current generated flows to analog ground.
> 
> To make it all work, connect the anode of a diode from the junction of
> the current source and S1 to the cap and analog input.
> 
> When S1 is on, no current gets to the cap. When S1 is off, all of the
> current gets to the cap, if S2 is off. This causes a linear buildup of
> voltage across the cap, for a suitable time.
> 
> When 1 PPS pulses are compared, suitable means one second to charge to
> almost the maximum that the micro A/D supports.
> The value of I is chosen to overwhelm diode leakage and A/D input
> current. The value of C follows.
> 
> All that remains for a working system is a pair of flip-flops to control
> S1 and S2.
> FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
> FF1 is on, S1 is off.
> FF 2 is set by PPS 1 and cleared by an output from the micro when the
> A/D conversion is done. When FF2 is on, S2 is off.
> 
> And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
> conversion occurs, and be reset to zero volts when the micro is done
> processing the input.
> 
> This gives the micro a linear conversion of pulse difference time rather
> than an RC exponential value.
> 
> Feedback controllers do better with linear error signals.
> 
> But all of this is wasted if the PPS signals are not accurate due to
> things that affect pulse rise and fall times.
> 
> If the above was not adequately clear, please ask for clarification. Or
> do a schematic and ask for corrections.
> 
> Bill Hawkins
> 
> P.S. This will not work well for small differences between PPS 1 and 2.
> It will work if the goal is 50% difference, or 90 degrees phase shift.
> 
> 
> -Original Message-
> From: Can Altineller
> Sent: Wednesday, September 23, 2015 2:56 AM
> 
> %< --
> 
> 4. I think an analog solution like Bill Hawkins described, would be best
> suited for this task. But I have not understood it enough to build it.
> 
> Best Regards,
> C.A.
> 
> 
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Re: [time-nuts] Symmetricom experts?

[Mike Cook]

Hi Chrs,
  Not an expert… but usually computer systems give some indication of why a 
boot is failing on the systems console. The S200 is probably a unix based 
system as it has utilities such as SSH. TELNET. HTTP. So you could try 
connecting an RS232 terminal , or telnet’ing to its console server if it is 
managed by one. Then power it on again and see what the symptoms are. If there 
is no output, then it is a probably hardware problem and you will need to 
either have it serviced, or dig into it yourself . I doubt however that it is 
user serviceable.
There are troubleshooting steps in the user manual, so I suggest you look at 
those. If you don’t have the manual handy, see


Have fun
Mike

> Le 24 sept. 2015 à 09:21, G1FEF  a écrit :
> 
> Do we have any Symmetricom experts on this list?
> 
> I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock running 
> for several years until we had a power cut and the UPS battery failed, on 
> powering back up it won't boot at all.
> 
> I suspect the flash is corrupt but they protect it in some way, so one can't 
> just copy the o/s onto a new card, and the company want 's to fix it for 
> me!
> 
> Thanks in advance,
> Chris
> 
> 
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"The main function of a modern police force is filling in forms."
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Alex Pummer]

the role of the diode is just to have a voltage drop?
73
KJ6UHN
Alex

On 9/23/2015 11:31 PM, Bill Hawkins wrote:

Perhaps I can do this in words, as I have no schematic software.

Start with the input to your favorite microprocessor's A/D converter.
Connect it to a suitable (more later) capacitor to analog ground.
Connect a cmos switch across the cap and call it S2. When S2 is on, it
discharges the cap.

Now build or buy a constant current generator connected from a suitable
positive voltage to another cmos switch called S1.
When S1 is on, all of the current generated flows to analog ground.

To make it all work, connect the anode of a diode from the junction of
the current source and S1 to the cap and analog input.

When S1 is on, no current gets to the cap. When S1 is off, all of the
current gets to the cap, if S2 is off. This causes a linear buildup of
voltage across the cap, for a suitable time.

When 1 PPS pulses are compared, suitable means one second to charge to
almost the maximum that the micro A/D supports.
The value of I is chosen to overwhelm diode leakage and A/D input
current. The value of C follows.

All that remains for a working system is a pair of flip-flops to control
S1 and S2.
FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
FF1 is on, S1 is off.
FF 2 is set by PPS 1 and cleared by an output from the micro when the
A/D conversion is done. When FF2 is on, S2 is off.

And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
conversion occurs, and be reset to zero volts when the micro is done
processing the input.

This gives the micro a linear conversion of pulse difference time rather
than an RC exponential value.

Feedback controllers do better with linear error signals.

But all of this is wasted if the PPS signals are not accurate due to
things that affect pulse rise and fall times.

If the above was not adequately clear, please ask for clarification. Or
do a schematic and ask for corrections.

Bill Hawkins

P.S. This will not work well for small differences between PPS 1 and 2.
It will work if the goal is 50% difference, or 90 degrees phase shift.


-Original Message-
From: Can Altineller
Sent: Wednesday, September 23, 2015 2:56 AM

%< --

4. I think an analog solution like Bill Hawkins described, would be best
suited for this task. But I have not understood it enough to build it.

Best Regards,
C.A.


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Re: [time-nuts] teensy as time capture device

[cfo]

On Thu, 24 Sep 2015 05:30:35 -0700, Jim Lux wrote:


> 
> What would be interesting is if there's a pin on the Arduino/Teensy that
> you could feed a high quality oscillator to, and then do counting with
> that.  The K20 microcontroller has a mindbendingly large number of
> features and alternate pin functions.

As i see it, from the DS. , it seems like there are 2 options.

External Oscillator (the system clock clock) , 
or External Timer clock (limited to system clock/4)

Electr. specs
https://www.pjrc.com/teensy/K20P64M72SF1.pdf

Family Ref
https://www.pjrc.com/teensy/K20P64M72SF1RM.pdf


Seems like the EXTAL pin (main oscillator) accepts an Oscillator signal 
(max VDD + 0.3v) (Electr specs pg.10)

Ext Osc Connection (Family ref. pg. 526)

Also see PLL jitter (Electr specs pg.27 table 14)


There is a possibility to clock the FlexTimerModule by an external clock  
(FTM_CLKIN/EXCLK - Max freq is Mainclock/4) , 
see (Family Ref. pg. 113, 214 & 774)


If using EXTAL and USB , you want to make sure that the USB part still 
gets it's 48Mhz (via the PLL mul/div).
Maybe divide 10Mhz (XTAL) by 2 , and mul by 48, in the PLL.


Rgds
CFO - Denmark




-- 
E-mail:xne...@luna.dyndns.dk

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Re: [time-nuts] Value of parts for the RC network of "GPSDO with 1ns res TIC"

[Jim Harman]

On Thu, Sep 24, 2015 at 10:14 AM, Jim Harman  wrote:

> The diode prevents it from being discharged by the LS4046.


Sorry, I meant HC4046.


-- 

--Jim Harman
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Re: [time-nuts] Symmetricom experts?

[Brian M]

S200s definitely shared the PSU issue. A rep from Symmetricom/MicroSemi
told me that the custom manufacturer had used a part which was not spec'd
properly (betting it was a cap).

I'd be surprised if the flash is corrupt. There's two compact flash cards,
each with a copy of the OS. Updates go to the non-running copy, so that the
current copy is a fail back for bad update. Cool strategy, but buggy for
things like password changes if you have two different versions.

I definitely had no problems cloning the cards and swapping my clones into
a unit. I'd be very surprised if corruption was the issue, and not just a
bad PSU.

- Brian

On Thu, Sep 24, 2015 at 7:00 AM Anders Wallin 
wrote:

> FWIW our SyncServer S250 has a PSU with an electrolytic cap that has failed
> at least twice over the years:
> http://www.anderswallin.net/2015/08/psu-electrolytic-cap-fix/
>
> Anders
>
> On Thu, Sep 24, 2015 at 10:21 AM, G1FEF  wrote:
>
> > Do we have any Symmetricom experts on this list?
> >
> > I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock
> running
> > for several years until we had a power cut and the UPS battery failed, on
> > powering back up it won't boot at all.
> >
> > I suspect the flash is corrupt but they protect it in some way, so one
> > can't just copy the o/s onto a new card, and the company want 's to
> fix
> > it for me!
> >
> > Thanks in advance,
> > Chris
> >
> >
> > ___
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> >
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Re: [time-nuts] Symmetricom experts?

[Wojciech Owczarek]

Hi Chris,

This is a Linux box - an x86 box in fact. As far as I remember they even
have VGA pin headers on the board inside. Boot it up with the serial
console active and see if you get anything meaningful, but I doubt it. I
opened one up for the same purpose last year but I don't have it to hand
anymore and I don't remember what the exact platform was. Open it and you
may be able to connect to it by other means than the serial port - which I
found to be of little use for troubleshooting. It could be something as
trivial as the box stuck in fsck prompt because of a corrupted FS. They do
have dual partitions, but I'm not sure whether they can actually fail over,
or is the second partition used only during f/w upgrades.

Is the statement about copy protection actually confirmed? I would try
finding someone with another S200 and copying the CF card first. And yes,
they will want ,££s, and it got worse since the Microsemi acquisition.
I have witnessed multiple S2xx deaths. Usually PSU fail, but death on power
cycle is not uncommon either.

Thanks,
Wojciech


On 24 September 2015 at 09:46, Mike Cook  wrote:

> Hi Chrs,
>   Not an expert… but usually computer systems give some indication of why
> a boot is failing on the systems console. The S200 is probably a unix based
> system as it has utilities such as SSH. TELNET. HTTP. So you could try
> connecting an RS232 terminal , or telnet’ing to its console server if it is
> managed by one. Then power it on again and see what the symptoms are. If
> there is no output, then it is a probably hardware problem and you will
> need to either have it serviced, or dig into it yourself . I doubt however
> that it is user serviceable.
> There are troubleshooting steps in the user manual, so I suggest you look
> at those. If you don’t have the manual handy, see
> <
> http://iecitel.com/resources/ntp%20network/S250/SyncServer%20S2xx%20User%20Guide.pdf
> >
>
> Have fun
> Mike
>
> > Le 24 sept. 2015 à 09:21, G1FEF  a écrit :
> >
> > Do we have any Symmetricom experts on this list?
> >
> > I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock
> running for several years until we had a power cut and the UPS battery
> failed, on powering back up it won't boot at all.
> >
> > I suspect the flash is corrupt but they protect it in some way, so one
> can't just copy the o/s onto a new card, and the company want 's to fix
> it for me!
> >
> > Thanks in advance,
> > Chris
> >
> >
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Wojciech Owczarek
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Re: [time-nuts] Symmetricom experts?

[Bob Darlington]

I've had the same problem with an S300 so I gave up and started working on
a replacement.  Eventually I'll get everything documented and offered to
the group, but far I've built a custom sheild for a BeagleBone Black with a
Furuno GT-8736 timing receiver, and it looks great so long as it's doing
nothing but running NTP.  As soon as I put load on the thing, it warms up,
and throws the time off.  NTP adjusts of course, but there's that  short
spike in offset that I find annoying and it makes my pretty graphs not so
pretty.  Perhaps it'll stabilize under a more realistic scenario of where
it services lots of NTP requests, and perhaps a small heatsink on the CPU
will help as well.  Much to do.

If you find a solution for the SyncServer products that doesn't involve a
complete replacement or a service contract, I'd love to hear about it.

-Bob

On Thu, Sep 24, 2015 at 1:21 AM, G1FEF  wrote:

> Do we have any Symmetricom experts on this list?
>
> I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock running
> for several years until we had a power cut and the UPS battery failed, on
> powering back up it won't boot at all.
>
> I suspect the flash is corrupt but they protect it in some way, so one
> can't just copy the o/s onto a new card, and the company want 's to fix
> it for me!
>
> Thanks in advance,
> Chris
>
>
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Re: [time-nuts] Value of parts for the RC network of "GPSDO with 1ns res TIC"

[Jim Harman]

Diode at HC4046 output pin 15 is 1N5711 (Schottky signal diode)
This is in series with 3900 ohm resistor.
Cap to ground is 1nf NPO ceramic
Resistor across the cap is 1 M

These values are suitable for the Arduino Uno (ATmega 328 processor) with
the analogReference set to INTERNAL. This gives the ADC a full-scale range
of 1.1 V. On the Micro (32u4 processor) the ADC range is 2.56 V so the cap
should be 220 pf.

Pin 3 of the HC4046 is fed by 1 MHz derived from the oscillator to be
controlled and pin 14 is the 1 pps from the GPS, which also drives the
interrupt that triggers the ADC.

The phase comparator is basically an R-S flip-flop. Once per second it
produces a 5 V pulse 0-1 microsec wide. The width of this pulse corresponds
to the time difference between the two inputs. When the pulse goes H, the
cap starts to charge through the diode and 3900 ohm resistor. The cap stops
charging when the pulse goes L. The diode prevents it from being discharged
by the LS4046. The ADC is triggered at the end of the pulse, reading the
peak value on the cap and thus the time difference. The 1 M resistor
discharges the cap over the remainder of the second before the next pulse.

The charging slope is not exactly linear, but for 0-1.1V it is pretty
close. It is noticeably curved for 0-2.56V, but works fine for this
application. It would be quite easy to linearize the response in software.

On Wed, Sep 23, 2015 at 7:07 PM, Can Altineller 
wrote:

> Hello,
>
> I got some 4046 plls and I decided to implement the schematic given on:
>
>
> https://www.febo.com/pipermail/time-nuts/attachments/20140211/8bdbc232/attachment-0004.jpg
>
> in the drawing phase comparator 3 output is connected to a diode, which
> then is fed to a network, and then read from an adc. I see a 1nF capacitor,
> but the other 2 parts I can not identify. (I am guessing one is a 1M
> resistor, and the other above is some inductor maybe?
>
> Best regards,
> C.A.
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--Jim Harman
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Re: [time-nuts] wwvb gps d-psk-r details 500KB

[John Ackermann N8UR]

This is profoundly cool, Paul!  Thanks so much for this work.

I'm not making any promises, but I hope to lay out a PCB for the DBM 
section and will make the gerbers available.  If there's enough 
interest, we might be able to do a group PCB order.  Contact me off-line 
about that.


John

On 9/24/2015 1:47 PM, paul swed wrote:

Hello to the group.
Here is the detailed document on the wwvb d-psk-r.
I do not know if it will be allowed through since its much larger then is
normal. Lets see.

Thanks for your interest also.

Regards
Paul
WB8TSL



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Re: [time-nuts] teensy as time capture device

[Jim Lux]

On 9/24/15 7:13 AM, cfo wrote:

On Thu, 24 Sep 2015 05:30:35 -0700, Jim Lux wrote:




What would be interesting is if there's a pin on the Arduino/Teensy that
you could feed a high quality oscillator to, and then do counting with
that.  The K20 microcontroller has a mindbendingly large number of
features and alternate pin functions.


As i see it, from the DS. , it seems like there are 2 options.

External Oscillator (the system clock clock) ,
or External Timer clock (limited to system clock/4)

Electr. specs
https://www.pjrc.com/teensy/K20P64M72SF1.pdf

Family Ref
https://www.pjrc.com/teensy/K20P64M72SF1RM.pdf


Seems like the EXTAL pin (main oscillator) accepts an Oscillator signal
(max VDD + 0.3v) (Electr specs pg.10)

Ext Osc Connection (Family ref. pg. 526)

Also see PLL jitter (Electr specs pg.27 table 14)


There is a possibility to clock the FlexTimerModule by an external clock
(FTM_CLKIN/EXCLK - Max freq is Mainclock/4) ,
see (Family Ref. pg. 113, 214 & 774)


If using EXTAL and USB , you want to make sure that the USB part still
gets it's 48Mhz (via the PLL mul/div).
Maybe divide 10Mhz (XTAL) by 2 , and mul by 48, in the PLL.


I would think that the FTM_CLKIN would be the way to go.. keep the core 
running at 48 and run 10 MHz in as EXCLK (since it's less than Mainclock/4)


Not sure I'd want to fool with the PLL programming: that's something 
where there might be other stuff that makes assumptions about how it's 
configured.



Now I have to look if the right pins come out to something I can see.
This is the MK20DX256VLH7 configuration.
Only FTM1 (0,1) and FTM2 (0,1) are configured I think.
"There are two external FTM_CLKINx pins that can be selected by any FTM 
module via the SOPT4 register in the SIM module."


Looks like pin 32 and 33 on the chip




Tnx
Jim
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Re: [time-nuts] teensy as time capture device

[Hal Murray]

xne...@luna.dyndns.dk said:
> External Oscillator (the system clock clock) ,  or External Timer clock
> (limited to system clock/4) 

That sounds like they are running the external signal through a synchronizer 
and then doing all the logic on the system clock.  That would add a lot of 
high frequency jitter but work as expected at longer time scales.

It would be fun to see if you could pick up hanging-bridge type artifacts.


-- 
These are my opinions.  I hate spam.



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