Hi Guys,
Le mercredi 13 janvier 2016 à 09:22 +, Jerome Blaha a écrit :
> Hey Guys,
>
> Is there an easy circuit to build that can consistently deliver a 1
> PPS from a 10MHz source with excellent resolution and
> repeatability? My first application is to test different 10MHz
> oscillators
Hi
> On Jan 25, 2016, at 8:55 AM, Xavier Bestel wrote:
>
> Hi Guys,
>
> Le mercredi 13 janvier 2016 à 09:22 +, Jerome Blaha a écrit :
>> Hey Guys,
>>
>> Is there an easy circuit to build that can consistently deliver a 1
>> PPS from a 10MHz source with excellent
On Wed, 20 Jan 2016 17:56:31 -0500
Bob Camp wrote:
> > Interestingly, some were close to 0ps, for which
> > we have no good explanation.
>
> The explanation is fairly simple, you have a clock and a “data pulse”
> flying down the delay / carry chain. With an ASIC you could make
Hi
> On Jan 21, 2016, at 5:48 AM, Attila Kinali wrote:
>
> On Wed, 20 Jan 2016 17:56:31 -0500
> Bob Camp wrote:
>
>>> Interestingly, some were close to 0ps, for which
>>> we have no good explanation.
>>
>> The explanation is fairly simple, you have a clock
rd RC oscillator as
> driven by the OCXO.
>
> Bob
>
>
>
>
> On Wed, 1/20/16, Poul-Henning Kamp <p...@phk.freebsd.dk> wrote:
>
> Subject: Re: [time-nuts] Generating a solid PPS from 10Mhz source
> To: "Disc
Attila,
On 01/20/2016 03:21 PM, Attila Kinali wrote:
On Wed, 20 Jan 2016 14:13:11 +
"Poul-Henning Kamp" wrote:
The test results showed a quite more
detailed structure with few delays over 100ps and most being between
20ps and 80ps. Interestingly, some were close to
Hi
> On Jan 20, 2016, at 6:28 AM, Attila Kinali wrote:
>
> On Mon, 18 Jan 2016 14:34:56 -0500
> Bob Camp wrote:
>
>> The nice thing about a FPGA (or CPLD) is that they come with a cute timing
>> analyzer. You can indeed
>> answer questions like this with a
rating a solid PPS from 10Mhz source
To: "Discussion of precise time and frequency measurement"
<time-nuts@febo.com>, "Attila Kinali" <att...@kinali.ch>
Date: Wednesday, January 20, 2016, 8:13 AM
In message <20160120122824.39fb655285dd0e68c38
On Wed, 20 Jan 2016 14:13:11 +
"Poul-Henning Kamp" wrote:
> >The test results showed a quite more
> >detailed structure with few delays over 100ps and most being between
> >20ps and 80ps. Interestingly, some were close to 0ps, for which
> >we have no explanation good
In message <20160120122824.39fb655285dd0e68c3884...@kinali.ch>, Attila Kinali w
rites:
>The test results showed a quite more
>detailed structure with few delays over 100ps and most being between
>20ps and 80ps. Interestingly, some were close to 0ps, for which
>we have no explanation good
On Mon, 18 Jan 2016 14:34:56 -0500
Bob Camp wrote:
> The nice thing about a FPGA (or CPLD) is that they come with a cute timing
> analyzer. You can indeed
> answer questions like this with a quite high level of confidence. That
> *assumes* that you bother to set
> up the timing
The nice thing about a FPGA (or CPLD) is that they come with a cute
timing analyzer. You can indeed
answer questions like this with a quite high level of confidence. That
*assumes* that you bother to set
up the timing analyzer :)
That true. Its nice looking "Timeng report". I saw the numbers
On Monday, January 18, 2016 08:45:20 PM you wrote:
>
>
> In message <29659871.S9XTlaFu4r@linux>, Bruce Griffiths writes:
> >To detect 100Hz modulation due to photocurrents in the LEDs the
150W
> >incandescent bulb had to be placed within a few cm of the LEDs.
>
> Incandescent bulbs
On 1/18/16 4:19 PM, Bob Camp wrote:
Hi
Some time - check out what a “60 Hz” incandescent bulb looks like when
hooked to 20 Hz …. flicker flicker flicker …
I suspect they optimize the thermal mass of the filament to reduce the flicker
at
50/60 Hz.
They optimize that to a tiny fraction of a
On Mon, 18 Jan 2016 20:45:20 +, you wrote:
>Incandescent bulbs don't have much "hum" in their light output,
>they're basically heating elements and they don't cool down nearly
>fast enough.
Hook photocell to an audio amp and shine a 60Hz powered lamp on it; you'll
be surprised. I don't know
Hi
If you fire up the FPGA and measure it, you will find a sub picosecond jitter
on a signal passing through it.
If you use the internal PLL or DLL in an FPGA, you might indeed see close to
1x10^-12 ADEV in some cases.
In general you should be able to get into the parts in the 10^-13 range
The clock to output delay of the PIC will be similar or perhaps a little
worse.
You seem to be confusing delay and jitter.
There are zero delay buffers (in the sense that the output transitions are
aligned with the clock transitions) but these have excessive jitter due to the
internal DLL used
Hi
Some time - check out what a “60 Hz” incandescent bulb looks like when
hooked to 20 Hz …. flicker flicker flicker …
I suspect they optimize the thermal mass of the filament to reduce the flicker
at
50/60 Hz.
Bob
> On Jan 18, 2016, at 3:45 PM, Poul-Henning Kamp wrote:
On Sun, 17 Jan 2016 17:32:58 +0100
Gerhard Hoffmann wrote:
> I have recently measured the noise of some regulators, LEDs and Zeners
> with partly unexpected results.
> I'll do a write-up and put it on my web site, but here are 3 pictures
> that already tell a lot:
Thanks a
In message <569bc23a.3030...@arcor.de>, Gerhard Hoffmann writes:
>LEDs abused as References:
This is one of the most stupid ideas ever, because LEDs works both ways.
(Back when LED wrist-watches first came out, people soon discovered
that they would reset themselves when photographed
On Wed, 13 Jan 2016 09:22:09 +, Jerome Blaha wrote:
> Is there an easy circuit to build that can consistently deliver a 1 PPS
> from a 10MHz source with excellent resolution and repeatability?
Ulrich B. has made an AVR 1PPS, for those that uses AVR's instead of PIC's
AVR PPSDIV 2008-09-06
Hi,
We are drifting from the original problem (dividing 10 MHz to 1 PPS) to
general questions such as hardware vs software implementation,
obsolescence of parts, program data retention and big program sizes for
trivial tasks, all of them also interesting.
Well, returning to the main problem
Hi
> On Jan 16, 2016, at 7:40 PM, jimlux wrote:
>
> On 1/16/16 10:07 AM, Poul-Henning Kamp wrote:
>>
>> In message <20160116080037.13903406...@ip-64-139-1-69.sjc.megapath.net>, Hal
>> Murray writes:
>>
>>> kb...@n1k.org said:
The astonishing part of this
Am 15.01.2016 um 10:14 schrieb Bruce Griffiths:
For lowest jitter the gate power supply noise needs to be very low.Biasing the
input at 50% supply helps somewhat but the gate threshold is never exactly 50%
and the low pass filtering effect of the coupling capacitor increases the
contribution
Hi
Back in the 70’s I was involved in making LCD watches. The whole “photo”
issue had not been fully through through. One day our chief marketing guy for
the project was driving around in Phoenix AZ. He looks down and notices that
his watch is dead. Pops out a spare, puts it on, confirms it it
You might have come across the Raspberry Pi story : one of the revised
versions had a SMPS control chip that was intended to be buried inside a
phone, not exposed on an open pcb.
https://www.raspberrypi.org/forums/viewtopic.php?t=99042
On Mon, Jan 18, 2016 at 3:11 PM, Bob Camp
Looking to the complex solutions for the frequency divider (CPLD/MCU), I
start to think about skews and propagation delays. Its not obvious from
the first glance. But I think such things exists.
It could be interesting to compare the numbers. Is it worth to consider
some correction to avoid
se time and frequency measurement"
<time-nuts@febo.com>
Sent: Monday, January 18, 2016 3:11 PM
Subject: Re: [time-nuts] Generating a solid PPS from 10Mhz source
Hi
Back in the 70’s I was involved in making LCD watches. The whole “photo”
issue had not been fully through through.
Hi,
No, the black plastic around ICs isn't black by chance.
Einstein got his Nobel price on the photoelectric effect, which is
relevant in this case.
A few years ago I assisted in modifying a camera for an amateur
astronomer. Among the modifications, one was to turn of power for a
In message <29659871.S9XTlaFu4r@linux>, Bruce Griffiths writes:
>To detect 100Hz modulation due to photocurrents in the LEDs the 150W
>incandescent bulb had to be placed within a few cm of the LEDs.
Incandescent bulbs don't have much "hum" in their light output,
they're basically
Hi
The same issue come into random logic. The most common chip logic way to do
this is with rippling
divide by 10’s. Been there / done that.. The output pulse in that case is
delayed by quite a bit. Put
a “sync” flip flop on the output and the (obvious) question is — do you know
the delay
On Monday, January 18, 2016 11:45:00 AM Poul-Henning Kamp wrote:
>
>
> In message <569bc23a.3030...@arcor.de>, Gerhard Hoffmann writes:
> >LEDs abused as References:
> This is one of the most stupid ideas ever, because LEDs works both ways.
>
> (Back when LED wrist-watches first came
kb...@n1k.org said:
> The astonishing part of this ânew worldâ is that a very complex chip that
> is
> made in high volume is cheaper than a handful of less popular (but far less
> complex) chips.
It would be interesting to see the die sizes.
Another advantage of the CPU solution is that
Hi
> On Jan 16, 2016, at 3:00 AM, Hal Murray wrote:
>
>
> kb...@n1k.org said:
>> The astonishing part of this “new world” is that a very complex chip that is
>> made in high volume is cheaper than a handful of less popular (but far less
>> complex) chips.
>
> It
In message <20160116080037.13903406...@ip-64-139-1-69.sjc.megapath.net>, Hal
Murray writes:
>kb...@n1k.org said:
>> The astonishing part of this “new world” is that a very complex chip that is
>> made in high volume is cheaper than a handful of less popular (but far less
>> complex)
On 1/16/16 10:07 AM, Poul-Henning Kamp wrote:
In message <20160116080037.13903406...@ip-64-139-1-69.sjc.megapath.net>, Hal
Murray writes:
kb...@n1k.org said:
The astonishing part of this “new world” is that a very complex chip that is
made in high volume is cheaper than a handful of
Thanks to everyone who responded.
I guess I'm just showing my age (66).
Of course all those considerations of cost etc are all true especially in the
world of the professional who has to make the product feasible for the market.
I'm a basement tinkerer with a well-stocked junk box for whom
Am 16.01.2016 um 15:03 schrieb Bob Camp:
Unlike the world of lithography, the dicing process has not made a lot of
progress.
Decades ago a 1mm x 1 mm die was about as small as you could get. From what
I can see that has not dropped by more than a factor of two in 40 years (if at
all).
Yes,
For lowest jitter the gate power supply noise needs to be very low.Biasing the
input at 50% supply helps somewhat but the gate threshold is never exactly 50%
and the low pass filtering effect of the coupling capacitor increases the
contribution of power supply noise to jitter.
A power supply
On Thu, 14 Jan 2016 09:50:15 -0500
Vlad wrote:
> I was thinking to make a frequency divider by using FPGA. Here is my
> attempt to implement it using VHDL.
> This is frequency divder plus D flip-flop which I was planed to use as
> source of 60Hz for my Telechron clock.
>
Am I missing something here?
I understand the ease and fun of programming up an AVR as much as anyone but
surely this task could be accomplished easily with a chain of fast
synchronous TTL or CMOS dividers. A resynchronising FF could also be added
at the end to clean up the 1 pps if
Why use a board full of TTL when an $1 8-pin chip will do it ?
On Thu, Jan 14, 2016 at 11:44 PM, Morris Odell
wrote:
> Am I missing something here?
>
> I understand the ease and fun of programming up an AVR as much as anyone
> but surely this task could be accomplished
> On Jan 14, 2016, at 3:44 PM, Morris Odell wrote:
>
> Am I missing something here?
>
> I understand the ease and fun of programming up an AVR as much as anyone but
> surely this task could be accomplished easily with a chain of fast
> synchronous TTL or CMOS
The programmable PIC or AVR or ... chip that will do the job are same or
less than a 555 chip, and a lot more flexible.
--- Graham
On Fri, Jan 15, 2016 at 11:55 AM, Adrian Godwin wrote:
> Why use a board full of TTL when an $1 8-pin chip will do it ?
>
>
> On Thu, Jan 14,
On Friday, January 15, 2016 12:13:47 PM Attila Kinali wrote:
> On Thu, 14 Jan 2016 09:50:15 -0500
>
> Vlad wrote:
> > I was thinking to make a frequency divider by using FPGA. Here is my
> > attempt to implement it using VHDL.
> > This is frequency divder plus D flip-flop which
Hi
The astonishing part of this “new world” is that a very complex chip that is
made in high
volume is cheaper than a handful of less popular (but far less complex) chips.
To do this with old style logic, you need to divide by 7 decades. If you do
three dual decade
counters, it’s probably
Nick wrote:
The output from my GPSDO is a square wave, so I didn't condition the
input. In the past what I've used for that is a DC blocking cap,
followed by a Thevenin termination (100 ohms to ground and Vcc)
feeding a 74LVC1G17 Schmitt trigger buffer. I don't know if that's
up to Time Nuts
I'm curious if that code will perform the intended function (down to the clock
cycle) when compiled. A check in the simulator would be a good idea while the
TIA is busy.
If it doesn't give you the performance you are looking for, try programming it
in assembly, as was done for the PicDiv.
Dan
Wed, 13 Jan 2016 12:12:39 -0800
> To: nsa...@kfu.com; time-nuts@febo.com
> Subject: Re: [time-nuts] Generating a solid PPS from 10Mhz source
> From: time-nuts@febo.com
>
> Just shy of a half dozen folks have asked, so I'll post here as soon as I
> finish cleaning it up. I'll put i
The code is at
https://github.com/nsayer/GPS-disciplined-OXCO/blob/master/tiny_divider.c
It’s a first cut. The code at the moment will just divide the input clock by 10
million, so you get a 1 PPS 50% duty square wave out. It should run on any
ATTinyx5 model - it certainly will fit on at
e. Can't seem to find anything in the datasheet for the tiny that
> explains the maximum frequency on a input pin.
>
> -=Bryan=-
>
>> Date: Wed, 13 Jan 2016 12:12:39 -0800
>> To: nsa...@kfu.com; time-nuts@febo.com
>> Subject: Re: [time-nuts] Generating a solid PPS from 10Mhz
I was thinking to make a frequency divider by using FPGA. Here is my
attempt to implement it using VHDL.
This is frequency divder plus D flip-flop which I was planed to use as
source of 60Hz for my Telechron clock.
However I never implement it in HW. Instead I was using STM32F4 with its
On Wed, 13 Jan 2016 14:31:25 +0100, Ole Petter Ronningen wrote:
> Sounds like a PICDIV is just about right:
> http://www.leapsecond.com/pic/picdiv.htm
>
Ulrich B made an AVRDIV, for those who use AVR's (bottom of page)
http://www.ulrich-bangert.de/html/downloads.html
/CFO
I and others have written divider routines in assembler for the ATtiny25
etc. The version I have is crude but divides by 10, 100, and 1000. I
also have a version that divides by 1E4, 1E5, and 1E6. I also have a
version that generates 3 pps outputs, one with a 50% duty cycle plus
positive
Following my previous note: today I did create simple test installation
using CPLD Xilinx XC2C32A. The project just get input from 50Mhz OSC and
divide it to get 1Hz output to send it to two LEDs and defined clk_out
pin. As I program it - the LEDs was blinking with 1Hz frequency. Which
means
> On Jan 14, 2016, at 4:20 AM, Daniel Watson wrote:
>
> I'm curious if that code will perform the intended function (down to the
> clock cycle) when compiled. A check in the simulator would be a good idea
> while the TIA is busy.
I did a test last night (I
> My test methodology was to feed 10 MHz from one of my GPSDOs into the TIA
> reference and the same 10 MHz into the device input. I then had the TIA
> perform period measurements with a 10 second gate. The result was 1 second,
> ± maybe a dozen or two ps on average, but again, thatâs where the
Hey Guys,
Is there an easy circuit to build that can consistently deliver a 1 PPS from a
10MHz source with excellent resolution and repeatability? My first application
is to test different 10MHz oscillators without a TIC always attached and then
compare the PPS output change over time against
Tom Van Baak has developed dividers based on simple PIC chips that will
produce 1 PPS from several input frequencies. These dividers have
remarkably low jitter, down in the couple-of-picosecond range, and are
very simple.
I've implemented life support circuitry around two versions of Tom's
Hi!
Try TVB's picDiv at http://www.leapsecond.com/pic/picdiv.htm
Edésio
On Wed, Jan 13, 2016 at 09:22:09AM +, Jerome Blaha wrote:
> Hey Guys,
>
> Is there an easy circuit to build that can consistently deliver a 1 PPS from
> a 10MHz source with excellent resolution and repeatability? My
Sounds like a PICDIV is just about right:
http://www.leapsecond.com/pic/picdiv.htm
Ole
On Wed, Jan 13, 2016 at 10:22 AM, Jerome Blaha
wrote:
> Hey Guys,
>
> Is there an easy circuit to build that can consistently deliver a 1 PPS
> from a 10MHz source with excellent
Just shy of a half dozen folks have asked, so I'll post here as soon as I
finish cleaning it up. I'll put it on Github when it's ready. I just need a day
or two.
Sent from my iPhone
> On Jan 13, 2016, at 6:43 AM, Nick Sayer via time-nuts
> wrote:
>
> If anyone is
If anyone is interested in the equivalent functionality using an ATTiny25 (for
instance, if you’re already heavily invested in AVR instead of PIC, like I am),
ping me. I’ve privately written code to solve almost the same problem and it
could easily be adapted into doing the same job.
> On Jan
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