Re: [time-nuts] Shera revisted

[Attila Kinali]

On Fri, 12 Aug 2016 13:56:40 +0200
Paul Boven  wrote:

> I'd want to use the programmable logic to build a (mostly) digital 
> interpolation, either something along the lines of the 5370, or digital 
> interpolation of the clock using DCM's like I did on a Spartan-3 years 
> ago. On that device, I could achieve a 16-fold resolution increase by 
> use of the clock management devices.

If you are not afraid of going FPGA, why not use the TDC core from
OHWR [1]? It has a very good resolution and more the sufficient long
term stability. I also have a port of this for cyclone4, but i would 
not recommend to use it, because it needs the paid version of quartus
while the OHWR version for spartan works with the free ISE version.

Attila Kinali

[1] http://www.ohwr.org/projects/tdc-core/wiki
-- 
Malek's Law:
Any simple idea will be worded in the most complicated way.
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Re: [time-nuts] Shera revisted

[Bruce Griffiths]

On Friday, August 12, 2016 12:21:55 PM David wrote:
> On Fri, 12 Aug 2016 13:56:40 +0200, you wrote:
> >Hi everyone,
> >
> >On 2016-08-11 21:06:12, Attila Kinali wrote:
> >> Hoi Bert,
> >> 
> >> I'm asking, because if you go the way of using a CPLD anyways, you 
could
> >> throw in another $2 for an opamp to build a time-to-amplitude 
converter
> >> (à la PICTIC II) and boost the resolutiong from 40ns to <100ps.
> >> As you would be measuring the PPS relative to the local clock, you
> >> would need only one "leg" of the PICTIC II (ie just one TAC plus a 
single
> >> ADC).>
> >I'd want to use the programmable logic to build a (mostly) digital
> >interpolation, either something along the lines of the 5370, or digital
> >interpolation of the clock using DCM's like I did on a Spartan-3 years
> >ago. On that device, I could achieve a 16-fold resolution increase by
> >use of the clock management devices.
> >
> >I'm currently trying to replicate my old digital clock interpolation
> >setup on the Xilinx/Digilent Arty board, with the aim of locking a Rb to
> >GPS.
> >Another goal is to get a DDMTD going on the Arty board for clock
> >comparisons.
> >
> >Regards, Paul Boven.
> 
> The HP5370 design seems awfully complicated unless it is significantly
> faster than a time to amplitude interpolator.  Integrating time
> stretching interpolators which were contemporary to the HP5370 were
> only 20 times slower and a time to amplitude interpolator is much
> faster.
> 
> Are there any modern implementations of the interpolator used in the
> HP5370?
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Not that I've seen.
However there are multichannel  damped sine TDCs with 5ps resolution 
from Keysight.

Bruce
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Re: [time-nuts] Shera revisted

[David]

On Fri, 12 Aug 2016 13:56:40 +0200, you wrote:

>Hi everyone,
>
>On 2016-08-11 21:06:12, Attila Kinali wrote:
>> Hoi Bert,
>
>> I'm asking, because if you go the way of using a CPLD anyways, you could
>> throw in another $2 for an opamp to build a time-to-amplitude converter
>> (à la PICTIC II) and boost the resolutiong from 40ns to <100ps.
>> As you would be measuring the PPS relative to the local clock, you
>> would need only one "leg" of the PICTIC II (ie just one TAC plus a single 
>> ADC).
>
>I'd want to use the programmable logic to build a (mostly) digital 
>interpolation, either something along the lines of the 5370, or digital 
>interpolation of the clock using DCM's like I did on a Spartan-3 years 
>ago. On that device, I could achieve a 16-fold resolution increase by 
>use of the clock management devices.
>
>I'm currently trying to replicate my old digital clock interpolation 
>setup on the Xilinx/Digilent Arty board, with the aim of locking a Rb to 
>GPS.
>Another goal is to get a DDMTD going on the Arty board for clock 
>comparisons.
>
>Regards, Paul Boven.

The HP5370 design seems awfully complicated unless it is significantly
faster than a time to amplitude interpolator.  Integrating time
stretching interpolators which were contemporary to the HP5370 were
only 20 times slower and a time to amplitude interpolator is much
faster.

Are there any modern implementations of the interpolator used in the
HP5370?
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Re: [time-nuts] Shera revisted

[Bob Camp]

Hi

It might be easier to get into this if we put numbers on some of this. Are 
we after a 16X increase from 10 ps (10 ps -> 0.6 fs) or from 10 ns (10 ns -> 
600 ps). 

There’s a lot of range there :)

Testing things like temperature dependance and noise / spurs can be challenging 
in
some of these approaches. It is not at all uncommon to see one person look at a 
system
and come up with a 50 ps number. Somebody else looks at it and comes up with 1 
ns. 
Who’s right? It depends a lot on the definition of what is being tested. 

Bob


> On Aug 12, 2016, at 7:56 AM, Paul Boven  wrote:
> 
> Hi everyone,
> 
> On 2016-08-11 21:06:12, Attila Kinali wrote:
>> Hoi Bert,
> 
>> I'm asking, because if you go the way of using a CPLD anyways, you could
>> throw in another $2 for an opamp to build a time-to-amplitude converter
>> (à la PICTIC II) and boost the resolutiong from 40ns to <100ps.
>> As you would be measuring the PPS relative to the local clock, you
>> would need only one "leg" of the PICTIC II (ie just one TAC plus a single 
>> ADC).
> 
> I'd want to use the programmable logic to build a (mostly) digital 
> interpolation, either something along the lines of the 5370, or digital 
> interpolation of the clock using DCM's like I did on a Spartan-3 years ago. 
> On that device, I could achieve a 16-fold resolution increase by use of the 
> clock management devices.
> 
> I'm currently trying to replicate my old digital clock interpolation setup on 
> the Xilinx/Digilent Arty board, with the aim of locking a Rb to GPS.
> Another goal is to get a DDMTD going on the Arty board for clock comparisons.
> 
> Regards, Paul Boven.
> 
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Re: [time-nuts] Shera revisted

[Paul Boven]

Hi everyone,

On 2016-08-11 21:06:12, Attila Kinali wrote:

Hoi Bert,



I'm asking, because if you go the way of using a CPLD anyways, you could
throw in another $2 for an opamp to build a time-to-amplitude converter
(à la PICTIC II) and boost the resolutiong from 40ns to <100ps.
As you would be measuring the PPS relative to the local clock, you
would need only one "leg" of the PICTIC II (ie just one TAC plus a single ADC).


I'd want to use the programmable logic to build a (mostly) digital 
interpolation, either something along the lines of the 5370, or digital 
interpolation of the clock using DCM's like I did on a Spartan-3 years 
ago. On that device, I could achieve a 16-fold resolution increase by 
use of the clock management devices.


I'm currently trying to replicate my old digital clock interpolation 
setup on the Xilinx/Digilent Arty board, with the aim of locking a Rb to 
GPS.
Another goal is to get a DDMTD going on the Arty board for clock 
comparisons.


Regards, Paul Boven.

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Re: [time-nuts] Shera revisted

[Attila Kinali]

Hoi Bert,

On Wed, 10 Aug 2016 09:33:30 -0400
Bert Kehren via time-nuts  wrote:

> I get repeated requests for info on Shera mainly for Rb applications. Shera 
>  has a successful history controlling Rb's.  Two things are a problem. The  
> AD 1861 is not only unavailable but also never intended for precise DAC  
> applications. The LTC 1655 makes a perfect replacement ,16 bits is more than  
> enough and covers range and resolution. What is needed is someone proficient 
>  with PIC assembly programming. We have the recommended changes.
> Second logic IC's are also outdated and hard to get. The solution is simple 
>  an Altera 32 cell 10 nsec. gate array, readily still available for less 
> than $  2, we have done a design and will gladly share once the PIC has been 
> modified  and tetsted.

What is your goal here? Simply a rebuild of the Shera controller
using current components?

I'm asking, because if you go the way of using a CPLD anyways, you could
throw in another $2 for an opamp to build a time-to-amplitude converter
(à la PICTIC II) and boost the resolutiong from 40ns to <100ps.
As you would be measuring the PPS relative to the local clock, you
would need only one "leg" of the PICTIC II (ie just one TAC plus a single ADC).

I guess you were refering to the 5M40Z from Altera, which can be had
for $1 at mouser. If you go slightly up in price to $1.5, you can get
an ICE40LP384 from Lattice with 384 LUTs, wastly enhancing your capabilities.

Yes, that would require a bit more than just changing a couple of
asm instructions, but would be worthwhile nontheless.
Especially if you are going to extend the system with pressure and
temperature compenstation anyways.

And I am with Chris on the topic of rewriting it in C, even if it's more
effort. Depending on what you actually do, part of the code can be
reused from open source projects out there, thus minimizing the actual work.


Attila Kinali

PS: If you are doing the CPLD/FPGA coding in VHDL and need help, let me know.

-- 
Malek's Law:
Any simple idea will be worded in the most complicated way.
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Re: [time-nuts] Shera revisted

[bownes]

There are also some nice cypresses semiconductor parts that are similar and 
have a really nice dev environment. 
Basically a core surrounded by programmable logic. Code in C ore close to it. 



> On Aug 11, 2016, at 07:06, Bob Camp  wrote:
> 
> Hi
> 
> To your earlier point, there are a number of fairly low cost boards with 
> Zynq’s on them. 
> They aren’t into the $5 range, but they are not that much more than one of 
> the Beagle 
> boards. 
> 
> Bob
> 
> 
>> On Aug 10, 2016, at 11:18 PM, Chris Albertson  
>> wrote:
>> 
>> Thanks for pointing out the Zynq.  Wow you get a dual core ARM and an
>> FPGA all in one package.   It seems overkill for a GPSDO but not the
>> type you are making as you can transferring the time out of the GPSDO
>> using PTP.
>> 
>> The Zyng looks to the the perfect platform for low-cost SDR.
>> 
>> On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
>>  wrote:
>>> Dear time-nuts,
>>> 
>>> My name is Joakim Langlet (SM0OET) and I just recently joined this list. As
>>> Brooks Shera was mentioned, I remembered that I was referenced in the
>>> footnotes of the original article in the QST - July 1998. It feels almost
>>> historical now. Brooks bought a few OCXOs from me.
>>> 
>>> I am currently working on a GPS stabilized OCXO.
>>> It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
>>> The hardware is starting to take shape. The control voltage of a 20 MHz OCXO
>>> is set by a DAC coupling from which I hope to set the voltage in very small
>>> steps.
>>> The OCXO has a CMOS level output which is converted to LVDS and is wired to
>>> the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input
>>> to the PLL of the clock tile. My intention is to scale up the clock to some
>>> where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
>>> receiver is also fed into the FPGA to gate the counters.
>>> 
>>> The reason for my choice of processor is that I want to run Linux on it in
>>> order benefit from the large software base. Time distribution using PTPv2
>>> and a nice web-application to visualize and control what is going on inside
>>> is part of the intended concept.
>>> 
>>> I still have a long way to the finish line but I will try to present some
>>> results as I proceed.
>>> 
>>> I am following what is written on this list with great interest. It feels
>>> good to know that I am not the only nut 
>>> 
>>> BR/
>>> Joakim
>>> ___
>>> time-nuts mailing list -- time-nuts@febo.com
>>> To unsubscribe, go to
>>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>>> and follow the instructions there.
>> 
>> 
>> 
>> -- 
>> 
>> Chris Albertson
>> Redondo Beach, California
>> ___
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> 
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Re: [time-nuts] Shera revisted

[jimlux]

On 8/10/16 8:18 PM, Chris Albertson wrote:

Thanks for pointing out the Zynq.  Wow you get a dual core ARM and an
FPGA all in one package.   It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.


There are SDRs based on the Zynq.


http://zedboard.org/product/zynq-sdr-ii-eval
http://www.mathworks.com/hardware-support/zynq-sdr.html
http://gnuradio.org/redmine/projects/gnuradio/wiki/Embedded

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Re: [time-nuts] Shera revisted

[Bob Camp]

Hi

To your earlier point, there are a number of fairly low cost boards with Zynq’s 
on them. 
They aren’t into the $5 range, but they are not that much more than one of the 
Beagle 
boards. 

Bob


> On Aug 10, 2016, at 11:18 PM, Chris Albertson  
> wrote:
> 
> Thanks for pointing out the Zynq.  Wow you get a dual core ARM and an
> FPGA all in one package.   It seems overkill for a GPSDO but not the
> type you are making as you can transferring the time out of the GPSDO
> using PTP.
> 
> The Zyng looks to the the perfect platform for low-cost SDR.
> 
> On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
>  wrote:
>> Dear time-nuts,
>> 
>> My name is Joakim Langlet (SM0OET) and I just recently joined this list. As
>> Brooks Shera was mentioned, I remembered that I was referenced in the
>> footnotes of the original article in the QST - July 1998. It feels almost
>> historical now. Brooks bought a few OCXOs from me.
>> 
>> I am currently working on a GPS stabilized OCXO.
>> It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
>> The hardware is starting to take shape. The control voltage of a 20 MHz OCXO
>> is set by a DAC coupling from which I hope to set the voltage in very small
>> steps.
>> The OCXO has a CMOS level output which is converted to LVDS and is wired to
>> the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input
>> to the PLL of the clock tile. My intention is to scale up the clock to some
>> where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
>> receiver is also fed into the FPGA to gate the counters.
>> 
>> The reason for my choice of processor is that I want to run Linux on it in
>> order benefit from the large software base. Time distribution using PTPv2
>> and a nice web-application to visualize and control what is going on inside
>> is part of the intended concept.
>> 
>> I still have a long way to the finish line but I will try to present some
>> results as I proceed.
>> 
>> I am following what is written on this list with great interest. It feels
>> good to know that I am not the only nut 
>> 
>> BR/
>> Joakim
>> ___
>> time-nuts mailing list -- time-nuts@febo.com
>> To unsubscribe, go to
>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>> and follow the instructions there.
> 
> 
> 
> -- 
> 
> Chris Albertson
> Redondo Beach, California
> ___
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Re: [time-nuts] Shera revisted

[Joakim Langlet]

You are so right, Chris.
The Zynq is absolutely an overkill for an ordinary GPSDO.
What I think is attractive with the Zynq are the possibilities to 
experiment with different implementations of counters and gates without 
soldering and that you can get pretty fast counters well integrated with 
the processor.


The Zynq would be pretty good for SDR experiments too, as you point out.
That may well be my next project.


On 2016-08-11 05:18, Chris Albertson wrote:

Thanks for pointing out the Zynq.  Wow you get a dual core ARM and an
FPGA all in one package.   It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

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Re: [time-nuts] Shera revisted

[Michael Wouters]

The Red Pitaya uses a Zynq, and there's an (unofficial) SDR application
available to experiment with.

Cheers
Michael
On Thursday, 11 August 2016, Chris Albertson 
wrote:

> Thanks for pointing out the Zynq.  Wow you get a dual core ARM and an
> FPGA all in one package.   It seems overkill for a GPSDO but not the
> type you are making as you can transferring the time out of the GPSDO
> using PTP.
>
> The Zyng looks to the the perfect platform for low-cost SDR.
>
> On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
> > wrote:
> > Dear time-nuts,
> >
> > My name is Joakim Langlet (SM0OET) and I just recently joined this list.
> As
> > Brooks Shera was mentioned, I remembered that I was referenced in the
> > footnotes of the original article in the QST - July 1998. It feels almost
> > historical now. Brooks bought a few OCXOs from me.
> >
> > I am currently working on a GPS stabilized OCXO.
> > It is based on a Xilinx Zynq FPGA as the processor and counter
> arrangement.
> > The hardware is starting to take shape. The control voltage of a 20 MHz
> OCXO
> > is set by a DAC coupling from which I hope to set the voltage in very
> small
> > steps.
> > The OCXO has a CMOS level output which is converted to LVDS and is wired
> to
> > the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as
> input
> > to the PLL of the clock tile. My intention is to scale up the clock to
> some
> > where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
> > receiver is also fed into the FPGA to gate the counters.
> >
> > The reason for my choice of processor is that I want to run Linux on it
> in
> > order benefit from the large software base. Time distribution using PTPv2
> > and a nice web-application to visualize and control what is going on
> inside
> > is part of the intended concept.
> >
> > I still have a long way to the finish line but I will try to present some
> > results as I proceed.
> >
> > I am following what is written on this list with great interest. It feels
> > good to know that I am not the only nut 
> >
> > BR/
> > Joakim
> > ___
> > time-nuts mailing list -- time-nuts@febo.com 
> > To unsubscribe, go to
> > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> > and follow the instructions there.
>
>
>
> --
>
> Chris Albertson
> Redondo Beach, California
> ___
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> mailman/listinfo/time-nuts
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>
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Re: [time-nuts] Shera revisted

[Chris Albertson]

Thanks for pointing out the Zynq.  Wow you get a dual core ARM and an
FPGA all in one package.   It seems overkill for a GPSDO but not the
type you are making as you can transferring the time out of the GPSDO
using PTP.

The Zyng looks to the the perfect platform for low-cost SDR.

On Wed, Aug 10, 2016 at 2:30 PM, Joakim Langlet
 wrote:
> Dear time-nuts,
>
> My name is Joakim Langlet (SM0OET) and I just recently joined this list. As
> Brooks Shera was mentioned, I remembered that I was referenced in the
> footnotes of the original article in the QST - July 1998. It feels almost
> historical now. Brooks bought a few OCXOs from me.
>
> I am currently working on a GPS stabilized OCXO.
> It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
> The hardware is starting to take shape. The control voltage of a 20 MHz OCXO
> is set by a DAC coupling from which I hope to set the voltage in very small
> steps.
> The OCXO has a CMOS level output which is converted to LVDS and is wired to
> the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as input
> to the PLL of the clock tile. My intention is to scale up the clock to some
> where a bit over 200 MHz to be fed to the counters.The 1 PPS from the GPS
> receiver is also fed into the FPGA to gate the counters.
>
> The reason for my choice of processor is that I want to run Linux on it in
> order benefit from the large software base. Time distribution using PTPv2
> and a nice web-application to visualize and control what is going on inside
> is part of the intended concept.
>
> I still have a long way to the finish line but I will try to present some
> results as I proceed.
>
> I am following what is written on this list with great interest. It feels
> good to know that I am not the only nut 
>
> BR/
> Joakim
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.



-- 

Chris Albertson
Redondo Beach, California
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Re: [time-nuts] Shera revisted

[Joakim Langlet]

Dear time-nuts,

My name is Joakim Langlet (SM0OET) and I just recently joined this list. 
As Brooks Shera was mentioned, I remembered that I was referenced in the 
footnotes of the original article in the QST - July 1998. It feels 
almost historical now. Brooks bought a few OCXOs from me.


I am currently working on a GPS stabilized OCXO.
It is based on a Xilinx Zynq FPGA as the processor and counter arrangement.
The hardware is starting to take shape. The control voltage of a 20 MHz 
OCXO is set by a DAC coupling from which I hope to set the voltage in 
very small steps.
The OCXO has a CMOS level output which is converted to LVDS and is wired 
to the FPGA board. The Xilinx Zynq take a minimum frequency of 19 MHz as 
input to the PLL of the clock tile. My intention is to scale up the 
clock to some where a bit over 200 MHz to be fed to the counters.The 1 
PPS from the GPS receiver is also fed into the FPGA to gate the counters.


The reason for my choice of processor is that I want to run Linux on it 
in order benefit from the large software base. Time distribution using 
PTPv2 and a nice web-application to visualize and control what is going 
on inside is part of the intended concept.


I still have a long way to the finish line but I will try to present 
some results as I proceed.


I am following what is written on this list with great interest. It 
feels good to know that I am not the only nut 


BR/
Joakim
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Re: [time-nuts] Shera revisted

[Chris Albertson]

On Wed, Aug 10, 2016 at 6:33 AM, Bert Kehren via time-nuts
 wrote:
..The LTC 1655 makes a perfect replacement ,16 bits is more than
> enough and covers range and resolution. What is needed is someone proficient
>  with PIC assembly programming.


Even if you solve this problem today, you will have to re-solve it
again and again over the life of the project.Better to re-code it
in C.  In the past one could get better performance with hand written
assembly but today the uP chip has 100X more space than needed.

In fact I, and I think most others have moved on to using small uP
development boards rather then bare uP chips because the little boards
come with USB programmers, chock crystals and everything you need and
might cost something under $5.   They are dramatically easier to use
as  most have a row of 0.1" headers so you can connect your custom
electronics.   This is not the way to go if you want to build 1,000
units but for a few tens of units it saves quite a to of work.
Especially if a software update has to be done after shipping.  The
board's USB connection saves end users much hassle.



-- 

Chris Albertson
Redondo Beach, California
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[time-nuts] Shera revisted

[Bert Kehren via time-nuts]

I get repeated requests for info on Shera mainly for Rb applications. Shera 
 has a successful history controlling Rb's.  Two things are a problem. The  
AD 1861 is not only unavailable but also never intended for precise DAC  
applications. The LTC 1655 makes a perfect replacement ,16 bits is more than  
enough and covers range and resolution. What is needed is someone proficient 
 with PIC assembly programming. We have the recommended changes.
Second logic IC's are also outdated and hard to get. The solution is simple 
 an Altera 32 cell 10 nsec. gate array, readily still available for less 
than $  2, we have done a design and will gladly share once the PIC has been 
modified  and tetsted.
With the work on the HP 5065A adding pressure compensation and temperature  
will be relatively simple using the 1655 with its reference output.
On the PIC issue please contact me directly off list
Bert Kehren 
 
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