Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bill Hawkins]

The role of the diode is to break the current path to the cap
when S1 shorts the current to ground when PPS 2 occurs.

With the diode, S1 does not short the cap to ground.

Bill Hawkins

-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Alex
Pummer
Sent: Thursday, September 24, 2015 3:58 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] algorithms and hardware for comparing clock
pulses

the role of the diode is just to have a voltage drop?
73
KJ6UHN
Alex

On 9/23/2015 11:31 PM, Bill Hawkins wrote:
> Perhaps I can do this in words, as I have no schematic software.
>
> Start with the input to your favorite microprocessor's A/D converter.
> Connect it to a suitable (more later) capacitor to analog ground.
> Connect a cmos switch across the cap and call it S2. When S2 is on, it

> discharges the cap.
>
> Now build or buy a constant current generator connected from a 
> suitable positive voltage to another cmos switch called S1.
> When S1 is on, all of the current generated flows to analog ground.
>
> To make it all work, connect the anode of a diode from the junction of

> the current source and S1 to the cap and analog input.
>
> When S1 is on, no current gets to the cap. When S1 is off, all of the 
> current gets to the cap, if S2 is off. This causes a linear buildup of

> voltage across the cap, for a suitable time.
>
> When 1 PPS pulses are compared, suitable means one second to charge to

> almost the maximum that the micro A/D supports.
> The value of I is chosen to overwhelm diode leakage and A/D input 
> current. The value of C follows.
>
> All that remains for a working system is a pair of flip-flops to 
> control
> S1 and S2.
> FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
> FF1 is on, S1 is off.
> FF 2 is set by PPS 1 and cleared by an output from the micro when the 
> A/D conversion is done. When FF2 is on, S2 is off.
>
> And so C will charge from PPS 1 to PPS 2, hold the value while the A/D

> conversion occurs, and be reset to zero volts when the micro is done 
> processing the input.
>
> This gives the micro a linear conversion of pulse difference time 
> rather than an RC exponential value.
>
> Feedback controllers do better with linear error signals.
>
> But all of this is wasted if the PPS signals are not accurate due to 
> things that affect pulse rise and fall times.
>
> If the above was not adequately clear, please ask for clarification. 
> Or do a schematic and ask for corrections.
>
> Bill Hawkins
>
> P.S. This will not work well for small differences between PPS 1 and
2.
> It will work if the goal is 50% difference, or 90 degrees phase shift.
>
>
> -Original Message-
> From: Can Altineller
> Sent: Wednesday, September 23, 2015 2:56 AM
>
> %< --
>
> 4. I think an analog solution like Bill Hawkins described, would be 
> best suited for this task. But I have not understood it enough to
build it.
>
> Best Regards,
> C.A.
>
>

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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bill Hawkins]

Don't know why I was referenced on this. The simple approach is what I
was trying to improve.
But I was only looking at a way to covert pulse width time to voltage
for further processing.
Perhaps linearity is not required in this application.

It's been my experience that controllers with proportional terms such as
PID do a better job with a linear error signal, unless the thing being
controlled (crystal frequency) is so nonlinear that the integral term
does most of the work.

Wish I could do the experiment, but no longer have a lab.

Bill Hawkins


-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Bob
Camp
Sent: Thursday, September 24, 2015 6:37 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] algorithms and hardware for comparing clock
pulses

Hi

Simple approach:

Use a pair of tri-state buffers. 

Both have their outputs hooked to the cap through resistors.

One (call it A) has its signal input grounded. The other (call it B) has
its signal input tied high. Both of the tri-state controls normal sit in
the "off" (= output is tri-state) condition. 

When I turn A on, the cap discharges. If instead, I turn B on, the cap
charges. If neither is on, the cap changes voltage only due to leakage
current. 

Let's say I have a long R/C on A and simply use it to discharge the cap
to zero. It's there only to set a starting value on the cap. The R/C
could be just about anything. 

Let's also say that I feed a variable width pulse into B. While the
pulse has the gate control "on" the cap charges. The voltage on the cap
is proportional to the well known R/C time constant formula and the
width of the pulse. 

Once the pulse is gone, I fire up the A/D and read the voltage. After I
have the voltage I put the cap back to ground with A. 



So what can go wrong?

1) I have the cap in the "both gates off" state to long and all I'm
reading is the impact of leakage current.

2) My pulse is to wide and the R/C maxes out.

3) My pulse is long enough that my resolution goes below my desired
resolution target. 

4) The resistance is low enough that the gate output R gets into the
act.

5) The C is so small that trace stray C (and input C's) get into the
act. 

6) The current into the R is so high that the gate current limits at the
start of the charge cycle. 

7) The caps or resistors are not stable so the system is not repeatable.


8) Your ADC has some pathogenic thing it does when it converts that
shorts the cap to ground. ( = you have a really weird ADC). 

Except for leakage current, everything is controllable in the design.
Some of the stuff above can be modeled (or measured) to minimize it's
impact. There are more subtle issues like the fact that the gate has a
different propagation delay low to high than high to low. That will
stretch the pulse a bit. If you get really fast on the pulse, the output
of the gate gets into the act a couple of ways. 

Bob


> On Sep 24, 2015, at 2:31 AM, Bill Hawkins <b...@iaxs.net> wrote:
> 
> Perhaps I can do this in words, as I have no schematic software.
> 
> Start with the input to your favorite microprocessor's A/D converter.
> Connect it to a suitable (more later) capacitor to analog ground.
> Connect a cmos switch across the cap and call it S2. When S2 is on, it

> discharges the cap.
> 
> Now build or buy a constant current generator connected from a 
> suitable positive voltage to another cmos switch called S1.
> When S1 is on, all of the current generated flows to analog ground.
> 
> To make it all work, connect the anode of a diode from the junction of

> the current source and S1 to the cap and analog input.
> 
> When S1 is on, no current gets to the cap. When S1 is off, all of the 
> current gets to the cap, if S2 is off. This causes a linear buildup of

> voltage across the cap, for a suitable time.
> 
> When 1 PPS pulses are compared, suitable means one second to charge to

> almost the maximum that the micro A/D supports.
> The value of I is chosen to overwhelm diode leakage and A/D input 
> current. The value of C follows.
> 
> All that remains for a working system is a pair of flip-flops to 
> control
> S1 and S2.
> FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
> FF1 is on, S1 is off.
> FF 2 is set by PPS 1 and cleared by an output from the micro when the 
> A/D conversion is done. When FF2 is on, S2 is off.
> 
> And so C will charge from PPS 1 to PPS 2, hold the value while the A/D

> conversion occurs, and be reset to zero volts when the micro is done 
> processing the input.
> 
> This gives the micro a linear conversion of pulse difference time 
> rather than an RC exponential value.
> 
> Feedback controllers do better with linear error signals.
> 
> But all of this is wasted if the PPS signals ar

Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bill Hawkins]

Perhaps I can do this in words, as I have no schematic software.

Start with the input to your favorite microprocessor's A/D converter.
Connect it to a suitable (more later) capacitor to analog ground.
Connect a cmos switch across the cap and call it S2. When S2 is on, it
discharges the cap.

Now build or buy a constant current generator connected from a suitable
positive voltage to another cmos switch called S1.
When S1 is on, all of the current generated flows to analog ground.

To make it all work, connect the anode of a diode from the junction of
the current source and S1 to the cap and analog input.

When S1 is on, no current gets to the cap. When S1 is off, all of the
current gets to the cap, if S2 is off. This causes a linear buildup of
voltage across the cap, for a suitable time.

When 1 PPS pulses are compared, suitable means one second to charge to
almost the maximum that the micro A/D supports.
The value of I is chosen to overwhelm diode leakage and A/D input
current. The value of C follows.

All that remains for a working system is a pair of flip-flops to control
S1 and S2.
FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
FF1 is on, S1 is off.
FF 2 is set by PPS 1 and cleared by an output from the micro when the
A/D conversion is done. When FF2 is on, S2 is off.

And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
conversion occurs, and be reset to zero volts when the micro is done
processing the input.

This gives the micro a linear conversion of pulse difference time rather
than an RC exponential value.

Feedback controllers do better with linear error signals.

But all of this is wasted if the PPS signals are not accurate due to
things that affect pulse rise and fall times.

If the above was not adequately clear, please ask for clarification. Or
do a schematic and ask for corrections.

Bill Hawkins

P.S. This will not work well for small differences between PPS 1 and 2.
It will work if the goal is 50% difference, or 90 degrees phase shift.


-Original Message-
From: Can Altineller
Sent: Wednesday, September 23, 2015 2:56 AM

%< --

4. I think an analog solution like Bill Hawkins described, would be best
suited for this task. But I have not understood it enough to build it.

Best Regards,
C.A.


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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bob Camp]

Hi

Simple approach:

Use a pair of tri-state buffers. 

Both have their outputs hooked to the cap through resistors.

One (call it A) has its signal input grounded. The other (call it B) has
its signal input tied high. Both of the tri-state controls normal sit in the 
“off” (= output is tri-state) condition. 

When I turn A on, the cap discharges. If instead, I turn B on, the cap 
charges. If neither is on, the cap changes voltage only due to leakage
current. 

Let’s say I have a long R/C on A and simply use it to discharge the cap 
to zero. It’s there only to set a starting value on the cap. The R/C could be
just about anything. 

Let’s also say that I feed a variable width pulse into B. While the pulse has
the gate control “on” the cap charges. The voltage on the cap is proportional to
the well known R/C time constant formula and the width of the pulse. 

Once the pulse is gone, I fire up the A/D and read the voltage. After I have
the voltage I put the cap back to ground with A. 



So what can go wrong?

1) I have the cap in the “both gates off” state to long and all I’m 
reading is the impact of leakage current.

2) My pulse is to wide and the R/C maxes out.

3) My pulse is long enough that my resolution goes below my desired
resolution target. 

4) The resistance is low enough that the gate output R gets into the 
act.

5) The C is so small that trace stray C (and input C’s) get into the act. 

6) The current into the R is so high that the gate current limits at the 
start of the charge cycle. 

7) The caps or resistors are not stable so the system is not repeatable. 

8) Your ADC has some pathogenic thing it does when it converts that shorts
the cap to ground. ( = you have a really weird ADC). 

Except for leakage current, everything is controllable in the design. Some
of the stuff above can be modeled (or measured) to minimize it’s impact. There
are more subtle issues like the fact that the gate has a different propagation 
delay
low to high than high to low. That will stretch the pulse a bit. If you get 
really fast
on the pulse, the output of the gate gets into the act a couple of ways. 

Bob


> On Sep 24, 2015, at 2:31 AM, Bill Hawkins  wrote:
> 
> Perhaps I can do this in words, as I have no schematic software.
> 
> Start with the input to your favorite microprocessor's A/D converter.
> Connect it to a suitable (more later) capacitor to analog ground.
> Connect a cmos switch across the cap and call it S2. When S2 is on, it
> discharges the cap.
> 
> Now build or buy a constant current generator connected from a suitable
> positive voltage to another cmos switch called S1.
> When S1 is on, all of the current generated flows to analog ground.
> 
> To make it all work, connect the anode of a diode from the junction of
> the current source and S1 to the cap and analog input.
> 
> When S1 is on, no current gets to the cap. When S1 is off, all of the
> current gets to the cap, if S2 is off. This causes a linear buildup of
> voltage across the cap, for a suitable time.
> 
> When 1 PPS pulses are compared, suitable means one second to charge to
> almost the maximum that the micro A/D supports.
> The value of I is chosen to overwhelm diode leakage and A/D input
> current. The value of C follows.
> 
> All that remains for a working system is a pair of flip-flops to control
> S1 and S2.
> FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
> FF1 is on, S1 is off.
> FF 2 is set by PPS 1 and cleared by an output from the micro when the
> A/D conversion is done. When FF2 is on, S2 is off.
> 
> And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
> conversion occurs, and be reset to zero volts when the micro is done
> processing the input.
> 
> This gives the micro a linear conversion of pulse difference time rather
> than an RC exponential value.
> 
> Feedback controllers do better with linear error signals.
> 
> But all of this is wasted if the PPS signals are not accurate due to
> things that affect pulse rise and fall times.
> 
> If the above was not adequately clear, please ask for clarification. Or
> do a schematic and ask for corrections.
> 
> Bill Hawkins
> 
> P.S. This will not work well for small differences between PPS 1 and 2.
> It will work if the goal is 50% difference, or 90 degrees phase shift.
> 
> 
> -Original Message-
> From: Can Altineller
> Sent: Wednesday, September 23, 2015 2:56 AM
> 
> %< --
> 
> 4. I think an analog solution like Bill Hawkins described, would be best
> suited for this task. But I have not understood it enough to build it.
> 
> Best Regards,
> C.A.
> 
> 
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Alex Pummer]

the role of the diode is just to have a voltage drop?
73
KJ6UHN
Alex

On 9/23/2015 11:31 PM, Bill Hawkins wrote:

Perhaps I can do this in words, as I have no schematic software.

Start with the input to your favorite microprocessor's A/D converter.
Connect it to a suitable (more later) capacitor to analog ground.
Connect a cmos switch across the cap and call it S2. When S2 is on, it
discharges the cap.

Now build or buy a constant current generator connected from a suitable
positive voltage to another cmos switch called S1.
When S1 is on, all of the current generated flows to analog ground.

To make it all work, connect the anode of a diode from the junction of
the current source and S1 to the cap and analog input.

When S1 is on, no current gets to the cap. When S1 is off, all of the
current gets to the cap, if S2 is off. This causes a linear buildup of
voltage across the cap, for a suitable time.

When 1 PPS pulses are compared, suitable means one second to charge to
almost the maximum that the micro A/D supports.
The value of I is chosen to overwhelm diode leakage and A/D input
current. The value of C follows.

All that remains for a working system is a pair of flip-flops to control
S1 and S2.
FF 1 is set by PPS 1 and cleared by PPS 2, and by power on reset. When
FF1 is on, S1 is off.
FF 2 is set by PPS 1 and cleared by an output from the micro when the
A/D conversion is done. When FF2 is on, S2 is off.

And so C will charge from PPS 1 to PPS 2, hold the value while the A/D
conversion occurs, and be reset to zero volts when the micro is done
processing the input.

This gives the micro a linear conversion of pulse difference time rather
than an RC exponential value.

Feedback controllers do better with linear error signals.

But all of this is wasted if the PPS signals are not accurate due to
things that affect pulse rise and fall times.

If the above was not adequately clear, please ask for clarification. Or
do a schematic and ask for corrections.

Bill Hawkins

P.S. This will not work well for small differences between PPS 1 and 2.
It will work if the goal is 50% difference, or 90 degrees phase shift.


-Original Message-
From: Can Altineller
Sent: Wednesday, September 23, 2015 2:56 AM

%< --

4. I think an analog solution like Bill Hawkins described, would be best
suited for this task. But I have not understood it enough to build it.

Best Regards,
C.A.


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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Bill Hawkins]

Group,

Seems to me that what's needed here is a current source for linear volts
vs. time and the cmos switching to control the duration of the capacitor
charge while the phase flip-flop is on. When it turns off, it interrupts
the processor and isolates the capacitor so it acts as a sample-and-hold
device. The processor can take its own sweet time reading the capacitor
voltage (although this sets minimum limits on the pulse duration). When
the reading has been captured, the micro toggles a FF that shorts the
capacitor with a cmos switch. The short is removed when the phase FF
toggles on.

This is a lot of analog circuitry, but it will operate as fast as the
parts are capable of switching and not at the whim of whatever the micro
is doing.

Hope that's useful. Probably already been done.

Bill Hawkins 


-Original Message-
From: Magnus Danielson
Sent: Tuesday, September 22, 2015 3:32 PM

Jim,

I had the intent to try this, but never got around doing it. Thanks for
reminding me. Please share any enhancements.

I did exchange some emails with Lars, but as that project never got off
the ground, it faded out.

Cheers,
Magnus


On 09/21/2015 10:02 PM, Jim Harman wrote:
> Hi Can,
>
> For a simple analog solution, you might try a 74HC4046 phase detector 
> followed by a diode and RC network as used in Lars Walenius' GPSDO, 
> described here in the archives:
>
> https://www.febo.com/pipermail/time-nuts/2014-February/082820.html
>
> The phase detector produces a pulse whose width equals the time 
> difference between the two pulses. The RC network converts this to a 
> voltage proportional to the time difference, which you then measure 
> with the MCU's A/D converter. Using the rising edge of the signal at 
> pin 14 as the interrupt source triggers the A/D converter at the end 
> of the pulse, which corresponds to the peak of the analog signal.. The

> 1 meg resistor discharges the capacitor between pulses.
>
> Lars' code also includes a filtering algorithm which does a nice job 
> of controlling one of the oscillators to match the 1-PPS generated by
the GPS.
> I have enhanced this if you are interested.
>

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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Can Altineller]

Hello All,

Another night heroically wasted, and I have achieved a PID lock within 50 /
80 000 000 th of a second between two clocks. 50 is there because it is the
minimum clock ticks for the irq handler to execute.

To summarize:

1. I am using a TI launchpad running at 80mhz. I was using micros() to
measure time, but then I realized I could use SysClockTicks, which is
80,000,000 per second. In Energia, I had to use: time_micros =
HWREG(DWT_BASE + DWT_O_CYCCNT) to get the sysTicks. I am not sure if PID
algorithm is the right one for tuning clocks, but thats what I only knew.

2. The diffuculty arises from the fact that I am using 1pps signal to tune
a DS3231, which also gives out a 1pps signal, (it can be configured to give
faster pulses, but then when I modify the ppms, they wont be reflected in
the pulse output) So in order to observe the reaction after setting aging
register, I have to compare 1pps signal.
If I had a RTC with a tunable 10mhz clock, I could feed that into a PLL /
counter, not the case. Eitherway, I am in the process of ordering a VCTCXO,
and probably will build my own RTC.

3. I have investigated and experimented different interrupt schemes, like
taking measurements on both rising and falling edge, and XOR'ing the clock
signals. Using a 74hc74 and a XOR gate, I have made a mini-circuit so that
if one clock is lagging behind, it will send pulses from one pin, and if
reverse, it will pulse from other pin. However this scheme failed because
same difficulty with interrupts arise again. The pulse is too fast in order
to trigger interrupts on the falling and rising edge, and measure time.

4. I think an analog solution like Bill Hawkins described, would be best
suited for this task. But I have not understood it enough to build it.

Best Regards,
C.A.

On Wed, Sep 23, 2015 at 7:25 AM, Bill Hawkins  wrote:

> Group,
>
> Seems to me that what's needed here is a current source for linear volts
> vs. time and the cmos switching to control the duration of the capacitor
> charge while the phase flip-flop is on. When it turns off, it interrupts
> the processor and isolates the capacitor so it acts as a sample-and-hold
> device. The processor can take its own sweet time reading the capacitor
> voltage (although this sets minimum limits on the pulse duration). When
> the reading has been captured, the micro toggles a FF that shorts the
> capacitor with a cmos switch. The short is removed when the phase FF
> toggles on.
>
> This is a lot of analog circuitry, but it will operate as fast as the
> parts are capable of switching and not at the whim of whatever the micro
> is doing.
>
> Hope that's useful. Probably already been done.
>
> Bill Hawkins
>
>
> -Original Message-
> From: Magnus Danielson
> Sent: Tuesday, September 22, 2015 3:32 PM
>
> Jim,
>
> I had the intent to try this, but never got around doing it. Thanks for
> reminding me. Please share any enhancements.
>
> I did exchange some emails with Lars, but as that project never got off
> the ground, it faded out.
>
> Cheers,
> Magnus
>
>
> On 09/21/2015 10:02 PM, Jim Harman wrote:
> > Hi Can,
> >
> > For a simple analog solution, you might try a 74HC4046 phase detector
> > followed by a diode and RC network as used in Lars Walenius' GPSDO,
> > described here in the archives:
> >
> > https://www.febo.com/pipermail/time-nuts/2014-February/082820.html
> >
> > The phase detector produces a pulse whose width equals the time
> > difference between the two pulses. The RC network converts this to a
> > voltage proportional to the time difference, which you then measure
> > with the MCU's A/D converter. Using the rising edge of the signal at
> > pin 14 as the interrupt source triggers the A/D converter at the end
> > of the pulse, which corresponds to the peak of the analog signal.. The
>
> > 1 meg resistor discharges the capacitor between pulses.
> >
> > Lars' code also includes a filtering algorithm which does a nice job
> > of controlling one of the oscillators to match the 1-PPS generated by
> the GPS.
> > I have enhanced this if you are interested.
> >
>
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Magnus Danielson]

Jim,

I had the intent to try this, but never got around doing it. Thanks for 
reminding me. Please share any enhancements.


I did exchange some emails with Lars, but as that project never got off 
the ground, it faded out.


Cheers,
Magnus


On 09/21/2015 10:02 PM, Jim Harman wrote:

Hi Can,

For a simple analog solution, you might try a 74HC4046 phase detector
followed by a diode and RC network as used in Lars Walenius' GPSDO,
described here in the archives:

https://www.febo.com/pipermail/time-nuts/2014-February/082820.html

The phase detector produces a pulse whose width equals the time difference
between the two pulses. The RC network converts this to a voltage
proportional to the time difference, which you then measure with the MCU's
A/D converter. Using the rising edge of the signal at pin 14 as the
interrupt source triggers the A/D converter at the end of the pulse, which
corresponds to the peak of the analog signal.. The 1 meg resistor
discharges the capacitor between pulses.

Lars' code also includes a filtering algorithm which does a nice job of
controlling one of the oscillators to match the 1-PPS generated by the GPS.
I have enhanced this if you are interested.

On Mon, Sep 21, 2015 at 1:45 PM, Can Altineller 
wrote:




I probably need a hardware to measure the time pulses more precisely. I
thought of XOR'ing the clocks, and measuring both rising and falling edges
trough interrupts, but when the pulse is close enough, it will lead to same
condition.

Are there any solutions to this problem? Maybe an analog hack? And what
are the mostly used algorithms to tune an oscillator to another? Currently
my algorithm sign corrects the result difference, and adjusts aging
register simply by adding to it, then runs a conversion command each second
to add or substract the ppms.

This looks a lot of fun,

Best Regards,
Can Altineller
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Jim Lux]

On 9/21/15 12:13 PM, Robert LaJeunesse wrote:

The Teensy 3.1 (http://www.pjrc.com/store/teensy31.html ~$20) has a Flex Timer 
Module that appears to allow a single counter to be captured into independent 
registers from independent inputs. Not sure, but PJRC tends to run the clock 
fast (96MHz) so relative timing resolution should be much better than 0.1 
microseconds.



I was looking at the discussion of the Flex Timer on the teensy forum..
One might want to be careful about the quality of the clock fed to those 
timers.  It's the regular old CPU clock, but it runs through a DPLL.
(e.g. the crystal is a 48 MHz crystal, and converted to either 72 or 96 
MHz as you select..)


I run my teensys at 48MHz, so I could hook up a 1pps to a pin and log 
some data pretty easily.  I suspect that the ADEV will be dominated by 
the CPU crystal, so I can use any convenient 1pps.





Bob LaJeunesse


Sent: Monday, September 21, 2015 at 1:45 PM
From: "Can Altineller" <altinel...@gmail.com>
To: "Discussion of precise time and frequency measurement" <time-nuts@febo.com>
Subject: [time-nuts] algorithms and hardware for comparing clock pulses

Dear Time-nuts,

  ...
I probably need a hardware to measure the time pulses more precisely.
  ...
Are there any solutions to this problem?
  ...
Best Regards,
Can Altineller
___

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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Hal Murray]

altinel...@gmail.com said:
>I finally found a way to measure 1pps output from my DS3231's, with a mcu
> unit, and modify the aging register on the RTC, I have been able to sync
> between 2-3 microseconds between clocks by substracting and adding 0.1ppm to
> 12.8ppm, with 7 bit resolution. 

I'd expect you can do much better than that.

What are you using for a MCU?  Many of them have timer/counter units that 
latch a counter on the rising edge of a pin.  That avoids any problems with 
the interrupt response time.

Another way you can do it is to take an interrupt on the rising edge of one 
pulse and the falling edge of the other pulse.  Then you have to correct for 
the pulse width in software.  That introduces errors when the pulse width 
changes with temperature, but they are probably small.  I might trigger a 
scope on the rising edge and zoom in on the trailing edge and see how much it 
moved around when I hit the unit under test with heat or cold.


-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Jim Lux]

On 9/21/15 12:13 PM, Robert LaJeunesse wrote:

The Teensy 3.1 (http://www.pjrc.com/store/teensy31.html ~$20) has a Flex Timer 
Module that appears to allow a single counter to be captured into independent 
registers from independent inputs. Not sure, but PJRC tends to run the clock 
fast (96MHz) so relative timing resolution should be much better than 0.1 
microseconds.



A bit of googling:  FreqMeasure library for the Teensy can time stamp 
zero crossings on pin 3
Apparently, the code is there to use up to 4 pins, but it's not really 
set up for multiple pins.
It uses the hardware to capture, and then an ISR to unload the register 
and buffer them up.


It also works on Arduinos.


https://www.pjrc.com/teensy/td_libs_FreqMeasure.html

the diagram in the K20 manual shows a two stage D flip-flop synchronizer 
driven off the system clock, and then a simple rising/falling edge (or, 
really, a 0->1 or 1->0 transition detector, which then latches the counter.

(Figure 37-175 in the manual)

Is this "time-nuts" precision capable. I've not tried to drive an 
Arduino or teensy with an external clock, which I think might be a 
starting point.




Bob LaJeunesse


Sent: Monday, September 21, 2015 at 1:45 PM
From: "Can Altineller" <altinel...@gmail.com>
To: "Discussion of precise time and frequency measurement" <time-nuts@febo.com>
Subject: [time-nuts] algorithms and hardware for comparing clock pulses

Dear Time-nuts,

  ...
I probably need a hardware to measure the time pulses more precisely.
  ...
Are there any solutions to this problem?
  ...
Best Regards,
Can Altineller
___

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[time-nuts] algorithms and hardware for comparing clock pulses

[Can Altineller]

   Dear Time-nuts,

   I finally found a way to measure 1pps output from my DS3231's, with a
mcu unit, and modify the aging register on the RTC, I have been able to
sync between 2-3 microseconds between clocks by substracting and adding
0.1ppm to 12.8ppm, with 7 bit resolution.

   Since the current setup involves a mcu and interrupts to measure the
time between time pulses, *(RTC being calibrated and RTC being used as sync
signal) and when the pulses are within 1 micro seconds away, the interrupt
service routines execute consecutively, loosing microseconds of precision.

   I probably need a hardware to measure the time pulses more precisely. I
thought of XOR'ing the clocks, and measuring both rising and falling edges
trough interrupts, but when the pulse is close enough, it will lead to same
condition.

   Are there any solutions to this problem? Maybe an analog hack? And what
are the mostly used algorithms to tune an oscillator to another? Currently
my algorithm sign corrects the result difference, and adjusts aging
register simply by adding to it, then runs a conversion command each second
to add or substract the ppms.

   This looks a lot of fun,

   Best Regards,
   Can Altineller
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Robert LaJeunesse]

The Teensy 3.1 (http://www.pjrc.com/store/teensy31.html ~$20) has a Flex Timer 
Module that appears to allow a single counter to be captured into independent 
registers from independent inputs. Not sure, but PJRC tends to run the clock 
fast (96MHz) so relative timing resolution should be much better than 0.1 
microseconds.

Bob LaJeunesse

> Sent: Monday, September 21, 2015 at 1:45 PM
> From: "Can Altineller" <altinel...@gmail.com>
> To: "Discussion of precise time and frequency measurement" 
> <time-nuts@febo.com>
> Subject: [time-nuts] algorithms and hardware for comparing clock pulses
>
>Dear Time-nuts,
> 
>  ...  
>I probably need a hardware to measure the time pulses more precisely. 
>  ...
>Are there any solutions to this problem? 
>  ...
>Best Regards,
>Can Altineller
> ___
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Jim Lux]

On 9/21/15 12:13 PM, Robert LaJeunesse wrote:

The Teensy 3.1 (http://www.pjrc.com/store/teensy31.html ~$20) has a Flex Timer 
Module that appears to allow a single counter to be captured into independent 
registers from independent inputs. Not sure, but PJRC tends to run the clock 
fast (96MHz) so relative timing resolution should be much better than 0.1 
microseconds.


I have, literally, a box full of teensy 3.1s at work.
If there's a quick test that would help answer any questions, I'm 
willing to set them up.
I have, in the lab with the Teensys, a SRS Rb and a Wenzel OCXO (not a 
superduper, just the streamline).


Is there a Flex Timer Module in the teensyduino library?



Bob LaJeunesse


Sent: Monday, September 21, 2015 at 1:45 PM
From: "Can Altineller" <altinel...@gmail.com>
To: "Discussion of precise time and frequency measurement" <time-nuts@febo.com>
Subject: [time-nuts] algorithms and hardware for comparing clock pulses

Dear Time-nuts,

  ...
I probably need a hardware to measure the time pulses more precisely.
  ...
Are there any solutions to this problem?
  ...
Best Regards,
Can Altineller
___

___
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
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Re: [time-nuts] algorithms and hardware for comparing clock pulses

[Jim Harman]

Hi Can,

For a simple analog solution, you might try a 74HC4046 phase detector
followed by a diode and RC network as used in Lars Walenius' GPSDO,
described here in the archives:

https://www.febo.com/pipermail/time-nuts/2014-February/082820.html

The phase detector produces a pulse whose width equals the time difference
between the two pulses. The RC network converts this to a voltage
proportional to the time difference, which you then measure with the MCU's
A/D converter. Using the rising edge of the signal at pin 14 as the
interrupt source triggers the A/D converter at the end of the pulse, which
corresponds to the peak of the analog signal.. The 1 meg resistor
discharges the capacitor between pulses.

Lars' code also includes a filtering algorithm which does a nice job of
controlling one of the oscillators to match the 1-PPS generated by the GPS.
I have enhanced this if you are interested.

On Mon, Sep 21, 2015 at 1:45 PM, Can Altineller 
wrote:

>
>
>I probably need a hardware to measure the time pulses more precisely. I
> thought of XOR'ing the clocks, and measuring both rising and falling edges
> trough interrupts, but when the pulse is close enough, it will lead to same
> condition.
>
>Are there any solutions to this problem? Maybe an analog hack? And what
> are the mostly used algorithms to tune an oscillator to another? Currently
> my algorithm sign corrects the result difference, and adjusts aging
> register simply by adding to it, then runs a conversion command each second
> to add or substract the ppms.
>
>This looks a lot of fun,
>
>Best Regards,
>Can Altineller
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>



-- 

--Jim Harman
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