Hi Erik.
What is your counter resolution/gate time? At 1second, the interval
difference from 10MHz + 5mHz is 500ps. --mike
On Fri, Feb 18, 2022 at 11:20 AM Erik Kaashoek wrote:
> During long term testing of some 10 MHz TCXO the output frequency seems
> to jump within one second 20 mHz (
I'll second the PRS-10, I have a used unit that I am very happy with. My
only complaint is that a few times an hour it fails to produce a PPS. On
my unit I expect that the problem is that it is going out of lock
(used!!!).
--mike
On Wed, Jul 21, 2021 at 4:04 AM Dana Whitlow wrote:
> Bert,
Hi, in reading between the lines, are you saying that in practice, the
tempco of twisted pair is worse than the tempco of coax? Wouldn't any
install where that was critical include a loopback to calibrate out cable
delay?
On Sun, May 9, 2021 at 8:27 AM Poul-Henning Kamp wrote:
>
>
Hi, I wonder if you could achieve this easier with a "brute force"
approach and digitize directly at the mixing frequency? Then do the rest
with math in an FPGA. --mike
On Wed, Feb 10, 2021 at 1:20 AM Magnus Danielson wrote:
> Attila,
>
> On 2021-02-09 21:15, Attila Kinali wrote:
> > Ciao
You might also look at the IGLOO nano from Actel (now microsemi). Low
power, small package, 250MHz, as few as 100 logic elements. Unfortunately
Microsemi. -- mike
On Fri, Jul 3, 2020 at 7:44 AM Hal Murray wrote:
>
> jim...@earthlink.net said:
> > 1) All those clever handbook designs and data
HI Peter,
Ebay.de just sold one with OCXO for 350 euro
HP 5371A Frequency & Time Interval Analyzer, frequency counter OCXO calling
up the original offer
Hi,
As suggested by others, another approach could be to use a cpld of some
type, for example look at the lattice mach or the old cool-runner
varieties.
You can usually DDR the clock. This should give the same symmetry as the
input clock. With a 50% duty cycle 50MHz input this should give a
Hi Gilles, I didn't peruse the linked paper, but I usually use a re-sync
FF MC100ep51 or 52 with the clock at the pre-divider rate, and the "D"
coming from in my case an FPGA. thai eliminates the phase noise
contributed by the FPGA. The nice thing with an FPGA, is you can use the
LVDS outputs
Hi All,
I will second Bob's comment on choosing a program with PCB - Schematic
integration. I can heartily recommend Kicad. I own Altium designer, but
work remotely for an American firm from Germany. The US office uses PADs.
We have finally agreed on projects going forward to both use Kicad.
respect.
On Wed, Apr 8, 2020 at 3:46 PM wrote:
> Hi Guys,
>
> Just though you'd be interested in my prototype rubidium frequency standard
> I made in the 1990's.
>
> http://www.ptsyst.com/RFS10-FrequencyDrift.pdf
>
> I have measured its frequency at random intervals for the past 18 years.
>
>
Hi
>
> Backing up a little bit …. the PPS in on these telecom Rb’s is designed to
> easily get the part set on frequency. It’s not designed for a GPSDO
> application.
> What you are seeing is consistent with that “application target”.
>
> Bob
>
> > On Apr 7, 2020, at 6:32
Hi all,
Thank you for your feedback. I found the schematics for the PRS-10 online,
and the output is 5V HCMOS.
signal :
locked --> hc08 inhc08 out --> hc14 in hc14 out --> 4x 240 ohm
resistors -> output pin
PPS--> hc08 in
Which brings me to my next question. I have been running
Hi Tobias,
IT drop should have been IR drop. --mike
On Fri, Jan 31, 2020 at 7:14 AM Mike Ingle wrote:
> Hi Tobias,
>
> I agree with Tom, that I also like PTC fuses, but don't forget that they
> have a sometimes significant IT drop. Been there, been burned.
>
> --mike
&g
Hi Tobias,
I agree with Tom, that I also like PTC fuses, but don't forget that they
have a sometimes significant IT drop. Been there, been burned.
--mike
On Fri, Jan 31, 2020 at 3:36 AM tom burkart wrote:
> Hi Tobias,
> additional answers below:
>
> Quoting Tobias Pluess :
>
> > a) is it
Hi All,
I am not an expert here, but I can say with some certainty that a divided
clock works well. I have a system with a 4GSPS RF ADC and a aux ADC which
runs at 1/64th the RF ADC. The whole clock chain is a 10MHz ext ref -> a
LMX2581 synth -> RF ADC -> RF ADC DCO -> nb4l52 clk in with a D
agreed.
I should have looked closer, I was remembering a control loop I worked with
which implemented the DAC by either adding a quanta of charge to a cap or
removing a quanta of charge, and hand very high effective bits and worked
well. It only "glitched" when updating. I had thought that was
Since for a PLL we generally want to steer in the direction indicated by
the error signal (phase detector), a relative output DAC rather than a
absolute output DAC seems more appropriate. I would look at something like
this:
https://www.edn.com/dc-accurate-32-bit-dac-achieves-32-bit-resolution/ .
Hi Martyn,
I think a few 10s of ps 1sigma error on the 1pps output should be
achievable. If for example the Rb was free running, and had for example a
100MHz (instead of 10MHz) output, it is not too difficult to measure the
PPS arrival time of the GNSS PPS down a 10ps uncertainty relative to
Hi everyone, Thanks for your reply's. The device is indeed in 50hz land
(germany). I suspect you are right that it is 50 hz mains pickup. A
little surprising since it is a "factory," as opposed to homemade unit.
But it is almost 20years old, so the caps may be dry, or it is just a bad
design.
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