Am 01.10.2018 um 03:01 schrieb Arthur Dent:
Oops, I meant divide by 5 to get 2 followed by 8x NB3N511 work?
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That should work, also for the 12 MHz case with 6x instead of 8x.
But it still needs a second divider chip like the solution I built
Oops, I meant divide by 5 to get 2 followed by 8x NB3N511 work?
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Arthur that is a very attractive answer. I had never heard of the chip
before surely looks simple enough.
Regards
Paul
WB8TSL
On Sun, Sep 30, 2018 at 8:45 PM Arthur Dent
wrote:
> Would a divide by 2 followed by a NB3N511 work?
> ___
> time-nuts
Would a divide by 2 followed by a NB3N511 work?
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Hi,
There is clearly enough clock chips today that would fit the bill and
probably provide good enough jitter for you to operate it safely.
Look at products like this:
https://www.silabs.com/products/timing/clocks/general-purpose-clock-generators
There is more of them as you look around.
Then,
A low phase noise method is to use a dual conjugate regenerative divider with
6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.
For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.
Bruce
> On 01 October 2018 at 09:05 Bob kb8tq wrote:
>
>
>
Hi
If (as originally specified) noise and jitter are not a big deal - there are a
lot
of chips out there like the ICS570. They are designed to do weird ratio
frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board
was
one way to get it all put together.
Bob
I agree with Alex - injection-locking would be the simplest of all, if
the slight correction signal added every 16 cycles is acceptable.
Ed
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On Sun, 30 Sep 2018 19:05:16 +0200
Gerhard Hoffmann wrote:
> Wow. That's truly a Rube Goldberg design.
You are right, one can do it simpler, in a single chip:
Take a uC (STM32F030 comes to mind), use its PLL, VCO and clock output
to do the heavy lifting. No external components (beside a few
On Sat, 29 Sep 2018 20:57:14 -0700
"Tom Van Baak" wrote:
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
> 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need
> to be sub-nanosecond. The main requirement is perfect cycle count accuracy.
> This is
Almost same answer as I gave Tom. Double to 20, divide by 10, and then mix
the 2 with the original 10, You could also just divide by 5 and then mix
that 2 with the original 10. Again, filtering required. 73 - Mike
Mike B. Feher, N4FS
89 Arnold Blvd.
Howell NJ 07731
848-245-9115
Am 30.09.2018 um 15:44 schrieb Pete Lancashire:
Same question 10 to 12:-)
Same Answer.
Select pins = (1, 1, 0) for 12 instead of (1, 1, 1) for 16.
\Gerhard
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The clockblock could do that, or probably any of the newer synth chips. Phase
noise and jitter are lousy of course.
On Sep 29, 2018, 11:58 PM, at 11:58 PM, Tom Van Baak
wrote:
>What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out
>of 10 MHz? Low phase noise isn't a big
Ingrid clicked through the "you might find that useful too" - list
and stumbled across this:
<
https://www.digikey.de/product-detail/de/adafruit-industries-llc/2045/1528-1206-ND/5353666
>
\Gerhard
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Am 30.09.2018 um 06:15 schrieb Hal Murray:
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
for driving a 16 MHz
On 09/30/2018 05:57 AM, Tom Van Baak wrote:
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
> MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
> sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
> for driving a
We use the ICS527 for many applications easy to get 80 or 160 MHz. in non
critical applications I use an AC14. Have a small board, 14 and ISC only if
interested have to look for it it is pre relocation. Juerg may also have one.
Corby uses it in his latest HP5065 tests along with a AD9850
Tom,
Divide the 10 MHz down to 2 MHz in the usual way, then multiply by 8
with a cascade of three analog freq doublers separated by fairly narrow
bandpass filters. Caveats: Would need four filters total along the path
to get rid of unwanted frequency components, gain distributed along
the path
On Sun, Sep 30, 2018 at 5:58 AM Tom Van Baak wrote:
>
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
> MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
> sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
> for
Simple 100 kHz ref frequency PLL (like old cmos series) with 16 MHz VCXO (
very simple 16MHz xtal with varicap arrangement).
All parts in the ordinary spare generic stuff drawer..
Il domenica 30 settembre 2018, Bruce Griffiths
ha scritto:
> Full wave rectify the sinewave input, extract
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