Hello,
I'm playing around with various methods of collecting data for oscillator
testing and would like to try the loose PLL which requires a phase detector
(PD). I'm testing an AD8302 but that has a flat spot around 176 to 180
degrees. One of the papers I read recommended the subject PD
I'd suggest that if you wish to use a DIP or SO-8 version of a single
CFA, and attain maximum BW and flatness, on a regular board, it should
be mounted on the ground plane side, and the feedback resistor should be
underneath on the opposite surface, directly between the output and
inverting
On Sat, 15 Dec 2018 19:02:30 +0200
Anders Wallin wrote:
> That got rid of the self-oscillation - but now I am left with severe (16 dB
> @ 230 MHz) gain-peaking! (see attached figure)
Could it be, that the stray capacitance to ground of the non-inverted
input is now too big? You increased the
Hi
It would be nice to see an ADEV plot if indeed GPSDO use is a target market.
Bob
> On Dec 18, 2018, at 2:02 PM, Russ Ramirez wrote:
>
> A new part at Digikey that looks promising for disciplined oscillator
> designs.
>
> https://www.sitime.com/datasheet/SiT5155
>
> Russ
> K0WFS
>
A new part at Digikey that looks promising for disciplined oscillator
designs.
https://www.sitime.com/datasheet/SiT5155
Russ
K0WFS
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Am 17.12.18 um 16:22 schrieb Anders Wallin:
Stylish dead-bug! ;)
On my board I increased Rf/Rg to 4k7, to get rid of the gain-peaking.
With 4k7 resistors I see +20 dBc/Hz worse phase-noise with the THS3491
compared to LMH6702 :( (image attached)
If noise power scales with the resistors then it
