Hi Pete...
TAPR doesn't really discontinue things until we've sold out the quantity we've
built. Sometimes that is 100pieces, sometimes 500. It all depends on how many
we think we can sell when the kit comes out. If we sell out and still see a lot
of interest, we may do a second build. The
Hi Pete --
TAPR did one production run of the ClockBlock at the beginning of 2007,
building 100 units, and they were available until all were sold (which
IIRC took a couple of years). I'm not sure if we ever looked at doing a
second run, but I seem to remember that one of the components
I just wish the tapr would not discontinue things so fast it seems once you
see it mentioned it's discontinued
On Sun, Sep 30, 2018, 1:08 PM Bob kb8tq wrote:
> Hi
>
> If (as originally specified) noise and jitter are not a big deal - there
> are a lot
> of chips out there like the ICS570. They
Brian
There are 2 parallel feedback paths one tuned to 6MHz and the other tuned to
16MHz.
They can either share the same amp or use separate amplifiers. There's a NIST
paper on using them to divide by factors other than 2 (e.g. 3, 5 etc).
https://tf.nist.gov/general/pdf/1890.pdf
Bruce
> On 04
Hi Brian,
The typical ones have two amplifier chains in parallel and one mixer.
You take the output from the amplifier branch of your liking.
The hard part is to tune them to run in synchronous mode and ensure they
stay there, or else there is a beat pattern causing excessive jitter
over that of
Bruce-
Does such a dual conjugate regen divider use a single mixer with the BPFs in
parallel? Or are there multiple loops? I'm trying to visualize the topology.
I've built a few divide-by-2 regen dividers (both worked very well) but nothing
else.
-Brian
> On Sep 30, 2018, at 4:25 PM,
On 10/1/2018 9:01 AM, ew via time-nuts wrote:
I made a mistake in the previous post we use the ICS 570 with very good results
in many applications. So it was easy to test. This has to be the easiest and
lowest cost circuit. Start with an AC14 ST, followed by a divide by 5. I used
part of a
I made a mistake in the previous post we use the ICS 570 with very good results
in many applications. So it was easy to test. This has to be the easiest and
lowest cost circuit. Start with an AC14 ST, followed by a divide by 5. I used
part of a HC390 but a LS 90 will do. Take the 2 MHz output
Moot point with free running clock oscillators in the digitising sound
cards often used. Some of the all in one cards with fast A/D's and
FPGA's etc can take an external frequency reference.
Some "adjustment" of the data can be done in software, to calibrate the
frequency domain. Smoke and
Am 01.10.2018 um 03:01 schrieb Arthur Dent:
Oops, I meant divide by 5 to get 2 followed by 8x NB3N511 work?
___
That should work, also for the 12 MHz case with 6x instead of 8x.
But it still needs a second divider chip like the solution I built
Oops, I meant divide by 5 to get 2 followed by 8x NB3N511 work?
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Arthur that is a very attractive answer. I had never heard of the chip
before surely looks simple enough.
Regards
Paul
WB8TSL
On Sun, Sep 30, 2018 at 8:45 PM Arthur Dent
wrote:
> Would a divide by 2 followed by a NB3N511 work?
> ___
> time-nuts
Would a divide by 2 followed by a NB3N511 work?
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Hi,
There is clearly enough clock chips today that would fit the bill and
probably provide good enough jitter for you to operate it safely.
Look at products like this:
https://www.silabs.com/products/timing/clocks/general-purpose-clock-generators
There is more of them as you look around.
Then,
A low phase noise method is to use a dual conjugate regenerative divider with
6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.
For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.
Bruce
> On 01 October 2018 at 09:05 Bob kb8tq wrote:
>
>
>
Hi
If (as originally specified) noise and jitter are not a big deal - there are a
lot
of chips out there like the ICS570. They are designed to do weird ratio
frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board
was
one way to get it all put together.
Bob
I agree with Alex - injection-locking would be the simplest of all, if
the slight correction signal added every 16 cycles is acceptable.
Ed
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On Sun, 30 Sep 2018 19:05:16 +0200
Gerhard Hoffmann wrote:
> Wow. That's truly a Rube Goldberg design.
You are right, one can do it simpler, in a single chip:
Take a uC (STM32F030 comes to mind), use its PLL, VCO and clock output
to do the heavy lifting. No external components (beside a few
On Sat, 29 Sep 2018 20:57:14 -0700
"Tom Van Baak" wrote:
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of
> 10 MHz? Low phase noise isn't a big requirement and jitter doesn't need
> to be sub-nanosecond. The main requirement is perfect cycle count accuracy.
> This is
-Original Message-
From: time-nuts On Behalf Of Pete
Lancashire
Sent: Sunday, September 30, 2018 9:45 AM
To: Tom Van Baak ; Discussion of precise time and
frequency measurement
Subject: Re: [time-nuts] 10 MHz -> 16 MHz
Same question 10 to 12:-)
On Sat, Sep 29, 2018, 8:58 PM Tom Van B
Am 30.09.2018 um 15:44 schrieb Pete Lancashire:
Same question 10 to 12:-)
Same Answer.
Select pins = (1, 1, 0) for 12 instead of (1, 1, 1) for 16.
\Gerhard
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The clockblock could do that, or probably any of the newer synth chips. Phase
noise and jitter are lousy of course.
On Sep 29, 2018, 11:58 PM, at 11:58 PM, Tom Van Baak
wrote:
>What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out
>of 10 MHz? Low phase noise isn't a big
Ingrid clicked through the "you might find that useful too" - list
and stumbled across this:
<
https://www.digikey.de/product-detail/de/adafruit-industries-llc/2045/1528-1206-ND/5353666
>
\Gerhard
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Am 30.09.2018 um 06:15 schrieb Hal Murray:
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
for driving a 16 MHz
On 09/30/2018 05:57 AM, Tom Van Baak wrote:
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
> MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
> sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
> for driving a
We use the ICS527 for many applications easy to get 80 or 160 MHz. in non
critical applications I use an AC14. Have a small board, 14 and ISC only if
interested have to look for it it is pre relocation. Juerg may also have one.
Corby uses it in his latest HP5065 tests along with a AD9850
Tom,
Divide the 10 MHz down to 2 MHz in the usual way, then multiply by 8
with a cascade of three analog freq doublers separated by fairly narrow
bandpass filters. Caveats: Would need four filters total along the path
to get rid of unwanted frequency components, gain distributed along
the path
On Sun, Sep 30, 2018 at 5:58 AM Tom Van Baak wrote:
>
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
> MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
> sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
> for
Simple 100 kHz ref frequency PLL (like old cmos series) with 16 MHz VCXO (
very simple 16MHz xtal with varicap arrangement).
All parts in the ordinary spare generic stuff drawer..
Il domenica 30 settembre 2018, Bruce Griffiths
ha scritto:
> Full wave rectify the sinewave input, extract
How about three doublers: 10 MHz -> 20 -> 40 -> 80 MHz and then divide
by 5 -> 16 MHz?
Jeremy
N6WFO
On Sat, Sep 29, 2018 at 9:17 PM Hal Murray wrote:
>
>
> > What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
> > MHz? Low phase noise isn't a big requirement and jitter
> What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
> MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
> sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
> for driving a 16 MHz microcontroller from a 10 MHz
What's a clever, simple, reliable (pick 2 of 3) way to get 16 MHz out of 10
MHz? Low phase noise isn't a big requirement and jitter doesn't need to be
sub-nanosecond. The main requirement is perfect cycle count accuracy. This is
for driving a 16 MHz microcontroller from a 10 MHz Rb/Cs/GPSDO. 10
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