Re: [time-nuts] PLL behavior
At 19-09-2012, you wrote: What we want to know is what happens if the receiver and transmitter can't run at the same time? Obviously, we have less information coming into the system (we see the uplink half the time, so right there, we have a 2:1 hit) and the ground end only sees the transmit signal half the time (another 2:1 hit), so, from an information theory standpoint we've already put ourselves in a hole, but, what does the statistics really look like for the turnaround loop.. Full Duplex full power turnaround is expensive in power, mass, etc. (for instance, you have to have good filters to make sure that your receiver isn't corrupted by the transmitter) Very interesting Jim, cant tell you much about the math. Maybe a hold last value may work best ? Raj ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
In my opinion you fall in the case of disciplining with holdover... this is more like a disciplined oscillator (like a GPSDO) problem than a PLL. On Wed, Sep 19, 2012 at 1:45 AM, Jim Lux jim...@earthlink.net wrote: On 9/18/12 9:48 AM, Raj wrote: If you break the DC control chain of the PLL with a A2D and a controller and back with a D2A .. you would program the control with any kind of behavior you want. Just a thought! That is exactly what we do... the PLL is actually implemented digitally (DAC driving the VCO).. But what I'm looking for is a theoretical treatment of the output statistics (Allan Dev, mostly) in terms of the interrupted reference input. For context.. we do precision ranging of spacecraft in deep space by sending a hydrogen maser derived signal TO the spacecraft which locks a local VCXO to that signal, and then uses the VCXO to generate a return signal with a constant ratio (e.g. 880/741) to the input. By measuring the time it takes for the round trip (essentially counting phase cycles on the return signal (against our hydrogen maser, again), we measure Range and Doppler, which is then used to determine the position of the spacecraft. Typical performance is sub-meter and sub cm/sec. (A very high performance would be that the transponder adds 4E-15 Allan Dev over 1000 sec... 1E-11 or 1E-12 over 10-100 secs is more usual) What we want to know is what happens if the receiver and transmitter can't run at the same time? Obviously, we have less information coming into the system (we see the uplink half the time, so right there, we have a 2:1 hit) and the ground end only sees the transmit signal half the time (another 2:1 hit), so, from an information theory standpoint we've already put ourselves in a hole, but, what does the statistics really look like for the turnaround loop.. Full Duplex full power turnaround is expensive in power, mass, etc. (for instance, you have to have good filters to make sure that your receiver isn't corrupted by the transmitter) __**_ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/** mailman/listinfo/time-nutshttps://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
Hi Commonly this sort of thing is done with a sample and hold in the loop. No reference in / put the loop voltage in hold. You still have a phase drift and need to cope with the phase offset when the reference comes back. Bob On Sep 19, 2012, at 4:08 AM, Azelio Boriani azelio.bori...@screen.it wrote: In my opinion you fall in the case of disciplining with holdover... this is more like a disciplined oscillator (like a GPSDO) problem than a PLL. On Wed, Sep 19, 2012 at 1:45 AM, Jim Lux jim...@earthlink.net wrote: On 9/18/12 9:48 AM, Raj wrote: If you break the DC control chain of the PLL with a A2D and a controller and back with a D2A .. you would program the control with any kind of behavior you want. Just a thought! That is exactly what we do... the PLL is actually implemented digitally (DAC driving the VCO).. But what I'm looking for is a theoretical treatment of the output statistics (Allan Dev, mostly) in terms of the interrupted reference input. For context.. we do precision ranging of spacecraft in deep space by sending a hydrogen maser derived signal TO the spacecraft which locks a local VCXO to that signal, and then uses the VCXO to generate a return signal with a constant ratio (e.g. 880/741) to the input. By measuring the time it takes for the round trip (essentially counting phase cycles on the return signal (against our hydrogen maser, again), we measure Range and Doppler, which is then used to determine the position of the spacecraft. Typical performance is sub-meter and sub cm/sec. (A very high performance would be that the transponder adds 4E-15 Allan Dev over 1000 sec... 1E-11 or 1E-12 over 10-100 secs is more usual) What we want to know is what happens if the receiver and transmitter can't run at the same time? Obviously, we have less information coming into the system (we see the uplink half the time, so right there, we have a 2:1 hit) and the ground end only sees the transmit signal half the time (another 2:1 hit), so, from an information theory standpoint we've already put ourselves in a hole, but, what does the statistics really look like for the turnaround loop.. Full Duplex full power turnaround is expensive in power, mass, etc. (for instance, you have to have good filters to make sure that your receiver isn't corrupted by the transmitter) __**_ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/** mailman/listinfo/time-nutshttps://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 09/19/2012 10:08 AM, Azelio Boriani wrote: In my opinion you fall in the case of disciplining with holdover... this is more like a disciplined oscillator (like a GPSDO) problem than a PLL. It is indeed very similar, However, a second of hold-over isn't all that hard, but one has to be careful to have sufficient of frequency resolution in the DAC (which can be interpolating). There are some tricks of trades to be done to achieve good hold-over performance on the short term. ADEV isn't a very good way of characterizing this type of behaviour, but it could be plotted as well. MTIE is a better tool, as this is a systematic effect, which MTIE is designed to model. However, there is no such thing as spending quality time glaring on the TE of the behaviour. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 9/19/12 1:08 AM, Azelio Boriani wrote: In my opinion you fall in the case of disciplining with holdover... this is more like a disciplined oscillator (like a GPSDO) problem than a PLL. Good point... it's like what happens when we come out of holdover. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 9/19/12 4:38 AM, Bob Camp wrote: Hi Commonly this sort of thing is done with a sample and hold in the loop. No reference in / put the loop voltage in hold. You still have a phase drift and need to cope with the phase offset when the reference comes back. or, in our case, we run the loop, but don't have any error signal input (if you have a second or third order loop, you might as well essentially predict what is going on) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 09/20/2012 01:55 AM, Jim Lux wrote: On 9/19/12 4:38 AM, Bob Camp wrote: Hi Commonly this sort of thing is done with a sample and hold in the loop. No reference in / put the loop voltage in hold. You still have a phase drift and need to cope with the phase offset when the reference comes back. or, in our case, we run the loop, but don't have any error signal input (if you have a second or third order loop, you might as well essentially predict what is going on) The phase drift you get repeatedly should integrate up to a frequency correction. If you want to get fancy, you could separate it and do a hold-over drift correction such that a secondary integrator compensates for hold-over drift. Not too hard to do. That was you could reduce the blurp. Unless you have a very unstable system, it should behave relatively linear to the amplitude of things, and this on/off pattern will be more of a 0.5 Hz noise signal in the loop. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
won't it depend almost entirely on the charge pump filter? Don Jim Lux I'm looking for info on behavior of a PLL (with VCXO) when the reference comes and goes periodically. When the reference is gone, the PLL will flywheel according to whatever the loop filter does. (we can turn off the input to the filter, so we're not trying to track noise).. What I'm particularly interested in is the behavior in the PLL when the reference returns. The overall situation is where we are trying to make a frequency/phase measurement over 10-100 seconds, where the reference has a 50% duty cycle, and is on for a second, off for a second. I can fairly simply model this, or just try it, but I'm looking for some references to an analytical approach. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Neither the voice of authority nor the weight of reason and argument are as significant as experiment, for thence comes quiet to the mind. De Erroribus Medicorum, R. Bacon, 13th century. If you don't know what it is, don't poke it. Ghost in the Shell Dr. Don Latham AJ7LL Six Mile Systems LLP 17850 Six Mile Road POB 134 Huson, MT, 59846 VOX 406-626-4304 www.lightningforensics.com www.sixmilesystems.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
Hi Gardner in Phaselock Techniques has figure 4.8 that is a pretty good starting point. Bob -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Jim Lux Sent: Tuesday, September 18, 2012 11:29 AM To: Discussion of precise time and frequency measurement Subject: [time-nuts] PLL behavior I'm looking for info on behavior of a PLL (with VCXO) when the reference comes and goes periodically. When the reference is gone, the PLL will flywheel according to whatever the loop filter does. (we can turn off the input to the filter, so we're not trying to track noise).. What I'm particularly interested in is the behavior in the PLL when the reference returns. The overall situation is where we are trying to make a frequency/phase measurement over 10-100 seconds, where the reference has a 50% duty cycle, and is on for a second, off for a second. I can fairly simply model this, or just try it, but I'm looking for some references to an analytical approach. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
Usually in a regular PLL the missing reference should pull the output at the lowest voltage: as if the input frequency is too high. It helps if the charge pump output can be disabled when the reference stops: in this case the output voltage will go down following the droop of the integrator/filter. On Tue, Sep 18, 2012 at 5:39 PM, Don Latham d...@montana.com wrote: won't it depend almost entirely on the charge pump filter? Don Jim Lux I'm looking for info on behavior of a PLL (with VCXO) when the reference comes and goes periodically. When the reference is gone, the PLL will flywheel according to whatever the loop filter does. (we can turn off the input to the filter, so we're not trying to track noise).. What I'm particularly interested in is the behavior in the PLL when the reference returns. The overall situation is where we are trying to make a frequency/phase measurement over 10-100 seconds, where the reference has a 50% duty cycle, and is on for a second, off for a second. I can fairly simply model this, or just try it, but I'm looking for some references to an analytical approach. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Neither the voice of authority nor the weight of reason and argument are as significant as experiment, for thence comes quiet to the mind. De Erroribus Medicorum, R. Bacon, 13th century. If you don't know what it is, don't poke it. Ghost in the Shell Dr. Don Latham AJ7LL Six Mile Systems LLP 17850 Six Mile Road POB 134 Huson, MT, 59846 VOX 406-626-4304 www.lightningforensics.com www.sixmilesystems.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
If you break the DC control chain of the PLL with a A2D and a controller and back with a D2A .. you would program the control with any kind of behavior you want. Just a thought! Raj, vu2zap At 18-09-2012, you wrote: I'm looking for info on behavior of a PLL (with VCXO) when the reference comes and goes periodically. When the reference is gone, the PLL will flywheel according to whatever the loop filter does. (we can turn off the input to the filter, so we're not trying to track noise).. What I'm particularly interested in is the behavior in the PLL when the reference returns. The overall situation is where we are trying to make a frequency/phase measurement over 10-100 seconds, where the reference has a 50% duty cycle, and is on for a second, off for a second. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 9/18/12 8:39 AM, Don Latham wrote: won't it depend almost entirely on the charge pump filter? Classic PLL with a mixer, not with a Phase Frequency Detector and charge pump.. But yes, it depends in large part on the loop filter, but also on the behavior of the oscillator.. (i.e. where does it go with fixed tune input) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 09/18/2012 05:28 PM, Jim Lux wrote: I'm looking for info on behavior of a PLL (with VCXO) when the reference comes and goes periodically. When the reference is gone, the PLL will flywheel according to whatever the loop filter does. (we can turn off the input to the filter, so we're not trying to track noise).. What I'm particularly interested in is the behavior in the PLL when the reference returns. The overall situation is where we are trying to make a frequency/phase measurement over 10-100 seconds, where the reference has a 50% duty cycle, and is on for a second, off for a second. I can fairly simply model this, or just try it, but I'm looking for some references to an analytical approach. The leakage of your filter will cause the frequency to have drifted a little during the off period, so one way of modelling it would be that you would treat it like a frequency step. However, if you think a little about it, the drift will most likely not be that great so you would only shifted a somewhat in phase, and what you get is a phase step response. It's really trivial to analyze and it has already been done to great extent. It helps if you realize that a dirac delta has the LaPlace form of I(s) = 1, and then that a phase step has the formula I(s) = /|phi / s and that a phase ramp/frequency step has the formula I(s) = /|omega / s^2. Applying these I(s) to you PLLs H(s) gives you the O(s) for your response to these stress-tests. Apply inverse LaPlace transform for impulse responces. You can cheat and look it up in standard books. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 09/18/2012 06:15 PM, Bob Camp wrote: Hi Gardner in Phaselock Techniques has figure 4.8 that is a pretty good starting point. In general, it's a really good book to read. Gardner covers this field well, and even if some of the stuff I needed wasn't in there, it was an excellent startingpoint. I rather have people first read Gardner thoroughly then reading the Best book randomly. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 9/18/12 1:49 PM, Magnus Danielson wrote: On 09/18/2012 05:28 PM, Jim Lux wrote: I'm looking for info on behavior of a PLL (with VCXO) when the reference comes and goes periodically. When the reference is gone, the PLL will flywheel according to whatever the loop filter does. (we can turn off the input to the filter, so we're not trying to track noise).. What I'm particularly interested in is the behavior in the PLL when the reference returns. The overall situation is where we are trying to make a frequency/phase measurement over 10-100 seconds, where the reference has a 50% duty cycle, and is on for a second, off for a second. I can fairly simply model this, or just try it, but I'm looking for some references to an analytical approach. The leakage of your filter will cause the frequency to have drifted a little during the off period, so one way of modelling it would be that you would treat it like a frequency step. However, if you think a little about it, the drift will most likely not be that great so you would only shifted a somewhat in phase, and what you get is a phase step response. It's really trivial to analyze and it has already been done to great extent. It helps if you realize that a dirac delta has the LaPlace form of I(s) = 1, and then that a phase step has the formula I(s) = /|phi / s and that a phase ramp/frequency step has the formula I(s) = /|omega / s^2. Applying these I(s) to you PLLs H(s) gives you the O(s) for your response to these stress-tests. Apply inverse LaPlace transform for impulse responces. That is basically what I have now.. I guess the next question that leads to is how big is the phase step, and that depends on what the oscillator did (in a statistical sense) during the flywheel time, which in turn, I should be able to figure out from the Allan Deviation data. A lot of classical loop analyses (in terms of the statistics) makes the assumption that the phase detector response is linear (that is, that the error signal is linearly proportional to phase error), which is reasonable for small delta phase. But in the phase step case, that might not be. I suppose then, it's more like looking at the acquisition behavior analysis. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] PLL behavior
On 9/18/12 9:48 AM, Raj wrote: If you break the DC control chain of the PLL with a A2D and a controller and back with a D2A .. you would program the control with any kind of behavior you want. Just a thought! That is exactly what we do... the PLL is actually implemented digitally (DAC driving the VCO).. But what I'm looking for is a theoretical treatment of the output statistics (Allan Dev, mostly) in terms of the interrupted reference input. For context.. we do precision ranging of spacecraft in deep space by sending a hydrogen maser derived signal TO the spacecraft which locks a local VCXO to that signal, and then uses the VCXO to generate a return signal with a constant ratio (e.g. 880/741) to the input. By measuring the time it takes for the round trip (essentially counting phase cycles on the return signal (against our hydrogen maser, again), we measure Range and Doppler, which is then used to determine the position of the spacecraft. Typical performance is sub-meter and sub cm/sec. (A very high performance would be that the transponder adds 4E-15 Allan Dev over 1000 sec... 1E-11 or 1E-12 over 10-100 secs is more usual) What we want to know is what happens if the receiver and transmitter can't run at the same time? Obviously, we have less information coming into the system (we see the uplink half the time, so right there, we have a 2:1 hit) and the ground end only sees the transmit signal half the time (another 2:1 hit), so, from an information theory standpoint we've already put ourselves in a hole, but, what does the statistics really look like for the turnaround loop.. Full Duplex full power turnaround is expensive in power, mass, etc. (for instance, you have to have good filters to make sure that your receiver isn't corrupted by the transmitter) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
