Hi Harsh,
Sorry for the slow reply, I have been quite busy.
On 26 February 2018 at 08:14, wrote:
> Hello all,
>
> I am a senior student at IIT (BHU) Varanasi and am pursuing a bachelors
> degree in Electronics Engineering. I want to contribute to the project idea
> on
Hello All,
I am a 3rd year dual degree student at IIIT , Hyderabad currently in 3rd
year. I want to contribute to the project idea on IBERT clone using LiteX.
So,basically i have thought of some ideas to do this project which are:
1. The sub block needed to implement this project will be
Hello Harsh,
the idea with the project is to have a clone of what can be done with the
IBERT Xilinx tools:
- 1) configure transceiver TX/RX parameters (electrical, post/pre emphasis,
etc...)
- 2) configure transceiver TX to emit PRBS/ RX to receive check PRBS
(PRBS-7, 15, 23, 31).
- 3) being
Hello Harsh,
To answer your questions.
1) I started with Tim's talk in the linux.conf.au last January where he
> explains how python could be used to speed up design cycle. It was an
> excellent introduction. I wanted to understand how can we be sure that
> performance {P, L, A} of the design
Hello all,
I am a senior student at IIT (BHU) Varanasi and am pursuing a bachelors
degree in Electronics Engineering. I want to contribute to the project idea
on IBERT clone using LiteX.
I have used IBERT logicore by Xilinx in an internship before for multi-GBPS
testing of an equalizer IC.I
Hello All,
I am a senior student at IIT (BHU), Varanasi and am pursuing a bachelors
degree in Electronics Engineering. I want to contribute to the project idea
on IBERT clone using LiteX.
I have used IBERT logicore by Xilinx in an internship before for multi-GBPS
testing of an equalizer IC. I