(This is an email sent Andrius Štikonas but seems that it didn't do it
to the mailing list)
Hi,
When trying to compile gcc, we stumbled upon strange segfault that seem
to be coming from tcc.
This is the reproducer:
struct thing {
unsigned index;
char mem[1];
};
struct function {
Hi
On 2024-04-16 20:21, Paul Moore wrote:
I hope this helps,
Ekaitz
My original confusion stemmed from R_RET, I read it as returning what type of
register to use for return values.
Plus the fact that the upper level tccgen code deals in register types not
registers (gv(rc), not gv(r)).
Hi,
On 2024-04-16 13:46, Detlef Riekenberg via Tinycc-devel wrote:
My suggestions:
* Please hold back any commit before the release.
* If you think, you have an urgent change to fix an urgent bug,
discuss it on the mailing list first.
* Together, we decide, if we postpone the change after the
Hi,
On 2024-04-16 01:50, Paul Moore wrote:
Writing my own backend. I am trying to understand reg_classes
On the face of it, it looks like a list of registers with flags saying
what classes they are in (int , float..)
So get_reg works down the table looking for registers of the right
class,
. If anyone could review it,
I'd be awesome.
Thanks,
Ekaitz
From 97638d3e6a9b12bd7a209e16d28307b20edddfbb Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga
Date: Sun, 17 Mar 2024 16:07:04 +0100
Subject: [PATCH] riscv: Add extended assembly support
NOTE: In order to be able to deal with general
Hi,
Unfortunately, i do not know riscv assembly good enough to help here.
Don't worry, I'll open a new thread here if someone else can help.
Thanks,
Ekaitz
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code in `subst_asm_operand` that I'm not sure about.
--
Regards ... Detlef
Thanks,
Ekaitz
From a62179bfcf8b4d4ac816b0227a894fa94f4cbc69 Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga
Date: Sun, 17 Mar 2024 16:07:04 +0100
Subject: [PATCH] riscv: Add extended assembly support
NOTE: In order
Hi,
> > I have not other chance at the moment but make this backport, as well as I
> > already did with GCC.
> >
> > Maybe this makes some more sense to you now you know.
>
> Actually no, it doesn't.
I'm not the best person to clarify it further. I didn't take this decision.
> > Could you
Hi grischka,
> > vtop->r and vtop->cmp_r are used interchangeably in some parts of the
> > codebase and I don't really understand why.
>
> I don't know where you see this?
I'm probably mistaken by the code I read. I'm having a hard time reading it
honestly.
> Also, what is "all the C
.
Thanks a lot,
Ekaitz
--- Original Message ---
On Thursday, August 11th, 2022 at 1:36 PM, Ekaitz Zarraga
wrote:
> Hi,
>
> I think I have it mostly working following your advice but I cannot find how
> to map v->cmp_r to the field that was storing that informat
int b = (vtop->cmp_r >> 8) & 0xff;
switch (op) {
```
What do I need to replace `a` and `b` with to use the previous register access
but I can't find how to do that.
Could you please help me?
Thank you,
Ekaitz
--- Original Message ---
On Wednesday, August 10th, 2022 at
Hi,
On Wednesday, August 10th, 2022 at 1:43 PM, grischka wrote:
> On 09.08.2022 20:39, Ekaitz Zarraga wrote:
>
> > Hi all,
> >
> > I'm working on the RISC-V bootstrapping efforts for Guix, and I have to
> > backport the RISC-V backend to an older TinyCC version
I finally found them.
They are nowadays defined in the X-gen.c files, but in the past were inserted
in libtcc.c using tcc_define_symbol.
Thanks a lot anyway!
Cheers,
Ekaitz
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Hi all,
I'm working on the RISC-V bootstrapping efforts for Guix, and I have to
backport the RISC-V backend to an older TinyCC version we have patched in order
to be able to build it with a simpler compiler.
The process worked mostly ok, but I can't understand very well the `gtst`
function in
Hi,
I'm adding some features to TinyCC and I'm having trouble finding where are the
preprocessor macros defined.
For example: __riscv_xlen
I searched through the codebase and I didn't find them.
Can anyone gide me a little bit throught the codebase?
Thanks!
Looks like it's working now!
Thanks a ton!
--- Original Message ---
On Tuesday, June 7th, 2022 at 9:05 PM, Herman ten Brugge via Tinycc-devel
wrote:
> I pushed a fix.
>
> Please try again.
>
> Herman
>
>
> On 6/7/22 12:46, Ekaitz Zarraga wrote:
>
>
Hi,
I've been trying to assemble small riscv64 programs with a cross compiler built
by `make cross-riscv64` and I get weird errors.
It's like instructions like `add a0,zero,zero` are not available, because it's
asking for another argument.
Am I doing something wrong?
Thanks,
Ekaitz
> With that in mind, I suppose that the differences between these two will be
> the length of the registers. So someone should be able to modify the TCC's
> "RISC-V64" version and make it support the 32-bit RISC-V with a couple of
> changes to both the backend and in the frontend (I suppose
Hi there,
> I tried to read the Tiger Book with examples. I tried to learn Bison. I
> tried to learn Lemon Parser. I could not write the grammar for a for-loop.
> I don't know if that's because if stupid, if it wasn't well explained or if
> it's difficult.
There are various books that explain
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