On Mon, Aug 07, 2017 at 09:09:40AM -0500, Haris Okanovic wrote: > I have a latency issue using a SPI-based TPM chip with tpm_tis driver > from non-rt usermode application, which induces ~400 us latency spikes > in cyclictest (Intel Atom E3940 system, PREEMPT_RT_FULL kernel). > > The spikes are caused by a stalling ioread8() operation, following a > sequence of 30+ iowrite8()s to the same address. I believe this happens > because the writes are cached (in cpu or somewhere along the bus), which > gets flushed on the first LOAD instruction (ioread*()) that follows.
I guess it is possible, the LPC bridge might have a small FIFO for posted writes from the CPU. That is how I run the LPC hardware on my ARM SOCs, for instance. I can't think of another approach, but this is pretty ugly, honestly.. non-DMA peripherals and RT seems fairly incompatible, IMHO.. Jason ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ tpmdd-devel mailing list tpmdd-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/tpmdd-devel
