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Proposal for a Post-doctoral Position ===================================== Title ===== Analyses and scheduling for advanced dataflow programming Location ======== Grenoble (France): CRI and INRIA Grenoble (Pop Art Team). Supervisors =========== INRIA Grenoble: Pascal FRADET and Alain GIRAULT. ST Microelectronics Ottawa: Ali-Erdem OZCAN and Pierre PAULIN. Application =========== Please send your CV and recommendation letters to alain.gira...@inria.fr and pascal.fra...@inria.fr. The postdoc funding is for 12 months. The net income is around 2100 € per month and includes health insurance coverage. Abstract ======== In this project, we focus on dataflow models of computation to program applications for a new embedded many-core platform designed by ST Microelectronics, called P2012. The static dataflow model of computation (SDF) is widely used because it allows analysis (deadlock and boundedness) and scheduling. SDF has a clean semantics and leads to efficient implementations but it cannot express many dynamic features. In particular, it cannot express dynamic input/output rate modifications, nor dynamic topology modifications. For this reason, many variants of SDF have been proposed, among which we can cite BDF, CSDF, HDF, and PSDF. Our objective for this project is to propose a variant of SDF able to express dynamicity while remaining verifiable (for deadlock and buffer boundedness) and schedulable. For rate modifications, PSDF offers a good trade off between expressiveness and verifiability. For dynamic topology modifications, HDF offers also a good trade off. Therefore, a combination of PSDF and HDF looks like a promising candidate as a SDF variant for our project. This point has been validated by ST Microelectronics. The postdoc should participate with ST Microelectronics to the definition of such a variant. The verification and analysis of that variant should be studied. The two main properties to guarantee are the absence of deadlocks and the boundedness of communication buffers. Another important point will be the study of a distributed scheduling of the SDF-variant programs, so that programs can be efficiently executed on the many-cores platform. To this end, a particular attention will be devoted to the minimization of the communication costs, in accordance to the memory hierarchy of the P2012 platform. To summarize, the work will consist in three main tasks: - the participation to the definition of the SDF variant (a mix of PSDF and HDF) with ST Ottawa; - the verification and analysis of the chosen variant (deadlock detection and buffer size analysis); - the scheduling (generation of a centralized version and a distributed version). Required Skills =============== A PhD in formal methods, embedded systems, and/or real-time programming (e.g. analysis, semantics, verification, validation, code generation, ...). A knowledge of dataflow programming and/or scheduling would be a plus. Context ======= The context of this work is the ST Microelectronics Platform 2012 initiative (P2012). P2012 is a many-core platform that integrates multiple clusters of processors and HW accelerators with a hierarchical memory architecture and a NoC. The position is likely to involve travels between Grenoble (Inria) and Ottawa (ST Microelectronics). The CRI is the recently created Integration Research Centre, a joint laboratory between two universities (Grenoble-INP and UJF) and three French research institutes (CEA, CNRS, and INRIA). Its purpose is to build bridges between industry and research to cut down time-to-market for innovative products, particularly smart miniaturized solutions. The main goal of the POP ART team (http://pop-art.inrialpes.fr) is the safe design of real-time embedded systems. We explore that area according to several research directions: programming languages, models of computation, static analysis, formal verification, implementation, ... The research within POP ART concerns: - design (component and interaction models for real-time systems, heterogeneity); - programming (synchronous, domain specific and aspect-oriented languages); - verification and correctness by construction (controller synthesis, compositionally, ...); - code generation (scheduling, fault-tolerance, compilation, ...). -- ------------- Alain GIRAULT http://pop-art.inrialpes.fr/~girault INRIA senior researcher tel: +(33|0) 476 61 53 51 Head of the POP ART project-team fax: +(33|0) 476 61 52 52 ----------------------------------------------------------------------------- Sauvons la Recherche ! http://www.sauvonslarecherche.fr -----------------------------------------------------------------------------