Fix the comment to reflect the actual function call time.
Change the printf message to look nicer in the context it might be printed.
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
board/cm_t35/cm_t35.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Signed-off-by: Stefano Babic sba...@denx.de
---
board/technexion/twister/twister.c | 49
include/configs/twister.h | 10
2 files changed, 59 insertions(+)
diff --git a/board/technexion/twister/twister.c
Signed-off-by: Stefano Babic sba...@denx.de
---
arch/arm/include/asm/arch-omap3/dss.h | 23 ---
drivers/video/omap3_dss.c | 40 -
2 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/dss.h
Signed-off-by: Stefano Babic sba...@denx.de
---
arch/arm/include/asm/arch-omap3/clocks.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-omap3/clocks.h
b/arch/arm/include/asm/arch-omap3/clocks.h
index bed0002..ab7b703 100644
---
Signed-off-by: Stefano Babic sba...@denx.de
---
board/teejet/mt_ventoux/mt_ventoux.c | 63 ++
board/teejet/mt_ventoux/mt_ventoux.h |2 +-
include/configs/mt_ventoux.h | 17 +
3 files changed, 81 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Stefano Babic sba...@denx.de
CC: Tom Rini tr...@ti.com
---
board/htkw/mcx/mcx.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
index d675a48..867cc9e 100644
--- a/board/htkw/mcx/mcx.h
+++
Signed-off-by: Stefano Babic sba...@denx.de
CC: Tom Rini tr...@ti.com
---
include/configs/mcx.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 1315c3c..6159268 100644
--- a/include/configs/mcx.h
+++
Detect hot-water-button to start a differnt image.
Signed-off-by: Stefano Babic sba...@denx.de
CC: Tom Rini tr...@ti.com
---
board/htkw/mcx/mcx.c | 23 +++
include/configs/mcx.h |2 ++
2 files changed, 25 insertions(+)
diff --git a/board/htkw/mcx/mcx.c
Patch drops also not used CFI setup in the
configuration file.
Signed-off-by: Stefano Babic sba...@denx.de
CC: Tom Rini tr...@ti.com
---
include/configs/mcx.h | 128 +++--
1 file changed, 91 insertions(+), 37 deletions(-)
diff --git
For some reason, bit 1 (connect status change) of PORTSC will be set
after issuing Port Reset (like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we add a definition in header file to ignore checking of that bit
after Port Reset.
Hi Kim,
On 03/21/2012 01:42 PM, Holger Brunck wrote:
This additional header is unneeded, we can use the tuxx1.h for this
target.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Kim Phillips kim.phill...@freescale.com
cc: Valentin Longchamp valentin.longch...@keymile.com
cc:
From: Surendra Barku Dhobale
Sent: Thursday, June 14, 2012 6:02 PM
To: 'U-Boot@lists.denx.de'
Subject: Is RSA algorithm support for the software authentication in u-boot?
Hi ,
I am looking for the RSA , public key authentication for the images
like u-boot.img ,uImage from the u-boot.
Hi ,
I am looking for the RSA , public key authentication for the images
like u-boot.img ,uImage from the u-boot. In u-boot already support for the
SHA1 and md5,that's great!!!. But I want to use RSA algorithm for more security
and official firmware releases.
Is there any support for
Hi Rajeshwari,
This patch has too many dependence with other patches.
(Pinmux and PeripID, patches for MSHCI setting).
And as i mentioned, designWare controller isn't exynos specific.
I think good that separate two files. (dw_mmc.c and exynos_dw_mmc.c)
Like this...dw_mmc.c is generic code and
From: Michael Langer michael.lan...@de.bosch.com
The commit i.mx: fsl_esdhc: add the i.mx6q support (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.
MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in i.MX6 silicon. However,
Hi All,
On Thu, May 31, 2012 at 1:41 AM, Ilya Yanok
ilya.ya...@cogentembedded.comwrote:
This is a draft implementation of cache coherent memory allocator.
This simple implementation just reserves memory area below malloc
space and leave it uncached even if data cache is enabled.
Allocations
On Wed, Jun 06, 2012 at 01:15:57AM +0200, Simon Guinot wrote:
This patch series provides bug fixes for LaCie devices (mostly for
Internet Space v2 and 2Big Network v2).
Changes for v2:
- Move bug fixes into a separate patch set.
Simon Guinot (3):
lacie_kw: fix SDRAM banks number for
On Wed, Jun 06, 2012 at 01:16:49AM +0200, Simon Guinot wrote:
Changes for v2:
- Move board support and feature into a separate patch set.
- Move mach-types update into a separate patch.
Simon Guinot (4):
lacie_kw: add support for EFI partitions
ARM: add netspace_mini_v2 to
Tom, guys,
I've just found that I forgot to mention that this version requires my
patch [1] to work with enabled D-Cache correctly.
Hope to get some comments on it soon.
[1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/132464
Regards, Ilya.
On Fri, Jun 8, 2012 at 5:12 PM, Ilya Yanok
-Original Message-
From: Simon Guinot [mailto:si...@sequanux.org]
Sent: 14 June 2012 20:41
To: Simon Guinot
Cc: Prafulla Wadaskar; u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2 0/3] Bug fixes for LaCie devices
On Wed, Jun 06, 2012 at 01:15:57AM +0200, Simon Guinot wrote:
On 06/13/2012 10:17 PM, Jim Lin wrote:
Add support for command line usb reset or usb start to initialize
, usb stop to stop multiple USB controllers at once.
Other commands like usb tree also support multiple controllers.
These patches also need to be sent to the USB maintainer since they
On 06/14/2012 04:40 AM, Jim Lin wrote:
For some reason, bit 1 (connect status change) of PORTSC will be set
after issuing Port Reset (like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we add a definition in header file to
Dear Surendra Barku Dhobale,
From: Surendra Barku Dhobale
Sent: Thursday, June 14, 2012 6:02 PM
To: 'U-Boot@lists.denx.de'
Subject: Is RSA algorithm support for the software authentication in
u-boot?
Hi ,
I am looking for the RSA , public key authentication for the
images like
Dear Stephen Warren,
On 06/13/2012 10:17 PM, Jim Lin wrote:
Add support for command line usb reset or usb start to initialize
, usb stop to stop multiple USB controllers at once.
Other commands like usb tree also support multiple controllers.
These patches also need to be sent to the
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms (where
our cacheline size is 64 not 32). First, the dcache_off call that
ehci-omap had been doing was now not happening soon enough to paper over
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off).
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/cache_v7.c | 11 +++
1 file changed, 11
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
---
Can i share patches for start u-boot on tms320c6745 processor
(http://www.ti.com/product/tms320c6745)?
What is the best way?
May be somebody already make support c6000 (c6x) arch in u-boot?
For information:
C6X family of processors supported by gcc from version 4.7.0.
C6745 pin compatible with
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/usb/host/ehci-omap.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host/ehci-omap.c
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini
On 06/14/2012 12:29 PM, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum.
Cc: Marek
Dear Tom Rini,
On 06/14/2012 12:29 PM, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
On 06/14/2012 12:41 PM, Marek Vasut wrote:
Dear Tom Rini,
On 06/14/2012 12:29 PM, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use
Dear Tom Rini,
On 06/14/2012 12:41 PM, Marek Vasut wrote:
Dear Tom Rini,
On 06/14/2012 12:29 PM, Marek Vasut wrote:
Dear Tom Rini,
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for
cache
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/usb/host/ehci-omap.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host/ehci-omap.c
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms (where
our cacheline size is 64 not 32). First, the dcache_off call that
ehci-omap had been doing was now not happening soon enough to paper over
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to usb.h to define USB_DMA_MINALIGN and
make use of it in
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off).
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/cache_v7.c | 11 +++
1 file changed, 11
Dear Dmitry Bondar,
Can i share patches for start u-boot on tms320c6745 processor
(http://www.ti.com/product/tms320c6745)?
Yes you can share patches.
What is the best way?
Use git send-email and send them to this list.
May be somebody already make support c6000 (c6x) arch in u-boot?
Is
Dear Tom Rini,
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Poor USB maintainer isn't CCed :'-(
Signed-off-by: Tom Rini tr...@ti.com
But this is always a good thing to see.
Acked-by: Marek Vasut
Dear Tom Rini,
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off).
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/cache_v7.c | 11 +++
Dear Tom Rini,
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms (where
our cacheline size is 64 not 32).
Good thing, it made a bug surface ;-)
First, the dcache_off call that
ehci-omap had
On 06/14/2012 03:00 PM, Marek Vasut wrote:
Dear Tom Rini,
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off).
Signed-off-by: Tom Rini tr...@ti.com
---
On 06/14/2012 03:02 PM, Marek Vasut wrote:
Dear Tom Rini,
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms (where
our cacheline size is 64 not 32).
Good thing, it made a bug surface ;-)
On 06/14/2012 02:57 PM, Marek Vasut wrote:
Dear Tom Rini,
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Poor USB maintainer isn't CCed :'-(
Whoops, forgot. I don't know why I thought it was you :)
On 06/13/2012 10:19 AM, Simon Glass wrote:
This is a commonly-used requirement, so add a function to support it
easily.
Uggh. Why would this ever be needed; shouldn't the driver for the node
referenced by the phandle fully control its own registers; why would any
other driver randomly trample
Dear Tom Rini,
On 06/14/2012 03:00 PM, Marek Vasut wrote:
Dear Tom Rini,
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off).
Signed-off-by: Tom Rini
Dear Tom Rini,
On 06/14/2012 03:02 PM, Marek Vasut wrote:
Dear Tom Rini,
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms
(where our cacheline size is 64 not 32).
Good thing,
On 06/13/2012 10:19 AM, Simon Glass wrote:
Add support for a default pin mapping for display1.
+static const struct pingroup_config disp1_default[] = {
+ PINMUX(LM0, RSVD4, NORMAL,NORMAL),
+ PINMUX(LPW1, RSVD4, NORMAL,TRISTATE),
Do you really need to explicitly
On 06/13/2012 10:19 AM, Simon Glass wrote:
Add LCD definitions and also a proposed binding for LCD displays.
The PWFM is in progress on the device-tree-discuss list, so only a
very basic binding is offered here.
I believe we have settled on a final representation, it just hasn't been
added
On 06/13/2012 10:19 AM, Simon Glass wrote:
The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.
Surely this should be modeled as a driver that's instantiated from DT,
which provides n PWMs. As such, I'd expect the
On 06/13/2012 10:19 AM, Simon Glass wrote:
From: Wei Ni w...@nvidia.com
Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.
diff --git a/arch/arm/include/asm/arch-tegra2/display.h
On 06/13/2012 10:19 AM, Simon Glass wrote:
This driver supports driving a single LCD and providing a U-Boot console
on it.
+int fdt_decode_lcd(const void *blob, struct fdt_lcd *config)
+ fdtdec_decode_gpio(blob, display_node, nvidia,backlight-vdd-gpios,
+
On 06/13/2012 10:19 AM, Simon Glass wrote:
Add calls to the LCD driver from Nvidia board code.
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
@@ -87,6 +88,9 @@ int board_init(void)
+#ifdef CONFIG_VIDEO_TEGRA2
+ tegra_lcd_check_next_stage(gd-blob, 0);
+#endif
On 06/13/2012 10:19 AM, Simon Glass wrote:
Add support for adjusting the cachability of an L1 section by updating
the MMU. The mmu_set_region_dcache() function allows drivers to make
these changes after the MMU is set up.
It is implemented only for ARMv7 at present.
This is needed for LCD
On 06/13/2012 10:19 AM, Simon Glass wrote:
This provides an option for the LCD to flush the dcache after each update
(puts, scroll or clear).
diff --git a/common/cmd_echo.c b/common/cmd_echo.c
+ /* Use puts() so that the LCD sees it as a new line */
if (putnl)
-
On 10 June 2012 05:13, Simon Glass s...@chromium.org wrote:
On Wed, Jun 6, 2012 at 10:54 PM, Rajeshwari Shinde rajeshwar...@samsung.com
wrote:
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.
On 10 June 2012 05:15, Simon Glass s...@chromium.org wrote:
On Wed, Jun 6, 2012 at 10:54 PM, Rajeshwari Shinde rajeshwar...@samsung.com
wrote:
Use the pinmux configuration function for SMDK5250.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Rajeshwari Shinde
Hi Tom,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rini tr...@ti.com wrote:
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off).
Today we do cache maintenance
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