Hello all!
I have some problem when using NAND flash manufactured by Toshiba.
The device ID is 0xD7 , value 4Gbyte, page size 0x1000,
erase blocksize 0x8.
The board is at91sam9260 based custom board.
At first I was a normal performance of the board with a chip
samsung k9k8g08 and u-boot
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to
This patch series attempts to simplify #ifdef complexity in common/lcd.c.
It was compile tested on Arm and PowerPC using MAKEALL
checkpatch reports warnings on some of the patches:
0003: WARNING: use of volatile is usually wrong
Since 'volatile' was in the original code I left it in the
Simplify lcd_logo by extracting bmp unzip into its own function.
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V2:
- used bitmap_display() to further simplify code
common/lcd.c | 12 +---
1 files changed, 1 insertions(+), 11 deletions(-)
diff --git
Move highly platform dependant code into its own functions to reduce the
number of #ifdefs in lcd_display_bitmap
To avoid breaking the mcc200 board which does not #define
CONFIG_CMD_BMP, this patch also implements bmp_display() for mcc200.
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Move highly platform dependant code into its own function to reduce the
number of #ifdefs in the bigger functions
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
common/lcd.c | 58
Simplify lcd_display by centralizing code into a funciton
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor Grinberg grinb...@compulab.co.il
---
common/lcd.c | 27 ++-
1 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/common/lcd.c
Dear Prabhakar Kushwaha,
In message 4fe7efa1.2050...@freescale.com you wrote:
Please help me in closing review related comments on this patch.
It appears most people here on the mailing list see not much need for
changing the debug flags, probbaly because nobody is using the single
tool that
Dear Michal Simek,
In message 4fe7f154.80...@monstr.eu you wrote:
On 06/21/2012 09:42 PM, Stephan Linz wrote:
To save memory the UBIFS is disabled by default.
The original patch was introdused with commit:
0114da7b06bd47b7f5c3f20a152dd11903b38fba
This say nothing to me.
Format is
Dear Nikita Kiryanov,
In message 1340607844-8718-4-git-send-email-nik...@compulab.co.il you wrote:
Move highly platform dependant code into its own function to reduce the
number of #ifdefs in the bigger functions
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Signed-off-by: Igor
From: Lad, Prabhakar prabhakar@ti.com
This series adds MMC/SD, NAND and NOR SPL support
for Logic PD's DA850/OMAP-L138 EVM. This series
also fixes some issues found on the EVM during
testing. The patches are sent in a series as these
patches need to be applied in the order they are sent.
The
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for MMC/SD on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for v2:
1:Removed
From: Rajashekhara, Sudhakar sudhakar@ti.com
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
GP0[11] is low, the SD0 interface will not work, but NOR
flash will. When GP0[11] is high, SD0 will work but NOR
flash will not.
From: Rajashekhara, Sudhakar sudhakar@ti.com
On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot
work together. This patch enables the MMC/SD support only
when NOR support is disabled. NOR Flash identification works
even without this patch, but erase and write will have issues.
From: Lad, Prabhakar prabhakar@ti.com
initialize baudrate, flags, data and serial initialization,
only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath
From: Lad, Prabhakar prabhakar@ti.com
define SPI specific configs for SPL only when CONFIG_USE_SPIFLASH
config is defined
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
From: Lad, Prabhakar prabhakar@ti.com
Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm:
setup the NAND flash timings) has configured the AEMIF timings, they
are not exactly in sync with the timings used in Linux. Linux is
configuring the timing register as 0x0804, where
From: Lad, Prabhakar prabhakar@ti.com
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the
From: Lad, Prabhakar prabhakar@ti.com
This patch adds configuration required for NAND SP
on DA850/OMAP-L138.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Signed-off-by: Hadli, Manjunath manjunath.ha...@ti.com
---
Changes for
From: Lad, Prabhakar prabhakar@ti.com
This patch adds support for direct NOR boot mode on
da850/omap-l138. Added da850evm_direct_nor entry in
boards.cfg to allow to build targets.
Signed-off-by: Lad, Prabhakar prabhakar@ti.com
Signed-off-by: Rajashekhara, Sudhakar sudhakar@ti.com
Thanks Wolfgang for the reply.
Please find my reply in-lined
On 06/25/2012 12:51 PM, Wolfgang Denk wrote:
Dear Prabhakar Kushwaha,
In message 4fe7efa1.2050...@freescale.com you wrote:
Please help me in closing review related comments on this patch.
It appears most people here on the
Hello :)
I have the board with u-boot and I want modify the firmware.
To modify I must find rootfs files. I look for the files firmware (hexedit)
and I don't visible the rootfs files. vmlinuz I'm extract good.
What I must do to etract the rootfs ( I must find the dir: /etc/ /home/)???
Please
This patch depends on Nobuhiro Iwamatsu's arm: rmobile: Add supoprt for KMC
KZM-A9-GT board
Reserve first 16MB for RT-CPU (as same as kernel config).
Without this patch, kernel can't get ATAGS info from u-boot properly.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
I tried nfs command on KZM-A9-GT board and it fails every time with ERROR:
Cannot umount.
Current NFS_TIMEOUT value is 2000UL. It seems too short. I changed this to
1UL then it succeeds.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
net/nfs.c |2 +-
1 file changed, 1
NetSetTimeout sets incorrect value to timeDelta when CONFIG_SYS_HZ != 1000.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
net/net.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/net.c b/net/net.c
index 9de7d92..ac9c2c8 100644
--- a/net/net.c
+++ b/net/net.c
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
save_boot_params_default() in cpu.c accesses uninitialized stack area
when it compiled with -O0 (not optimized).
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
arch/arm/cpu/armv7/cpu.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/cpu.c
Dear Bo Shen,
Hi Marek,
On 6/25/2012 10:57, Marek Vasut wrote:
Dear Bo Shen,
Hi Marek,
On 6/21/2012 18:17, Marek Vasut wrote:
Dear Bo Shen,
Some Atmel SoC support USB EHCI, add the EHCI driver to support it.
To enable the USB EHCI, add the following configuration
On 06/25/2012 06:40 AM, Tetsuyuki Kobayashi wrote:
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
On 06/25/2012 12:40 AM, Jim Lin wrote:
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we
From: seedshope bocui...@gmail.com
Signed-off-by: Zhong Hongbo bocui...@gmail.com
---
Makefile | 20
board/samsung/smdk6400/config.mk |4 +---
boards.cfg |2 ++
include/configs/smdk6400.h |2 +-
4 files
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/25/2012 12:35 AM, Prabhakar Lad wrote:
From: Lad, Prabhakar prabhakar@ti.com
This series adds MMC/SD, NAND and NOR SPL support for Logic PD's
DA850/OMAP-L138 EVM. This series also fixes some issues found on
the EVM during testing.
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option is to use bounce buffer,
Or get cache coherent hardware. :-)
Am Montag, den 25.06.2012, 09:22 +0200 schrieb Wolfgang Denk:
Dear Michal Simek,
In message 4fe7f154.80...@monstr.eu you wrote:
On 06/21/2012 09:42 PM, Stephan Linz wrote:
To save memory the UBIFS is disabled by default.
The original patch was introdused with commit:
Am Montag, den 25.06.2012, 06:55 +0200 schrieb Michal Simek:
On 06/21/2012 09:42 PM, Stephan Linz wrote:
Use XILINX_FLASH_START to set/unset FLASH and RAMENV.
Error was:
board.c: In function 'board_init':
board.c:134: error: 'XILINX_FLASH_START' undeclared (first use in this
On Thu, Jun 21, 2012 at 05:00:39PM -0700, Allen Martin wrote:
Change the mkdir commands for the object directories to be more
general purpose. This fixes an issue when building for SPL where
SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE.
Signed-off-by: Allen Martin
C6X (C6000) is family of fixed and floating-point DSPs manufactured by Texas
Instruments.
---
Changes for v2:
- reset_c.c rewritten with readl/writel.
- Tom Rini tr...@ti.com added to cc
Changes for v3:
- fix coding style
- arch/c6x/include/asm/io.h - add memory
C6X has subfamilys: C62x C64x C66x C67x C645x C674x.
This patch add support of subfamily C674x (C6745/C6746/C6747 CPUs).
Signed-off-by: Dmitry Bondar b...@inmys.ru
Cc: Tom Rini tr...@ti.com
---
arch/c6x/cpu/c674x/Makefile | 30
arch/c6x/cpu/c674x/cache.c | 17 +
C674x CPUs has same peripherals(uart,emac,nand contoller) like sitara
processors (am1705/am1707/omapl137/omapl138).
In u-boot this peripheral known as davinci SOC, and placed in
arch/arm/cpu/arm926ejs/davinci
This patch allow compile davinci SOC code whith c674x CPU.
Reset code rewritten in C
Add support board c6745-som (http://inmys.ru/?_=/products/som_c6745) with C6745
cpu.
Signed-off-by: Dmitry Bondar b...@inmys.ru
Cc: Tom Rini tr...@ti.com
---
MAINTAINERS |3 +
board/inmys/c6745-som/Makefile| 27
board/inmys/c6745-som/c6745-som.c | 246
Hi Marek,
On Sun, Jun 24, 2012 at 7:17 PM, Marek Vasut ma...@denx.de wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option is to use bounce buffer, but
Hi Marex,
On Sun, Jun 24, 2012 at 7:17 PM, Marek Vasut ma...@denx.de wrote:
The asix driver did not align buffers, therefore it didn't work
with data cache enabled. Fix this.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Joe Hershberger joe.hershber...@gmail.com
---
Acked-by: Joe Hershberger
Hi at All,
I need a little help:
My Hardware:
Power PC MPC8641D
Board freescale MPC8641hpcn
I want to turn on the debug in file hush.c
I see in source code “hush.c”, as example:
debug_printf(parse_stream: ch=%c (%d) m=%d quote=%d - %c\n,
ch = ' ' ? ch : '.', ch, m,
Modified the arch-kirkwood header so KWGBE_PORT_SERIAL_CONTROL1_REG(x)
returns the correct address.
Originally calling KWGBE_PORT_SERIAL_CONTROL1_REG(1) returned the
address for port 0 and vice versa.
Doesn't have any knock on effects to the u-boot code as the only
time they're used is to do
On 06/24/2012 03:38 PM, Сергей К. wrote:
Hello all!
I have some problem when using NAND flash manufactured by Toshiba.
The device ID is 0xD7 , value 4Gbyte, page size 0x1000,
erase blocksize 0x8.
The board is at91sam9260 based custom board.
At first I was a normal performance of the
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote:
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other
On 06/25/2012 01:43 PM, Tom Rini wrote:
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote:
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate
Hi Michael,
On Fri, Jun 22, 2012 at 4:24 PM, Michael Walle mich...@walle.cc wrote:
If the requested length is too small to hold the received packet,
eth_receive() will return -1 and will leave the packet in the receive
buffers. Instead of returning an error in this case, we return the first
Hi Aneesh,
BTW, I agree that enabling un-aligned access is not a bad idea.
Just being not a bad idea is not enough for me to accept this. It
will have to be the sole sound solution to a problem, and at this
point, I do not think it is as far as USB structure mis-alignement
issues are
From: Mathieu J. Poirier mathieu.poir...@linaro.org
Following ARM's reference manuel for initializing the cache - the
kernel won't boot otherwise.
Signed-off-by: Mathieu Poirier mathieu.poir...@linaro.org
Signed-off-by: John Rigby john.ri...@linaro.org
---
Changes for v2:
- Correcting cache
From: Mathieu J. Poirier mathieu.poir...@linaro.org
Some CPU (i.e u8500) need more cache management before launching
the Linux kernel.
Signed-off-by: Mathieu Poirier mathieu.poir...@linaro.org
Signed-off-by: John Rigby john.ri...@linaro.org
---
Changes for v2:
- Moved from __attribute__(...)
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/25/2012 01:08 PM, Scott Wood wrote:
On 06/25/2012 01:43 PM, Tom Rini wrote:
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote:
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
[removed Piotr Kruszynski from CC because mail address does not exist anymore]
Hi Joe,
Am Montag 25 Juni 2012, 22:25:56 schrieb Joe Hershberger:
Hi Michael,
On Fri, Jun 22, 2012 at 4:24 PM, Michael Walle mich...@walle.cc wrote:
If the requested length is too small to hold the received
Hello :)
Hi
I have the board with u-boot and I want modify the firmware.
To modify I must find rootfs files. I look for the files firmware (hexedit)
and I don't visible the rootfs files. vmlinuz I'm extract good.
What I must do to etract the rootfs ( I must find the dir: /etc/ /home/)???
Simon,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Wednesday, June 13, 2012 3:58 PM
To: Simon Glass
Cc: U-Boot Mailing List; Tom Warren
Subject: Re: [PATCH v2 0/19] tegra: Add display driver and LCD support for
Seaboard
On 06/13/2012 10:19 AM,
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This macro returns 1 if the argument (address) is aligned, returns
zero otherwise. This will be used to test user-supplied address to
various commands to prevent user from loading data to/from unaligned
address when using caches.
This is made as a
On 06/25/2012 03:48 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/25/2012 01:08 PM, Scott Wood wrote:
On 06/25/2012 01:43 PM, Tom Rini wrote:
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote:
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the
Hi Nobuhiro,
On Thu, 21 Jun 2012 15:23:39 +0900,
Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote :
The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM,
USB, Ethernet, and more.
This patch supports the following functions:
- 512MB DDR2-SDRAM
- 16MB NOR
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/25/2012 02:17 PM, Scott Wood wrote:
On 06/25/2012 03:48 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1
On 06/25/2012 01:08 PM, Scott Wood wrote:
On 06/25/2012 01:43 PM, Tom Rini wrote:
On Mon, Jun 25, 2012 at 11:58:10AM
Hi Prafulla,
u-boot-marvell.git is cloned from u-boot-arm.git, and I always sync with
this before any task. And just to keep it clean for pull requests I would
not like to pull any other repository in it.
i just got informed by albert, that he updated his tree. So hopefully the
patchset can
Hi Albert,
Am Montag, den 25.06.2012, 22:17 +0200 schrieb Albert ARIBAUD:
Hi Lucas,
On Sun, 24 Jun 2012 08:30:19 +0200, Lucas Stach d...@lynxeye.de wrote:
Hi Albert,
Am Samstag, den 23.06.2012, 11:01 +0200 schrieb Albert ARIBAUD:
[snip]
But apart from this, we certainly have
Dear Tetsuyuki Kobayashi,
In message 4fe85b13.5080...@kmckk.co.jp you wrote:
I tried nfs command on KZM-A9-GT board and it fails every time with ERROR:
Cannot umount.
KZM-A9-GT board? This is an out of tree port, isn't it?
Are you sure the problems are not in the board specific code?
Dear Thies Peter Thiesen,
In message 20120625161735.141...@gmx.net you wrote:
I need a little help:
Please learn to use tools. For example, grep is your friend.
I want to turn on the debug in file hush.c
I see in source code “hush.c”, as example:
debug_printf(parse_stream: ch=%c (%d)
Hi Albert,
On 06/25/2012 01:34 PM, Albert ARIBAUD wrote:
Hi Aneesh,
BTW, I agree that enabling un-aligned access is not a bad idea.
Just being not a bad idea is not enough for me to accept this. It
will have to be the sole sound solution to a problem, and at this
point, I do not think it is
Dear Aneesh V,
In message 4fe8dce7.7090...@ti.com you wrote:
What is the (non-contrived) problem to which allowing mis-aligned
accesses would be a solution?
memcpy() when there is a mismatch in the alignment of source and
destination buffers. Let's say the source buffer is 4 byte
On Mon, Jun 25, 2012 at 10:02:38PM +0400, Dmitry Bondar wrote:
C6X (C6000) is Texas Instruments architecture of fixed and floating-point
DSPs.
This patch add basic support.
Many of code in arch/c6x/include/asm come from c6x-linux project
(http://linux-c6x.org)
Signed-off-by: Dmitry
On Mon, Jun 25, 2012 at 10:02:37PM +0400, Dmitry Bondar wrote:
C6X (C6000) is family of fixed and floating-point DSPs manufactured by Texas
Instruments.
---
Changes for v2:
- reset_c.c rewritten with readl/writel.
- Tom Rini tr...@ti.com added to cc
Changes for v3:
-
On Mon, Jun 25, 2012 at 10:02:41PM +0400, Dmitry Bondar wrote:
Add support board c6745-som (http://inmys.ru/?_=/products/som_c6745) with
C6745 cpu.
Signed-off-by: Dmitry Bondar b...@inmys.ru
Cc: Tom Rini tr...@ti.com
[snip]
diff --git a/MAINTAINERS b/MAINTAINERS
index e55893b..710f3df
On Mon, Jun 25, 2012 at 10:02:39PM +0400, Dmitry Bondar wrote:
C6X has subfamilys: C62x C64x C66x C67x C645x C674x.
This patch add support of subfamily C674x (C6745/C6746/C6747 CPUs).
Signed-off-by: Dmitry Bondar b...@inmys.ru
Cc: Tom Rini tr...@ti.com
This one is fine, FYI.
--
Tom
On Mon, Jun 25, 2012 at 10:02:40PM +0400, Dmitry Bondar wrote:
C674x CPUs has same peripherals(uart,emac,nand contoller) like sitara
processors (am1705/am1707/omapl137/omapl138).
In u-boot this peripheral known as davinci SOC, and placed in
arch/arm/cpu/arm926ejs/davinci
This patch allow
This patch series fixes a long standing problem with the tegra20
u-boot build. Tegra20 contains an ARM7TDMI boot processor and a
Cortex A9 main processor. Prior to this patch series this was
accomplished by #ifdefing out any armv7 code from the early boot
sequence and creating a single binary
Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA.
The meaning of the config options is now:
CONFIG_TEGRA - Any tegra chip
CONFIG_TEGRA20 - A tegra20 family chip
CONFIG_TEGRA30 - A tegra30 family chip (not added yet)
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by:
Add target for tegra20 u-boot image. This is a concatenation of tegra
spl and normal u-boot binaries. For non-devicetree builds this is
named u-boot-t2.bin for devicetree builds is named
u-boot-dtb-t2.bin. This target is the default target for tegra20
and will get copied over u-boot.bin.
Don't use timer_init from tegra board.c. This comes out of arm720t
for the SPL build.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
board/nvidia/common/board.c |2 ++
1 file changed, 2 insertions(+)
diff --git
Change the mkdir commands for the object directories to be
unconditional. This fixes an issue when building for SPL where
SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE.
Signed-off-by: Allen Martin amar...@nvidia.com
---
board/avionic-design/medcom/Makefile |2 --
Add support for specifying a different CPU for main u-boot and SPL
u-boot builds. This is done by adding an optional SPL CPU after the
main CPU in boards.cfg as follows:
normal_cpu:spl_cpu
This this case CPU will be set to normal_cpu during the main u-boot
build and spl_cpu during the SPL
These flags were necessary when building tegra20 as a single binary
that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support
is split into a separate SPL, this is no longer necessary.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
Add SPL options to tegra20 config files and enable SPL build for
tegra20 boards in boards.cfg. Also remove redundant code from u-boot
that is not contained in SPL.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
arch/arm/cpu/armv7/start.S
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Stephen Warren
Add tegra20-common-post.h to be consistent with other tegra20 boards.
Signed-off-by: Allen Martin amar...@nvidia.com
Acked-by: Thierry Reding thierry.red...@avionic-design.de
Acked-by: Stephen Warren swar...@wwwdotorg.org
---
include/configs/tec.h |2 ++
1 file changed, 2 insertions(+)
diff
Move warmboot_save_sdram_params() to later in the boot sequence. This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.
Signed-off-by: Allen Martin
Add support for tegra20 arm7 boot processor. This processor is used
to power on the Cortex A9 and transfer control to it. In tegra this
processor is an ARM7TDMI not an ARM720T, but since we don't use cache
it was easier to just reuse the ARM720T code as the processors are
otherwise identical
On 06/25/2012 04:55 PM, Allen Martin wrote:
This patch series fixes a long standing problem with the tegra20
u-boot build. Tegra20 contains an ARM7TDMI boot processor and a
Cortex A9 main processor. Prior to this patch series this was
accomplished by #ifdefing out any armv7 code from the
Dear Joe Hershberger,
Hi Marek,
On Sun, Jun 24, 2012 at 7:17 PM, Marek Vasut ma...@denx.de wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option
Dear Joe Hershberger,
Hi Marex,
On Sun, Jun 24, 2012 at 7:17 PM, Marek Vasut ma...@denx.de wrote:
The asix driver did not align buffers, therefore it didn't work
with data cache enabled. Fix this.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Joe Hershberger
On Mon, Jun 25, 2012 at 04:04:28PM -0700, Stephen Warren wrote:
On 06/25/2012 04:55 PM, Allen Martin wrote:
This patch series fixes a long standing problem with the tegra20
u-boot build. Tegra20 contains an ARM7TDMI boot processor and a
Cortex A9 main processor. Prior to this patch series
Dear Scott Wood,
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This macro returns 1 if the argument (address) is aligned, returns
zero otherwise. This will be used to test user-supplied address to
various commands to prevent user from loading data to/from unaligned
address when using
Dear Scott Wood,
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option is to use bounce buffer,
Or get cache
Dear Tom Rini,
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote:
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM
Allen,
-Original Message-
From: Allen Martin [mailto:amar...@nvidia.com]
Sent: Monday, June 25, 2012 4:21 PM
To: Stephen Warren
Cc: Tom Warren; s...@chromium.org; thierry.red...@avionic-design.de; u-
b...@lists.denx.de
Subject: Re: [PATCH v5 00/13] split tegra20 arm7 code into
Dear Scott Wood,
On 06/25/2012 03:48 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/25/2012 01:08 PM, Scott Wood wrote:
On 06/25/2012 01:43 PM, Tom Rini wrote:
On Mon, Jun 25, 2012 at 11:58:10AM -0500, Scott Wood wrote:
On 06/24/2012 07:17 PM, Marek Vasut
Dear Stephen Warren,
On 06/25/2012 12:40 AM, Jim Lin wrote:
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like usb reset in u-boot command line).
This will be treated as an error and stops later device
Marek,
-Original Message-
From: Marek Vasut [mailto:marek.va...@gmail.com]
Sent: Monday, June 25, 2012 4:48 PM
To: Stephen Warren
Cc: Jim Lin; 'u-boot@lists.denx.de'; Tom Warren
Subject: Re: [PATCH v5 1/1] tegra: usb: Fix device enumeration problem of
USB1
Dear Stephen Warren,
On 06/25/2012 06:37 PM, Marek Vasut wrote:
Dear Scott Wood,
On 06/24/2012 07:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the
device uses DMA to deploy data. In that case, it might not
be possible to flush/invalidate data to RAM properly. The
other option
On 06/25/2012 06:42 PM, Marek Vasut wrote:
Dear Scott Wood,
On 06/25/2012 03:48 PM, Tom Rini wrote:
Right. What I'm trying to say is it's not a NAND problem it's an
unaligned addresses problem so the solution needs to be easily used
everywhere.
OK, so fix it in each driver that has this
Hello, Wolfgang Denk,
Thank you for responding.
(06/26/2012 06:34 AM), Wolfgang Denk wrote:
In message 4fe85b13.5080...@kmckk.co.jp you wrote:
I tried nfs command on KZM-A9-GT board and it fails every time with ERROR:
Cannot umount.
KZM-A9-GT board? This is an out of tree port, isn't it?
Hello,
(06/26/2012 12:10 AM), Stephen Warren wrote:
On 06/25/2012 06:40 AM, Tetsuyuki Kobayashi wrote:
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch
Dear Tom Warren,
Marek,
-Original Message-
From: Marek Vasut [mailto:marek.va...@gmail.com]
Sent: Monday, June 25, 2012 4:48 PM
To: Stephen Warren
Cc: Jim Lin; 'u-boot@lists.denx.de'; Tom Warren
Subject: Re: [PATCH v5 1/1] tegra: usb: Fix device enumeration problem of
Dear Scott Wood,
On 06/25/2012 06:42 PM, Marek Vasut wrote:
Dear Scott Wood,
On 06/25/2012 03:48 PM, Tom Rini wrote:
Right. What I'm trying to say is it's not a NAND problem it's an
unaligned addresses problem so the solution needs to be easily used
everywhere.
OK, so fix it
1 - 100 of 109 matches
Mail list logo
