-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Karl O. Pinc
Sent: 30 July 2012 08:00
To: Sabri Altunbas
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] building u-boot inside buildroot
On 07/29/2012 07:43:00 AM, Sabri
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Marek Vasut
Sent: 28 July 2012 01:20
To: u-boot@lists.denx.de
Cc: Marek Vasut; Joe Hershberger; u-boot...@lists.denx.de
Subject: [U-Boot] [PATCH] dm: net: Fixup the armada100
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Gerlando Falauto
Sent: 27 July 2012 20:28
To: u-boot@lists.denx.de
Cc: Holger Brunck
Subject: [U-Boot] [PATCH] km/common: remove printfs for i2c deblocking
code
From:
Dear Prafulla Wadaskar,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Marek Vasut
Sent: 28 July 2012 01:20
To: u-boot@lists.denx.de
Cc: Marek Vasut; Joe Hershberger; u-boot...@lists.denx.de
Subject: [U-Boot] [PATCH]
Dear Marek Vasut,
Write the TSCR register via 32bit write instead of 16bit one.
The register is 32bit wide and bit 16 is being set, triggering
gcc overflow error and making the code broken.
[...]
Dan, can you please pick these (I didn't CC you ... sigh :/ ) ?
Best regards,
Marek Vasut
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Karl O. Pinc
Sent: 27 July 2012 20:23
To: u-boot@lists.denx.de
Subject: Re: [U-Boot] Cosmetic doc typo fixes to the kwbimage feature
docs
On 07/26/2012 11:15:32 PM, Karl O.
This series adds NAND flash support to Tegra and enables it on Seaboard.
Included here is a proposed device tree binding with most of the properties
private to nvidia,. The binding includes information about the NAND
controller as well as the connected NAND device. The Seaboard has a
Hynix
Add a NAND controller along with a bindings file for review.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add new patch to align default
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for unit address (should be used for chip select)
-
Add selection of NAND flash pins to the funcmux.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra20-common/funcmux.c |7 +++
arch/arm/include/asm/arch-tegra20/funcmux.h |3 +++
2 files changed, 10 insertions(+), 0
This enables NAND support for the Seaboard.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4:
- Move to using CONFIG_SYS_NAND_SELF_INIT
- Rename CONFIG_TEGRA2_NAND to CONFIG_TEGRA_NAND
include/configs/seaboard.h |9 +
include/configs/tegra20-common.h |2 ++
2
From: Jim Lin ji...@nvidia.com
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin ji...@nvidia.com
Signed-off-by: Simon Glass s...@chromium.org
---
Hi, Andy
Could you give some reason why eMMC device will be so slowed down by
re-initialization?
I think eMMC device is initialized only once, except it invoke 'mmc_init' many
times.
The workaround mmc rescan works when replace the card.
But if one card is removed, then use mmcfinfo: there is
-Original Message-
From: Marek Vasut [mailto:marek.va...@gmail.com]
Sent: Friday, July 27, 2012 5:26 PM
To: u-boot@lists.denx.de
Cc: Jim Lin; Wolfgang Denk; Tom Warren
Subject: Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB
controllers at once
Wolfgang,
Is there any
Dear Marek Vasut,
In message 1343429832-24194-1-git-send-email-ma...@denx.de you wrote:
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break
strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Wolfgang Denk
Dear Marek Vasut,
In message 1343429832-24194-1-git-send-email-ma...@denx.de you wrote:
cpu.c: In function ‘check_CPU’:
cpu.c:256:2: warning: dereferencing type-punned pointer will break
strict-aliasing rules [-Wstrict-aliasing]
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Wolfgang Denk
Dear daniel.schwierz...@gmail.com,
In message 1343426851-2415-1-git-send-email-daniel.schwierz...@gmail.com you
wrote:
Dear Wolfgang,
please pull a small fix for v2012.07
The following changes since commit c627faf637f5fe091bdb6846a52b16983e97b262:
Prepare v2012.07-rc3 (2012-07-27
Hi Pavel,
The ahci.c is a ahci driver using pci interface, while dwc_asata is not.
u-boot don't have a pure ahci driver now, thus we have to reuse some
ahci parts from ahci.c in dwc_asata.c.
Thanks~~
Yours
Terry
-Original Message-
From:
Dear Wolgfang Denk,
On 07/27/2012 07:30 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message1343402200-32020-4-git-send-email-gerlando.fala...@keymile.com you
wrote:
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need
to keep them as separate .h config files.
Dear Lv Terry-R65388,
Hi Pavel,
The ahci.c is a ahci driver using pci interface, while dwc_asata is not.
u-boot don't have a pure ahci driver now, thus we have to reuse some
ahci
parts from ahci.c in dwc_asata.c.
Ok, I think we can unify that eventually.
Thanks~~
Hello Gerlando,
On 27.07.2012 16:58, Gerlando Falauto wrote:
From: Holger Brunckholger.bru...@keymile.com
This code will also be used before reallocation and during this time we
are not allowed to do these printings.
Signed-off-by: Holger Brunckholger.bru...@keymile.com
---
Hi:
If the voltage of battery is below 3.6v, the system still can be startup, and
do you think it is right? The function mx28_powerdown is meaningless.
At 2012-07-26 09:31:20,alex laub...@163.com wrote:
The poweroff function in kernel can work. The similar code can be found in
bootlet
2012/7/30 Marek Vasut ma...@denx.de:
Dear Marek Vasut,
Write the TSCR register via 32bit write instead of 16bit one.
The register is 32bit wide and bit 16 is being set, triggering
gcc overflow error and making the code broken.
[...]
Dan, can you please pick these (I didn't CC you ... sigh
Hello Gerlando,
On 27.07.2012 16:11, Gerlando Falauto wrote:
Hi all,
On 03/09/2011 02:21 PM, Detlev Zundel wrote:
Hi Heiko,
Maybe a way to go ... more comments?
Below a patch, which introduces a function, which checks for
protection bugfixes, and if no bugfix is found the old code is
hi Wolfgang,
On Fri Jul 27, 2012 at 03:16:15PM +0530, Sughosh Ganu wrote:
On Fri Jul 27, 2012 at 01:51:53PM +0530, Linu Cherian wrote:
Hawkboard was using the wrong nand_read_page version for SPL image.
As a side effect, the u-boot image loaded by the SPL from nand
was getting corrupted.
Hi Heiko,
On Monday 30 July 2012 13:07:07 Heiko Schocher wrote:
Have there been (since the original posting) other instances of flash
parts requiring quirks (like the original one introduced by Philippe De
Muyter for the Numonyx chip)?
I don´t know ...
Is there any ongoing activity
Hi,
On Tue, Jul 24, 2012 at 8:23 AM, Rajeshwari Shinde
rajeshwar...@samsung.com wrote:
This patch set enables I2C support for EXYNOS5.
This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5.
Multichannel support has been added to the s3c24x0 I2C driver.
s3c24x0_i2c struct has
Dear Jim Lin,
-Original Message-
From: Marek Vasut [mailto:marek.va...@gmail.com]
Sent: Friday, July 27, 2012 5:26 PM
To: u-boot@lists.denx.de
Cc: Jim Lin; Wolfgang Denk; Tom Warren
Subject: Re: [U-Boot] [PATCH 1/1] USB: EHCI: Initialize multiple USB
controllers at once
Dear Gerlando Falauto,
In message 50164f3a.6050...@keymile.com you wrote:
boards.cfg |4 +-
include/configs/km82xx.h| 149
+++
include/configs/mgcoge.h| 93 ---
Does anyone have any experience enabling the second or third mmc
channels in u-boot on an omap3 board?
I used the feature successfully a couple of years ago on Overo, but of
course there have been many changes in the mmc code since then.
Here's what I tried for overo with the current head of
On Fri, Jul 27, 2012 at 03:16:15PM +0530, Sughosh Ganu wrote:
On Fri Jul 27, 2012 at 01:51:53PM +0530, Linu Cherian wrote:
Hawkboard was using the wrong nand_read_page version for SPL image.
As a side effect, the u-boot image loaded by the SPL from nand
was getting corrupted.
Enable
On Mon, Jul 30, 2012 at 06:36:24AM -0700, Steve Sakoman wrote:
Does anyone have any experience enabling the second or third mmc
channels in u-boot on an omap3 board?
I used the feature successfully a couple of years ago on Overo, but of
course there have been many changes in the mmc code
On 07/30/2012 03:00 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message50164f3a.6050...@keymile.com you wrote:
boards.cfg |4 +-
include/configs/km82xx.h| 149
+++
include/configs/mgcoge.h| 93
On 07/30/2012 01:28:45 AM, Prafulla Wadaskar wrote:
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Karl O. Pinc
Sent: 30 July 2012 08:00
To: Sabri Altunbas
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] building
Hi Marek,
On Mon, Jul 30, 2012 at 1:35 AM, Marek Vasut ma...@denx.de wrote:
Dear Prafulla Wadaskar,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Marek Vasut
Sent: 28 July 2012 01:20
To: u-boot@lists.denx.de
Cc:
Dear Joe Hershberger,
Hi Marek,
On Mon, Jul 30, 2012 at 1:35 AM, Marek Vasut ma...@denx.de wrote:
Dear Prafulla Wadaskar,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Marek Vasut
Sent: 28 July 2012 01:20
Dear Gerlando Falauto,
In message 5016a093.6040...@keymile.com you wrote:
The way I understand it, such renaming information is built on the fly
while building the patch (like you're suggesting, it's a parameter to
git format-patch, not to the commit itself).
Yes, and I fail to understand
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers lwith...@guralp.com
Cc: Prabhakar Lad
On Sat, Jul 28, 2012 at 12:49:55PM +0530, Prabhakar Lad wrote:
Thanks for the patch. I have tested this patch, below are few comments.
[snip]
+int set_cpu_clk_info(void)
+{
+ gd-bd-bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 100;
+ /* DDR PHY uses an x2 input clock */
+
On Mon, Jul 30, 2012 at 04:30:15PM +, Laurence Withers wrote:
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by:
Hey all,
The following series of patches improves am33xx support, and cleans up
omap3/4/5 slightly. The slight cleanup to omap3/4/5 is that we can all
share a single function to see if we are executing in SDRAM or not. The
rest of the series cleans up the EMIF code for am33xx. While I had
- Add default commands
- Add HUSH parser
- Make environment, malloc areas larger
- Add ATAGS and OF_LIBFDT
- Add defaults to boot ramdisk and MMC, use uEnv.txt
Signed-off-by: Tom Rini tr...@ti.com
---
include/configs/am335x_evm.h | 69 --
1 file changed,
On all OMAP3+ platforms we know that SDRAM starts at 0x8000 and we
can use 0xD000 as the end.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c|4 ++--
arch/arm/cpu/armv7/omap3/sys_info.c | 12
The am33xx does not have a DMM, so don't define the base.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/include/asm/arch-am33xx/hardware.h |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h
b/arch/arm/include/asm/arch-am33xx/hardware.h
index
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 29 ++-
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 27 -
2 files changed, 15 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c
When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
We do not need to check for EMIF_GCLK and L3_GCLK being active. This
was a hold-over from bringup and no longer required.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock.c |5 -
1 file changed, 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c
With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/emif4.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const. This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.
Signed-off-by: Tom Rini tr...@ti.com
---
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()). For now, pass in
the value of DDR2.
Signed-off-by: Tom Rini tr...@ti.com
---
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/clock.c|5
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/emif4.c | 46 +--
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 32
From: Vaibhav Bedia vaibhav.be...@ti.com
EMIF parameters are calculated based on the AC timing
parameters from the SDRAM datasheet and the DDR frequency.
Current values for these paramters in AM335x U-Boot code,
though reliable, are not fully optimal. The most optimal
settings can be derived
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.
Signed-off-by: Tom Rini tr...@ti.com
---
- Remove the call to set ddrctrl-ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl-ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/emif4.c
Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 28 -
arch/arm/cpu/armv7/am33xx/emif4.c | 43
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c | 29 ++-
The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/ddr.c
On Mon, Jul 30, 2012 at 7:27 AM, Tom Rini tr...@ti.com wrote:
After adding a few printf's, it seems that the crash/hang is occurring
when calling env_relocate_spec in env_nand.c, which of course is
completely unrelated code!
I've spent some time scratching my head against a hang in the same
On Sat, Jul 28, 2012 at 01:19:31PM +0200, Javier Martinez Canillas wrote:
IGEP-based boards can have two different flash memories, a OneNAND or a
NAND device.
Since u-boot still lacks of a device model to be the able to look at
run-time which memory type is available on a the board, a built
Here is my log. It stops at the done, booting kernel.I tried
setting the console to ttyAM0 and no change. I don't think its booting
as I don't see the LCD flash and no penguin. The odd this is that I
built the latest kernel for iMX and this uboot will boot it. I also
included my
On Wed, Jul 25, 2012 at 02:22:15AM +0400, Ilya Yanok wrote:
These patches add CPSW switch driver and enable support for it
on TI AM335x based boards. This version is rebased on top of
u-boot-ti/next. Also now CPSW driver uses internal controller
memory for DMA descriptors so coherent
On Mon, Jul 30, 2012 at 2:06 PM, Bill bsou...@techsi.com wrote:
Here is my log. It stops at the done, booting kernel.I tried setting
the console to ttyAM0 and no change. I don't think its booting as I don't
see the LCD flash and no penguin. The odd this is that I built the latest
kernel
On Mon, Jul 30, 2012 at 04:34:39PM +, Laurence Withers wrote:
On Mon, Jul 30, 2012 at 04:30:15PM +, Laurence Withers wrote:
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have
Simon,
-Original Message-
From: Simon Glass [mailto:s...@chromium.org]
Sent: Sunday, July 29, 2012 11:53 PM
To: U-Boot Mailing List
Cc: Tom Warren; Stephen Warren; Scott Wood; Simon Glass
Subject: [PATCH v4 0/6] tegra: Add NAND flash support
This series adds NAND flash support to
On 07/30/2012 12:53 AM, Simon Glass wrote:
This series adds NAND flash support to Tegra and enables it on Seaboard.
Included here is a proposed device tree binding with most of the properties
private to nvidia,. The binding includes information about the NAND
controller as well as the
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
---
board/nvidia/dts/tegra20-harmony.dts | 10 ++
include/configs/harmony.h|9 -
2 files changed, 18 insertions(+), 1 deletions(-)
diff --git
From: Stephen Warren swar...@nvidia.com
This allows cache flush/invalidate operations to succeed on the buffers.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
common/env_nand.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/env_nand.c
Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Monday, July 30, 2012 10:34 AM
To: Simon Glass
Cc: U-Boot Mailing List; Tom Warren; Scott Wood
Subject: Re: [PATCH v4 0/6] tegra: Add NAND flash support
On 07/30/2012 12:53 AM, Simon Glass
On 07/30/2012 06:07 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message5016a093.6040...@keymile.com you wrote:
The way I understand it, such renaming information is built on the fly
while building the patch (like you're suggesting, it's a parameter to
git format-patch, not to the
Since mgcoge and mgcoge3ne are the only km82xx boards, there is no need
to keep them as separate .h config files.
Therefore, make mgcoge3ne.h and mgcoge.h converge into a single km82xx.h
file.
Signed-off-by: Gerlando Falauto gerlando.fala...@keymile.com
---
Changes from v1:
switched to git
Dear Linu Cherian,
In message 1343377313-30301-1-git-send-email-linucher...@gmail.com you wrote:
Hawkboard was using the wrong nand_read_page version for SPL image.
As a side effect, the u-boot image loaded by the SPL from nand
was getting corrupted.
Enable CONFIG_SYS_NAND_HW_ECC_OOBFIRST
On 07/27/2012 07:31 PM, Wolfgang Denk wrote:
Dear Gerlando Falauto,
In message1343402200-32020-5-git-send-email-gerlando.fala...@keymile.com you
wrote:
The only file including km82xx-common.h is km82xx.h.
So there is no need to have it as a separate file.
Signed-off-by: Gerlando
Progress! I switched all the references from ttyAMA0... to ttyAM0.
Also changed netargs too. Now it starts to boot linux but hangs right
after the line of:
mxs_cpu_init: cpufreq init finished.
In regards to your question, yes it was booting the mainline kernel.
Here is the latest
Dear Gerlando,
In message 5016d241.4030...@keymile.com you wrote:
Please also try with -M -C and see if this changes anything.
For this one patch I can't get git to detect renames.
Neither can I. Thanks for trying, though.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH,
Hello all,
U-Boot v2012.07 has been released and is available from the git
repository and the FTP server.
The Merge Window for the next release (v2012.10) is open until
Sat Aug 18, 2012, 23:59:59 CEST = 19 days remaining.
Release v2012.10 is scheduled in 77 days — on October 15, 2012.
A
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero,
While tuning ext2load, we found that usb_test_unit_ready was being called
every block read. We compared the usb block storage to the scsi block
storage cmd_scsi.c, and found that the scsi device was only calling its
scsi_setup_test_unit_ready() during scsi_can. It appears that
Albert,
Please pull u-boot-tegra/master into ARM master. Thanks!
The following changes since commit f8f09dd40423b7f9ea0f0b810a8f5da9cd580a17:
Benoît Thébaudeau (1):
ARM1136: Fix cache range checks
are available in the git repository at:
git://git.denx.de/u-boot-tegra master
Allen
On Mon, Jul 30, 2012 at 6:37 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
(nice to have a commit message though)
---
board/nvidia/dts/tegra20-harmony.dts |
On Mon, Jul 30, 2012 at 6:38 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
This allows cache flush/invalidate operations to succeed on the buffers.
Signed-off-by: Stephen Warren swar...@nvidia.com
Acked-by: Simon Glass s...@chromium.org
---
This patch restores the Linkstation's original behaviour when powering off.
Once the (soft) power switch is turned off, linux will reboot and the
bootloader turns off HDD and USB power. Then it loops as long as the switch
is in the off position, before continuing the boot process again.
From: Stephen Warren swar...@nvidia.com
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables
From: Stephen Warren swar...@nvidia.com
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables
From: Stephen Warren swar...@nvidia.com
eMMC devices may have hardware-level partitions: 2 boot partitions,
up to 4 general partitions, plus the user area. This change introduces
optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which
partition the environment should be stored in:
From: Stephen Warren swar...@nvidia.com
When I set up Tegra's config files to put the environment into eMMC, I
assumed that CONFIG_ENV_OFFSET was a linearized address relative to the
start of the eMMC device, and spanning HW partitions boot0, boot1,
general* and the user area in order. However,
On Mon, Jul 30, 2012 at 3:53 PM, Bill bsou...@techsi.com wrote:
Progress! I switched all the references from ttyAMA0... to ttyAM0. Also
changed netargs too. Now it starts to boot linux but hangs right after the
line of:
mxs_cpu_init: cpufreq init finished.
Please remove cpufreq
Hi Mike,
On Wed, Jul 25, 2012 at 1:49 PM, Mike Frysinger vap...@gentoo.org wrote:
On Tuesday 24 July 2012 16:11:15 Joe Hershberger wrote:
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -131,8 +131,17 @@ static void nc_send_packet(const char *buf, int len)
}
if
Dear Simon Glass,
In message CAPnjgZ2gJLhmZyXB1DW=83GBdf1QNv_=q+qfprawczx4yq7...@mail.gmail.com
you wrote:
- env_t env_new;
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t));
I think this should b
Should be ... ???
Best regards,
Wolfgang Denk
--
DENX Software
Hi Wolfgang,
On Mon, Jul 30, 2012 at 10:10 PM, Wolfgang Denk w...@denx.de wrote:
Dear Simon Glass,
In message
CAPnjgZ2gJLhmZyXB1DW=83GBdf1QNv_=q+qfprawczx4yq7...@mail.gmail.com you
wrote:
- env_t env_new;
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t));
I
I submitted this a while ago[0], it would be nice to see it included
if possible. It generalises the DNS325 support so that it can be used
for both the DNS320 and DNS325.
Luka Perkov stated I have no more questions regarding this patch, not
sure if this counts as an ACK. The patch here is ~same,
Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more
information on this NAS, see:-
http://jamie.lentin.co.uk/devices/dlink-dns320
http://dns323.kood.org/dns-320
http://sharecenter.dlink.com/products/DNS-320
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Cc:
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud.net
---
On 07/30/2012 01:53 AM, Simon Glass wrote:
From: Jim Lin ji...@nvidia.com
A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin ji...@nvidia.com
Dear Benoît Thébaudeau,
[...]
Can you explain where this gain would come from? In both cases, the
data in USB
transfers would be organized in the same way, and it would be
accessed in memory
also in the same way (regarding bursts). The only difference would
be the fetch
time
On 07/30/2012 01:53 AM, Simon Glass wrote:
Add a flash node to handle the NAND, including memory timings and
page / block size information.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update NAND binding to add nvidia, prefix
Changes in v3:
- Add reg property for
Dear Jim Shimer,
While tuning ext2load, we found that usb_test_unit_ready was being called
every block read. We compared the usb block storage to the scsi block
storage cmd_scsi.c, and found that the scsi device was only calling its
scsi_setup_test_unit_ready() during scsi_can. It appears
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