Hi Haijun,
On Nov 5, 2013, at 8:23 AM, Haijun Zhang wrote:
Erass sequence:
1. check if erase command is support by card. If not return.
2. Check the erase range to see if it was aligned. The min erase size
should be one erase group. SD card it was one block(512), mmc card
it should be one
Hi Haijun,
On Nov 5, 2013, at 8:23 AM, Haijun Zhang wrote:
If the block rang was not algined, We tried to algined the range,
then erase the block. So the block range erased should be less or
equal to the block range send. If error occured during erase procedure
part of them will be erased.
Hi Haijun,
On Nov 5, 2013, at 8:23 AM, Haijun Zhang wrote:
Once mmc initialization was faild has_init should be set to 0,
prepard for the next initialization to recover from error.
Once mmcinfo command failed error should point out instead of print
incorrect mmc device information.
Hi Haijun,
On Nov 5, 2013, at 8:23 AM, Haijun Zhang wrote:
The max timeout value esdhc host can accept was about 2.69 sec
At 50 Mhz SD_CLK period, the max busy timeout
value = 2^27 * SD_CLK period ~= 2.69 sec.
In case erase command CMD38 timeout is caculate by
^ calculated?
mult * 300ms
Hi Haijun,
On Dec 2, 2013, at 7:25 AM, Haijun Zhang wrote:
Card detection pin is ineffective on T4240QDS.
This workaround force sdhc driver scan and initialize the card regardless
of whether the card is inserted. if no card is in the slot, the error message
card is not inserted will be
Hi Haijun,
On Dec 2, 2013, at 7:25 AM, Haijun Zhang wrote:
On BSC9131 and BSC9132: For High Capacity SD Cards ( 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need
Hi Haijun,
On Dec 2, 2013, at 7:25 AM, Haijun Zhang wrote:
The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc
before enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c
Hi Alexey,
On Nov 27, 2013, at 3:00 PM, Alexey Brodkin wrote:
If platform provides host-fifoth_val it will be used for
initialization of DWMCI_FIFOTH register. Otherwise default value will be
used.
This implementation allows:
* escape unclear and recursive calculations that are currently
Hi all
On Sun, Dec 8, 2013 at 12:46 PM, Pantelis Antoniou
pantelis.anton...@gmail.com wrote:
Hi Haijun,
On Dec 2, 2013, at 7:25 AM, Haijun Zhang wrote:
Card detection pin is ineffective on T4240QDS.
This workaround force sdhc driver scan and initialize the card regardless
of whether the
Hi Lad,
On Dec 3, 2013, at 8:47 AM, Lad, Prabhakar wrote:
From: Lad, Prabhakar prabhakar.cse...@gmail.com
The spl_mmc_load() was removed while converting to
CONFIG_SPL_FRAMEWORK usage the definition was removed
but the declaration was missed. This patch removes this
declaration.
Hi Priyanka,
On Nov 28, 2013, at 6:42 AM, Priyanka Jain wrote:
Existing eSDHC SPL framework assumes booting from sd-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
Hi Kuo-Jung,
On Nov 25, 2013, at 4:51 AM, Kuo-Jung Su wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTSDC021 is a controller which is compliant with
SDHCI v3.0, SDIO v2.0 and MMC v4.3.
However this driver is only verified with SD memory cards.
Signed-off-by: Kuo-Jung Su
ABB code uses LDELAY but does not include the header that provides its
definition.
Include the header.
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
arch/arm/cpu/armv7/omap-common/abb.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Disclaimer: disregard the 1/4. This is supposed to be a standalone
patch, I just forgot to
remove the patch counter before sending.
On 12/08/2013 02:29 PM, Nikita Kiryanov wrote:
ABB code uses LDELAY but does not include the header that provides its
definition.
Include the header.
Cc: Tom
On 12/7/2013 6:51 AM, Scott Wood wrote:
On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 000..7bc8ce1
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,73 @@
+/* Copyright
-Original Message-
From: York Sun [mailto:york...@freescale.com]
Sent: Saturday, December 07, 2013 12:39 AM
To: Liu Shengzhou-B36685; u-boot@lists.denx.de
Subject: Re: [PATCH] t2080qds/ddr: update ddr parameters
On 12/06/2013 12:53 AM, Shengzhou Liu wrote:
- optimize ddr
Hello Piotr,
Am 20.11.2013 10:43, schrieb Piotr Wilczek:
This patch adapts the s3c24x0 driver to the new i2c framework.
Config file is modified for all the boards that use the driver.
Signed-off-by: Piotr Wilczekp.wilc...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
CC:
Hello Piotr,
Am 20.11.2013 10:43, schrieb Piotr Wilczek:
Fix clock value initialisation for Exynos other than Exynos5 for hsi2c.
Signed-off-by: Piotr Wilczekp.wilc...@samsung.com
Signed-off-by: Kyungmin Parkkyungmin.p...@samsung.com
Cc: Minkyu Kangmk7.k...@samsung.com
Cc: Heiko
Hello Kuo-jung,
Am 02.12.2013 09:02, schrieb Kuo-Jung Su:
From: Kuo-Jung Sudant...@faraday-tech.com
Coding style cleanup
Signed-off-by: Kuo-Jung Sudant...@faraday-tech.com
Cc: Heiko Schocherh...@denx.de
---
Changes for v2 v3:
- Nothing updates
drivers/i2c/fti2c010.c | 31
Hello Kuo-jung,
Am 02.12.2013 09:02, schrieb Kuo-Jung Su:
From: Kuo-Jung Sudant...@faraday-tech.com
Replace the legacy i2c model with the new one.
Signed-off-by: Kuo-Jung Sudant...@faraday-tech.com
Cc: Heiko Schocherh...@denx.de
---
Changes for v2 v3:
- Nothing updates
Hello Kuo-jung,
Am 02.12.2013 09:02, schrieb Kuo-Jung Su:
From: Kuo-Jung Sudant...@faraday-tech.com
For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B),
the r/w address should be serial out in MSB order.
Signed-off-by: Kuo-Jung Sudant...@faraday-tech.com
Cc: Heiko
Hello Kuo-jung,
Am 02.12.2013 09:02, schrieb Kuo-Jung Su:
From: Kuo-Jung Sudant...@faraday-tech.com
The local pointer of address (i.e., addr) only gets
referenced under SPI mode, and it won't be appropriate
to pass only 1-byte addr[1] to i2c_read/i2c_write while
CONFIG_SYS_I2C_EEPROM_ADDR_LEN
Hello Nikita,
Am 28.11.2013 17:04, schrieb Nikita Kiryanov:
Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
based devices. This seems to be related to the following advisory which
apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
OMAP4430 TRM:
Hello Naveen,
Am 06.12.2013 07:42, schrieb Naveen Krishna Ch:
From: Naveen Krishna Chch.nav...@samsung.com
This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels
on Exynos5420 and Exynos5250 and also adds support for init function
for hsi2c channels
Signed-off-by: Naveen Krishna
Hello Tom,
please pull from u-boot-i2c.git.
The following changes since commit f44483b57c49282299da0e5c10073b909cdad979:
Merge branch 'serial' of git://git.denx.de/u-boot-microblaze (2013-12-02
08:48:02 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-i2c.git
Hi All,
I have tried booting SMDK5250 on the latest U-boot-Samsung branch, It
builds fine but does not boot.
Observation:
If revert the following patch it works fine:
commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7
Author: Albert ARIBAUD albert.u.b...@aribaud.net
Date: Thu Nov 7 14:21:46 2013
26 matches
Mail list logo
