Hi Albert,
Tested on SMDK5250 and working fine.
Tested by: Rajeshwari S Shinde rajeshwar...@samsung.com
Regards,
Rajeshwari.
On Fri, Dec 13, 2013 at 1:14 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Some targets will build fine but not boot if sections .hash and
.got.plt are not
Hello Albert.
$(obj)$(SPL_BIN).bin:$(obj)$(SPL_BIN)
- $(OBJCOPY) $(OBJCFLAGS) -O binary $ $@
+ $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O srec $
$(obj)$(SPL_BIN).srec
+ $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $ $@
The new file .srec is not mentioned in the
Hello,
I just discovered that uboot has a sandbox build - output binary is
a standard linux application. This prompted me to try stepping through
the code with gdb and I'm running into an annoyance.
The sandbox binary is splitting into 4 threads (I'm guessing one for
each of my cores, am running
(adding Minkyu as the Samsung custodian)
On Mon, 9 Dec 2013 18:09:18 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
mkexynos reads its input file which might be smaller than
( typo: s/mkexynos/mkexynosspl/ -- wil fix when applying if thee is
no other change to be made )
its read
As there were parallel set of patches running between u-boot and kernel.
hence, some patch-sets caused regression for OMAP3x platforms when booting
using u-boot specifically for ecc-schemes (like BCH4_SW).
Hence this patch series fixes those regressions, and tests complete
NAND boot sequence for
This patch mainly fixes ecc-layout for following ecc-schemes, to bring them
in sync with u-boot omap_gpmc NAND driver:
- BCH4_SW: OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
This ecc-scheme is mainly used on AM35xx and other legacy platforms.
- BCH8_SW: OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
This patch updates starting offset for free bytes in OOB which can be used by
file-systems to store their metadata (like clean-marker in case of JFFS2).
Signed-off-by: Pekon Gupta pe...@ti.com
---
drivers/mtd/nand/omap2.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
Hi Masahiro,
On Fri, 13 Dec 2013 17:15:51 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
Hello Albert.
$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN)
- $(OBJCOPY) $(OBJCFLAGS) -O binary $ $@
+ $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O srec $
$(obj)$(SPL_BIN).srec
+
Dear Ron Eggler,
On 12/12/2013 10:22 PM, Ron Eggler wrote:
Hi,
I got a SAMA5D31 evaluation kit here, it came with some default application.
I started
reading through the getting started guide and immediately tried to load my
own image -
MISTAKE!
I started playing around with u-boot
Hi Chao Fu,
Please check the checkpatch.pl issues.
On Friday 13 December 2013 11:20 AM, Chao Fu wrote:
From: Chao Fu b44...@freescale.com
Freescale DSPI module is used on both the ColdFire platform and the ARM
platform. The original DSPI driver is written for ColdFire platform only,
this
On Friday 13 December 2013 11:20 AM, Chao Fu wrote:
From: Chao Fu b44...@freescale.com
This patch enable the DSPI moudle on VF610 platform with following udpate:
Add get_dspi_clk() function and enable DPSI clock gate.
Add DSPI iomux definition and set the iomux for DSPI.
Signed-off-by: Chao Fu
Dear Sergey Alyoshin,
On Thursday, December 12, 2013 5:46:21 PM, Sergey Alyoshin wrote:
Enable fuse supply gate before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin alyoshi...@gmail.com
Tested-by: Sergey Alyoshin alyoshi...@gmail.com
You convinced me. ;)
---
On Fri, Aug 23, 2013 at 12:26:49PM -0400, Tom Rini wrote:
Test on Beaglebone white over cpsw, usb ether and SD card (read and
write), performance increased, crc32 of data matches.
Signed-off-by: Tom Rini tr...@ti.com
Applied to u-boot-ti/master, thanks!
--
Tom
signature.asc
Description:
Hello,
The following changes since commit a5a42eec8ed64cbc72d2e59199819e48f904e38f:
ARM: fix the standalone programs (2013-12-12 11:27:59 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-ti.git master
for you to fetch changes up to
On Wed, Dec 04, 2013 at 09:14:20AM -0500, Tom Rini wrote:
To make managing the environment easier, add DFUARGS to
CONFIG_EXTRA_ENV_SETTINGS. Then we set DFUARGS down in the DFU part of
the file, and include (or not) the NAND part, based on if NAND is set.
Signed-off-by: Tom Rini
On Wed, Dec 04, 2013 at 01:54:18PM +0100, Stefan Roese wrote:
Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
board. Currently only the 256MiB SDRAM board versions are supported.
Tested by booting via MMC and NAND.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini
On Wed, Dec 04, 2013 at 12:22:55PM +0530, Lokesh Vutla wrote:
With the current scenario SPL size is being overlapped with the public
stack and not allowing any OMAP4 device to boot. So the suggestion came
up was to move the TEXT_BASE down to non-HS limit. Fixing the same and
also moving the
On Thu, Dec 05, 2013 at 07:19:17AM -0600, Dan Murphy wrote:
Fix the offset for the USB clock registers
Signed-off-by: Dan Murphy dmur...@ti.com
Applied to u-boot-ti/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
U-Boot
On Thu, Dec 12, 2013 at 03:34:56PM +0530, Lokesh Vutla wrote:
Commit armv7: hw_data: change clock divider setting
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.
Reported-by: Rajendran, Vinothkumar
On Tue, Dec 10, 2013 at 11:56:53AM +0100, Heiko Schocher wrote:
commit 16297cfb2a20c9d89834cd9e31edac5184a777a1
Author: Mateusz Zalega m.zal...@samsung.com
Date: Fri Oct 4 19:22:26 2013 +0200
usb: new board-specific USB init interface
introduced a new parameter to the dfu command.
On Wed, Dec 11, 2013 at 06:04:40PM +0200, Nikita Kiryanov wrote:
This patch makes the following updates to the cm_t35 config file:
- Replace ttyS in default environment kernel bootargs with the new ttyO
notation.
- Remove omapfb.debug=y from default environment kernel bootargs.
- Define a
On Friday, December 13, 2013 1:42:10 PM, Benoît Thébaudeau wrote:
On Thursday, December 12, 2013 5:46:21 PM, Sergey Alyoshin wrote:
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+static inline void enable_fuse_prog(unsigned char enable)
+{
+ enable_efuse_prog_gate(enable);
+}
On Wed, Dec 11, 2013 at 03:41:11PM +0100, Yegor Yefremov wrote:
From: Yegor Yefremov yegorsli...@googlemail.com
Pin 30 is connected to PHY's RESET# signal, so it must be
put to high. Otherwise PHY won't be found via MDIO interface.
Signed-off-by: Yegor Yefremov yegorsli...@googlemail.com
On Sun, Dec 08, 2013 at 02:29:19PM +0200, Nikita Kiryanov wrote:
ABB code uses LDELAY but does not include the header that provides its
definition.
Include the header.
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Acked-by: Nishanth Menon n...@ti.com
On Thu, Dec 12, 2013 at 03:36:21PM +0530, Lokesh Vutla wrote:
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.
Reported-by:
On Wed, Dec 04, 2013 at 09:27:34AM +0100, Stefan Roese wrote:
Add SPL support for the Technexion TAO3530 SOM to replace
x-loader. Tested with the Thunder baseboard. Currently this is
only tested with the TAO3530 SOM revision (Ax/Bx).
Tested by booting via MMC and NAND.
Signed-off-by:
On Wed, Dec 04, 2013 at 09:27:37AM +0100, Stefan Roese wrote:
The Head acoustics (HA) baseboard used the Technexion TAO3530 SOM
and has only some minor differences to the Technexion Thunder baseboard.
This patch adds support for this HA baseboard / TAO3530 as the omap3_ha
build target.
On Wed, Dec 04, 2013 at 09:27:36AM +0100, Stefan Roese wrote:
Signed-off-by: Stefan Roese s...@denx.de
Cc: Tapani Utriainen tap...@technexion.com
Cc: Thorsten Eisbein thorsten.eisb...@head-acoustics.de
Cc: Tom Rini tr...@ti.com
---
v2:
- Use puts instead of printf when possible
On Wed, Dec 04, 2013 at 09:27:35AM +0100, Stefan Roese wrote:
The memory size is autodetected and is passed to the Linux kernel
either via ATAGs or device-tree (dtb). So there is no need to
pass it via the bootargs.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Tapani Utriainen
On Wed, Dec 04, 2013 at 09:27:33AM +0100, Stefan Roese wrote:
From: Tapani Utriainen tap...@technexion.com
Add support for TechNexion TAO3530 SoM
This patch has been posted quite a long time ago. I ported it to
the latest mainline U-Boot version. With some additional cleanup
and
On Fri, Dec 13, 2013 at 10:35:11AM +0400, Alexey Brodkin wrote:
Driver for non-standard on-chip UART, instantiated in the ARC (Synopsys)
FPGA Boards such as ARCAngel4/ML50x
Signed-off-by: Alexey Brodkin abrod...@synopsys.com
Cc: Mischa Jonker mjon...@synopsys.com
Cc: Francois Bedard
On Fri, Dec 13, 2013 at 07:01:07AM +, Alexey Brodkin wrote:
Hi Tom,
On Mon, 2013-12-09 at 16:57 +0400, Alexey Brodkin wrote:
Current implementation works fine if usec * get_tbclk() fits in 32
bits. Otherwise result will be cut down to 32-bit.
Fix is obvious - first extend data
On Mon, Oct 28, 2013 at 2:56 PM, Luka Perkov l...@openwrt.org wrote:
All other hex values in sf_probe.c are in lower case so we should
fix this one too.
Signed-off-by: Luka Perkov l...@openwrt.org
---
drivers/mtd/spi/sf_probe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Fri, 2013-12-13 at 08:07 -0500, Tom Rini wrote:
Looks fine, please list this as a pre-requisite patch when posting the
rest of the board, thanks!
Hi Tom,
is my understanding correct that this patch will be accepted as it is
but later when I do submission of corresponding board I just
Hi Tom,
On Fri, 13 Dec 2013 07:45:39 -0500, Tom Rini tr...@ti.com wrote:
Hello,
The following changes since commit a5a42eec8ed64cbc72d2e59199819e48f904e38f:
ARM: fix the standalone programs (2013-12-12 11:27:59 +0100)
are available in the git repository at:
On Fri, Dec 13, 2013 at 01:19:12PM +, Alexey Brodkin wrote:
On Fri, 2013-12-13 at 08:07 -0500, Tom Rini wrote:
Looks fine, please list this as a pre-requisite patch when posting the
rest of the board, thanks!
Hi Tom,
is my understanding correct that this patch will be accepted
On Fri, Dec 13, 2013 at 02:29:23PM +0100, Albert ARIBAUD wrote:
Hi Tom,
On Fri, 13 Dec 2013 07:45:39 -0500, Tom Rini tr...@ti.com wrote:
Hello,
The following changes since commit a5a42eec8ed64cbc72d2e59199819e48f904e38f:
ARM: fix the standalone programs (2013-12-12 11:27:59
On Fri, Dec 13, 2013 at 08:07:51AM -0500, Tom Rini wrote:
On Fri, Dec 13, 2013 at 07:01:07AM +, Alexey Brodkin wrote:
Hi Tom,
On Mon, 2013-12-09 at 16:57 +0400, Alexey Brodkin wrote:
Current implementation works fine if usec * get_tbclk() fits in 32
bits. Otherwise result will
On Fri, 2013-12-13 at 09:09 -0500, Tom Rini wrote:
Please note that I'm taking http://patchwork.ozlabs.org/patch/297361/ as
the solution for this problem, thanks!
As long as it resolves overflow issue (and from that patch I'd say it
should) I'm totally fine with it.
Thanks.
P.S. funny
Hi Tom,
On Fri, 13 Dec 2013 07:45:39 -0500, Tom Rini tr...@ti.com wrote:
Hello,
The following changes since commit a5a42eec8ed64cbc72d2e59199819e48f904e38f:
ARM: fix the standalone programs (2013-12-12 11:27:59 +0100)
are available in the git repository at:
On Wed, 2013-12-11 at 00:16 -0600, Liu Po-B43644 wrote:
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE,
CONFIG_SYS_NAND_BASE_PHYS,
-MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
This corrects i2c core to interpret the value returned by
i2c_set_bus_speed as a success indicator rather than the
actual speed that was set. When i2c_set_bus_speed returns
a failure code, the speed is unknown so the adapter speed
is set to zero.
Signed-off-by: Darwin Rambo dra...@broadcom.com
On Tue, 2013-12-10 at 20:46 -0600, Liu Po-B43644 wrote:
Sorry for late reply since the email system crash.
-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
Sent: Saturday, December 07, 2013 9:22 AM
To: Liu Po-B43644
Cc: u-boot@lists.denx.de; Sun
Hi Masahiro,
On 12 December 2013 16:39, Simon Glass s...@chromium.org wrote:
Hi Masahiro,
On 11 December 2013 19:53, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hello Simon
You need to apply above patches beforehand to use this series.
They are simple patches, so I hope they will
Hi,
On 1 December 2013 23:10, Heiko Schocher h...@denx.de wrote:
Hello Andreas,
Am 27.11.2013 13:10, schrieb andr...@oetken.name:
As proposed by Heiko I made some small changes and verified the patch with
the
checkpatch-script.
You can also use patman to generate, check and send your
On Fri, 2013-12-13 at 21:09 -0600, Liu Po-B43644 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, December 14, 2013 4:26 AM
To: Liu Po-B43644
Cc: u-boot@lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579
Subject: Re: [PATCH v2 2/2]
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/fdt_support.c | 66 ++
1 file changed, 34 insertions(+), 32 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/cmd_pxe.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
index db6b156..c27ec35 100644
--- a/common/cmd_pxe.c
+++ b/common/cmd_pxe.c
From: Scott Wood scottw...@freescale.com
While performing relocations on u-boot.bin should be good enough for
booting on real hardware, some simulators insist on booting an ELF file
(and yet don't perform ELF relocations), so convert the relocated
binary back into an ELF file. This can go away
My original intention was to have a 100ms timeout. However, the timer
operations used return values in ms not us, so we ended up with a 100s
timeout instead. Fixing this exposes that some operations need longer
to operate than 100ms, so bump the timeout up to a whole second.
Reported-by: Andre
From: David Feng feng...@phytium.com.cn
Changes for v16:
- make the patches work with latest recently u-boot.
add rela relocation type to OBJCFLAGS definition
at arm/config.mk.
Changes for v15:
- modify boot process, u-boot will run at the highest
exception level until it prepare
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/board_f.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index f0664bc..d918e4b 100644
--- a/common/board_f.c
+++
From: Scott Wood scottw...@freescale.com
ARM64 uses the newer RELA-style relocations rather than the older REL.
RELA relocations have an addend in the relocation struct, rather than
expecting the loader to read a value from the location to be updated.
While this is beneficial for ordinary
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
MAKEALL | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/MAKEALL b/MAKEALL
index a74f0fc..562071a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -381,6 +381,12 @@
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
board/armltd/vexpress64/Makefile |8 ++
board/armltd/vexpress64/vexpress64.c | 56 ++
boards.cfg |
From: Scott Wood scottw...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: David Feng feng...@phytium.com.cn
---
Makefile | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index 861f31e..e331d35 100644
---
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
include/linux/linkage.h |4
1 file changed, 4 insertions(+)
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 39c712e..7435fcd 100644
--- a/include/linux/linkage.h
+++
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and
Using the TPL method for nand boot by sram was already
supported. Here add some code for mpc85xx ifc nand boot.
- For ifc, elbc, esdhc, espi, all need the SPL without
section .resetvec.
- Use a clear function name for nand spl boot.
- Add CONFIG_SPL_IFC_SUPPORT to
On Sat, Dec 14, 2013 at 2:27 AM, Darwin Rambo dra...@broadcom.com wrote:
This corrects i2c core to interpret the value returned by
i2c_set_bus_speed as a success indicator rather than the
actual speed that was set. When i2c_set_bus_speed returns
a failure code, the speed is unknown so the
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Eric Nelson
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function.
Fix the register access in EHCI HCD. We need to use address of the register
as an ehci_writel() argument.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
---
drivers/usb/host/ehci-hcd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Make indirect vectors addresses global, so they can be replaced by
various code that needs to do so. For example the MX6 PCI express
driver needs to temporarily replace data abort handler when reading
the config space.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Albert Aribaud
Enable PCI express on MX6 Sabrelite.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Eric Nelson eric.nel...@boundarydevices.com
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Stefano Babic sba...@denx.de
---
include/configs/nitrogen6x.h | 11
The detection function of the EHCI PCI controller was really cryptic,
add a beefy comment and clean the portion of the code up a bit. No
change in the logic of the code.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
---
drivers/usb/host/ehci-pci.c | 28
In case the controller is not initialized, we shall not de-initialize it.
As the control structure will not be filled, we will produce a null ptr
dereference if the controller is not inited.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
---
Dear Albert,
On 13/12/13 18:00, Albert ARIBAUD wrote:
(adding Minkyu as the Samsung custodian)
On Mon, 9 Dec 2013 18:09:18 +0100, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
mkexynos reads its input file which might be smaller than
( typo: s/mkexynos/mkexynosspl/ -- wil fix when
On Sat, Dec 14, 2013 at 9:17 AM, feng...@phytium.com.cn wrote:
From: Scott Wood scottw...@freescale.com
ARM64 uses the newer RELA-style relocations rather than the older REL.
RELA relocations have an addend in the relocation struct, rather than
expecting the loader to read a value from the
Hi all,
I am working on trying to shrink down a bootloader for one of our chips
where the bootloader must fit in around 448K of memory and things are
fairly tight. I found that the oob data structures for 8, 16, 64 and 128
bytes were taking up a fair amount of space. I had to increase the
On Sat, Dec 14, 2013 at 9:17 AM, feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
Signed-off-by: David Feng feng...@phytium.com.cn
---
common/cmd_pxe.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
--
*ron eggler | semios | senior software engineer*
320 - 887 Great Northern Way | Vancouver, BC | V5T 4T5
T | 604 229 2044 ext 105[1]
C | 778 230 9442[2]
E | regg...@semios.com[3]
smart farming[4]
twitter[5] linkedin[6]
Dear Ron Eggler,
On 12/12/2013 10:22 PM, Ron Eggler wrote:
Hi,
On Sat, Dec 14, 2013 at 10:25 AM, Marek Vasut ma...@denx.de wrote:
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function.
On Sat, Dec 14, 2013 at 10:25 AM, Marek Vasut ma...@denx.de wrote:
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.
Signed-off-by: Marek Vasut ma...@denx.de
On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote:
[...]
+/*
+ * Replace the original ARM DABT handler with a simple jump-back one.
+ *
+ * The problem here is that if we have a PCIe bridge attached to this
PCIe + * controller, but no PCIe device is connected to the
I always used tftp in my test, so the first dm9000 on LP-8x4x was
always properly initialized. However, if the boot doesn't include
network related commands, linux will not find a valid MAC and will
complain.
No longer.
Signed-off-by: Sergei Ianovich ynv...@gmail.com
---
Initial configuration has worng address of the second chip.
There is an alias for the 1st chip at 0x0200 in earlier
verions of LP-8x4x, so the boot normally.
However, new LP-8x4xs have a bigger 1st flash chip, and hang on
boot without this patch.
Signed-off-by: Sergei Ianovich
The device has only 256 kiB for U-Boot binary.
Binary size exceeds 256 kiB after activating CONFIG_OF_LIBFDT, so
we disable USB support which was not working anyway.
Disabled USD frees more space than libfdt requires, so activate
long command line help.
Signed-off-by: Sergei Ianovich
Linux kernel maintainers require new machnines to support device
tree boot. The config for LP-8x4x needs updating.
In addition, there are a few fixes to board's configuration.
Sergei Ianovich (4):
ARM: pxa: prevent PXA270 occasional reboot freezes
arm: pxa: always init ethaddr for LP-8x4x
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.
If SDRAM is not reset, it causes memory bus congestion and
the device hangs.
We put SDRAM in selfresh mode before watchdog reset, removing
potential
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