Dear Gerhard,
2014/1/9 Gerhard Sittig g...@denx.de
According to `git log` and `git show b77026225a31` (ARM : Add
support for MINI2440 (s3c2440). as of 2012-05-02) only boot from
NOR is supported. Later commit 79a6fcf2573e (2013-06-15) fixed
GPIO register access, and commit 2108f4c4a302
Dear colleagues,
Thank you very much for all the replies.
Finally, I have found the cause of the problem and there is some joy this
weekend.
The problem was the SION bit. The clock has to loop back. I think it is a
u-boot bug in the pinmux table for the imx6dl. The mode ALT2
(ENET_REF_CLK/)
The ENET_REF_CLK has to loopback: the patch was produced from u-boot 2013-10
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 7851eb1..9c18847 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++
For KVM we have a special PV machine type called ppce500. This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.
It also provides more PCI slots and is supposed to be enumerated by
device tree only.
This patch adds support for the current generation
In QEMU we implement a PV machine type called ppce500. That board is able
to run any e500+ FSL cores (e500v2, e500mc, e5500, e6500).
It is heavily inspired by the MPC8544DS SoC and board combination, but
implements only the bare minimum to make Linux happy enough to drive a
virtual machine.
This
We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.
To know where we have to start executing this ELF binary we have to
tell the linker where our entry point is.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/cpu/mpc85xx/u-boot.lds |
With the qemu-ppce500 machine type we can run the same board with
either an e500v2 or an e500mc core plugged in.
This means that the IVOR setup can't be based on compile time decisions,
so instead we have to do a runtime check which CPU generation we're
running on.
Signed-off-by: Alexander Graf
On Sun, Jan 19, 2014 at 12:34 PM, Andy Ng andreas2...@gmail.com wrote:
The ENET_REF_CLK has to loopback: the patch was produced from u-boot 2013-10
Please:
- Add Signed-off-by
- Rebase it to imx/master as this does not apply in current source code.
--
Otavio Salvador
Andy,
On Sun, Jan 19, 2014 at 2:58 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
On Sun, Jan 19, 2014 at 12:34 PM, Andy Ng andreas2...@gmail.com wrote:
The ENET_REF_CLK has to loopback: the patch was produced from u-boot 2013-10
Please:
- Add Signed-off-by
- Rebase it to imx/master
Hi, Jagan,
Could you help to review the series? Thanks.
Best Regards,
Alison Wang
On Monday 13 January 2014 02:24 PM, Huan Wang wrote:
Hi, Jagan,
I tested my driver based on your sf quad changes, and it is ok. For the
sf quad functions, I didn' t test, because my
Hi Otavio/Andy,
On Sun, Jan 19, 2014 at 3:07 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01,0x05E0,
0x0210, 5, 0x, 0, 0)
On Sun, Jan 19, 2014 at 3:48 PM, Fabio Estevam feste...@gmail.com wrote:
Hi Otavio/Andy,
On Sun, Jan 19, 2014 at 3:07 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -695,7 +695,7 @@
On Sun, Jan 19, 2014 at 3:55 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
Personally I think when using the ALT 2 people are expecting it works
out of box so I think this should be in the PAD declaration.
This pin works out of the box in hummingboard, for example.
IOMUX_CONFIG_SION is
On Sun, Jan 19, 2014 at 4:03 PM, Fabio Estevam feste...@gmail.com wrote:
On Sun, Jan 19, 2014 at 3:55 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
Personally I think when using the ALT 2 people are expecting it works
out of box so I think this should be in the PAD declaration.
This
The summary already has other verification. This one is not needed.
The check caused summaries to be ignored if they were not on the
numbered block. This caused problems when a summary was embedded in an
image and the image is written to a flash with bad blocks.
Signed-off-by: Charles Manning
Hi,
I am interested in changing the default serial console from UART 0 to
UART 1, which are the files need to be changed in u-boot code and what
changes are done , so that with new u-boot , the console should be on UART1.
Thanks in advance.
Thanks and Regards
Pradeep S
--
View this
Ummm... what hardware are you working on ? processor+board ?
-Abraham V.
On Mon, Jan 20, 2014 at 12:20 PM, pshambhu pradeep.sham...@gmail.com wrote:
Hi,
I am interested in changing the default serial console from UART 0 to
UART 1, which are the files need to be changed in u-boot code
On 17/01/14 17:36, Przemyslaw Marczak wrote:
On 01/17/2014 07:26 AM, Minkyu Kang wrote:
On 15/01/14 17:18, Przemyslaw Marczak wrote:
In this way we can add other functions in the future even without
CONFIG_MISC_INIT_R.
partly agree.
But, I doubt what is the role of misc.c file.
because of
Hi,
I am using P2020 PowerPC QorIQ Family Processor.
Thanks and Regards
Pradeep S
--
View this message in context:
http://u-boot.10912.n7.nabble.com/changing-default-serial-console-from-UART0-to-UART-1-tp171838p171841.html
Sent from the U-Boot mailing list archive at Nabble.com.
Hi,
Issue.
---
1) Downloaded u-boot-2010.09 source code.
(u-boot-2010.09.tar.bz2http://ftp.denx.de/pub/u-boot/u-boot-2010.09.tar.bz2)
2) Some files, have version header information along with the source code.
Ex:
1) In u-boot-2010.09/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h
*
T4/B4 SoC's have a different version of ISBC. The secure boot
functionality is different with the new version of ISBC
compared to the earlier SoC's. So the version information is added
in file config_mpc85xx.h
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping
T4/B4 SoC's have a different version of ISBC. The secure boot
functionality is different with the new version of ISBC
compared to the earlier SoC's. So the version information is added
in file config_mpc85xx.h
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Aneesh Bansal
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping
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