Hi Steve,
Hi Lukasz,
On 14-12-08 03:21 AM, Lukasz Majewski wrote:
Hi Steve,
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Signed-off-by: Steve Rae s...@broadcom.com
---
Hi,
On 12/08/2014 11:19 PM, Jeroen Hofstee wrote:
Hi,
A while ago [1], a RFC was posted to disable workaround for
besides others, errata 430973. It is a bit unclear to me which
revision actually need this workaround, but as suggested in
[2] also enabling this workaround in Linux seem to
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
board/sunxi/Kconfig | 4
Hi Steve,
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
add validation of the GPT before writing to flash
(suggested
On 12/09/2014 04:57 AM, Tom Rini wrote:
On Mon, Dec 08, 2014 at 07:52:10PM -0600, Robert Nelson wrote:
On Mon, Dec 8, 2014 at 3:44 PM, Tom Rini tr...@ti.com wrote:
Hey all,
I've pushed v2015.01-rc3 out to the repository and tarballs should exist
soon.
So, we're nearing the end now,
Offsets were overlaping, causing pamu access violations in
hypervised scenarios.
Signed-off-by: Cristian Sovaiala cristian.sovai...@freescale.com
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Reviewed-by: Fleming Andrew-AFLEMING aflem...@freescale.com
Reviewed-by: Sun Yusong-R58495
Hi,
On 09-12-14 09:56, Chen-Yu Tsai wrote:
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Hi,
On 08-12-14 12:04, Ian Campbell wrote:
On Mon, 2014-12-08 at 11:59 +0100, Hans de Goede wrote:
Hi,
On 08-12-14 10:31, Ian Campbell wrote:
On Mon, 2014-12-08 at 09:26 +, Ian Campbell wrote:
On Sun, 2014-12-07 at 21:23 +0100, Hans de Goede wrote:
The Colombus defconfig settings are
On 09/12/2014 10:14, Nikita Kiryanov wrote:
On 12/09/2014 04:57 AM, Tom Rini wrote:
On Mon, Dec 08, 2014 at 07:52:10PM -0600, Robert Nelson wrote:
On Mon, Dec 8, 2014 at 3:44 PM, Tom Rini tr...@ti.com wrote:
Hey all,
I've pushed v2015.01-rc3 out to the repository and tarballs should
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
p.s.
On 09-12-14 09:56, Chen-Yu Tsai wrote:
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi,
On Tue, Dec 9, 2014 at 5:10 PM, Hans de Goede hdego...@redhat.com wrote:
p.s.
On 09-12-14 09:56, Chen-Yu Tsai wrote:
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip,
This patch will fix the bug that the partitions on the SD card could
not be accessed and add the support for the FAT fs.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
include/configs/ls1021aqds.h | 3 +++
include/configs/ls1021atwr.h | 3 +++
2
The SD/NAND/QSPI boot definations are wrong for QE support, this
patch is to fix this error.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
include/configs/ls1021aqds.h | 3 ++-
include/configs/ls1021atwr.h | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Hi Kevin,
Lukasz Majewski l.majew...@majess.pl writes:
[...]
On 28 November 2014 at 06:46, Lukasz Majewski
l.majew...@majess.pl wrote:
Hello Javier,
Hello Lukasz,
On Fri, Nov 28, 2014 at 9:39 AM, Lukasz Majewski
l.majew...@majess.pl wrote:
I have yet to take him up
Am 18.11.2014 um 15:13 schrieb Markus Niebel:
Ping - any comments?
From: Markus Niebel markus.nie...@tq-group.com
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
drivers/mmc/mmc.c | 3 +++
include/mmc.h | 1 +
2 files changed, 4 insertions(+)
diff --git
Hi,
On Tue, Dec 9, 2014 at 2:53 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 08-12-14 15:28, Chen-Yu Tsai wrote:
On Mon, Dec 8, 2014 at 4:27 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
This is still a bit rough around the edges, I'll clean it up as
time permits and then post
Hi,
On 09-12-14 11:17, Chen-Yu Tsai wrote:
Hi,
On Tue, Dec 9, 2014 at 2:53 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 08-12-14 15:28, Chen-Yu Tsai wrote:
On Mon, Dec 8, 2014 at 4:27 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
This is still a bit rough around the edges,
On Tue, Dec 9, 2014 at 6:25 PM, Hans de Goede hdego...@redhat.com wrote:
On 09-12-14 11:17, Chen-Yu Tsai wrote:
On Tue, Dec 9, 2014 at 2:53 AM, Hans de Goede hdego...@redhat.com wrote:
On 08-12-14 15:28, Chen-Yu Tsai wrote:
On Mon, Dec 8, 2014 at 4:27 AM, Hans de Goede hdego...@redhat.com
Hi,
On 8 December 2014 at 18:27, Kevin Hilman khil...@kernel.org wrote:
Hi Simon,
Simon Glass s...@chromium.org writes:
On 8 December 2014 at 10:58, Kevin Hilman khil...@kernel.org wrote:
[...]
FWIW, the XU3 firmware is broken in other ways as well which have a
major impact on power
Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass s...@chromium.org
---
Kconfig | 9 +
arch/arm/cpu/armv7/tegra-common/Kconfig | 3 +++
arch/arm/cpu/armv7/uniphier/Kconfig | 3 +++
arch/x86/Kconfig| 3
Kconfig has been available for a while but there are still driver model
CONFIG options. Move all of these to Kconfig.
This patch isn't final - I need to wait until the SPL series can be fully
applied, which is in turn waiting on some ARM SPL problems. So for now it
is just a placeholder. But it
Hi Ajay,
On 7 December 2014 at 23:45, Ajay kumar ajayn...@gmail.com wrote:
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass s...@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add
Hi Ajay,
(resending sorry)
On 7 December 2014 at 23:45, Ajay kumar ajayn...@gmail.com wrote:
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass s...@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay
Hi Heiko,
On 8 December 2014 at 23:17, Heiko Schocher h...@denx.de wrote:
Hello Simon,
Am 09.12.2014 06:31, schrieb Simon Glass:
Hi,
On Dec 5, 2014 8:32 AM, Simon Glass s...@chromium.org wrote:
The uclass implements the same operations as the current I2C framework
but
makes some
On 8 December 2014 at 08:14, Nikita Kiryanov nik...@compulab.co.il wrote:
Introduce lcd_getbgcolor() and lcd_getfgcolor(), and use them where
applicable.
This is a preparatory step for extracting lcd console code into its own
file.
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
Cc:
(sorry, forgot to cc list)
On 9 December 2014 at 07:17, Simon Glass s...@chromium.org wrote:
Hi,
On 8 December 2014 at 01:54, Duxiaoqiang duxiaoqi...@huawei.com wrote:
Hi Michael,
Thanks for your information.
My working result show that public exponent is not the only problem caused
by
Hi Simon,
On Fri, Dec 5, 2014 at 11:12 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 5 December 2014 at 02:14, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Dec 5, 2014 at 7:43 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 4 December 2014 at 08:02, Bin Meng
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng bmeng...@gmail.com
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by:
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
This patch series add the Intel Queensbay platform support. The Queensbay
platform includes an Atom E6xx processor (codename Tunnel Creek) and a
Platform Controller Hub EG20T (codename Topcliff). The support depends
on Intel Firmware Support Package (FSP) to initialize the processor and
chipset
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Add a comment to describe
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Move setup_pch_gpios() to
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- tools/ifdtool: Change WRITE_NUM to
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/crownbay.dts | 53 +++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/pci_ids.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h
index ee98bee..26f4748 100644
--- a/include/pci_ids.h
+++
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/spi/ich.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Also update FSP support codes license header to use SPDX ID.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Update the codes to use U-Boot
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/cpu.c | 1 +
arch/x86/include/asm/post.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/queensbay/M0220661105.inc | 1288
1 file changed, 1288 insertions(+)
create mode 100644
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Replace 0xcf9 with macro PORT_RESET from processor.h
- Move FspInit call from start.S to car_init
- Add UART0_BASE and UART1_BASE
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f09db5..5033d2b 100644
--- a/arch/x86/cpu/Makefile
+++
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Update ifdtool flags to indicate FSP and CMC files are in
the board directory
- Use consistent XXX_FILE name for binary blob file
Makefile | 10 +-
include/configs/chromebook_link.h | 2 +-
2
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to use consistent name XXX_ADDR for binary blobs
Makefile | 2 +-
arch/x86/cpu/ivybridge/sdram.c | 2 +-
arch/x86/cpu/queensbay/Kconfig | 4 ++--
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
configs/crownbay_defconfig | 6 ++
include/configs/crownbay.h | 52 ++
2 files changed, 58 insertions(+)
create mode 100644 configs/crownbay_defconfig
create mode 100644
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Fix several typos in queensbay/Kconfig
- Change FSP_FILE and CMC_FILE description to indicate the file is
in the board directory
- Add help for FSP_TEMP_RAM_ADDR
- Add more help for CMC_FILE
arch/x86/Kconfig | 13
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Move PCH_LPC_DEV to arch/x86/include/asm/arch-queensbay/tnc.h
- Check return value of x86_cpu_init_f()
arch/x86/cpu/queensbay/tnc.c | 26 +-
arch/x86/include/asm/arch-queensbay/tnc.h | 15
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to rename coreboot-serial to x86-serial
arch/x86/dts/coreboot.dtsi | 2 +-
drivers/serial/Makefile| 2 +-
drivers/serial/{serial_coreboot.c = serial_x86.c} | 12
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Use ARRAY_SIZE(mmc_supported) instead of 2
- Check return value
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Remove the 'make menuconfig' in the crownbay build instructions
- Indicate all the binary blobs should be put in the board directory
doc/README.x86 | 126 +
1 file changed,
This patch-set added byte program support for sst flashes
and some implementation changes in sf to support array slow
and byte program specific controllers.
Bin Meng (1):
spi: sf: Support byte program for sst spi flash
Jagannadha Sutradharudu Teki (2):
sf: Fix look for the fastest read
From: Simon Glass s...@chromium.org
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann jens.rottm...@adlinktech.com
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by:
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch
gives a rx transfer flag to set the BP so-that sf
will operate on byte program transfer.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h
From: Bin Meng bmeng...@gmail.com
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
Hi Bin,
On 9 December 2014 at 20:59, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This patch-set added byte program support for sst flashes
and some implementation changes in sf to support array slow
and byte program specific controllers.
Bin Meng (1):
spi: sf: Support
Hi,
I created a patch for mxsldr, which adds a status read after the firmware
upload. This is necessary, if the last instruction is 'hab jump' in the sb
file, otherwise it is not working. The sb_loader is doing the same.
Best regards,
Robert Hodaszi
On 8 December 2014 at 00:23, Martin Dorwig dor...@tetronik.com wrote:
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function
pointers.
The EXPORT_FUNC macro now has 3 fixed parameters and one
variadic parameter
The
On Tuesday, December 09, 2014 at 08:20:51 AM, Stefan Roese wrote:
On 08.12.2014 23:53, Scott Wood wrote:
= nand device
Device 0: 2x nand0, sector size 128 KiB
Page size 2048 b
OOB size 64 b
Erase size 131072 b
Shouldn't you see Device 0 and Device 1 ?
Hi Simon,
On 04/12/14 15:53, Simon Glass wrote:
[715.979284 HC 0xd2]
This is a reboot command - EC_CMD_REBOOT_EC. I wonder how/why your
U-Boot might issue that command?
From my investigation, Coreboot is issuing this reboot command, because
the Coreboot payload (which in my case is U-Boot)
On 10/29/2014 11:26 PM, Chao Fu wrote:
From: Chao Fu b44...@freescale.com
Configure ls1021a scfg register for QSPI clock initalization.
Signed-off-by: Chao Fu b44...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
pci ports are used as root complex in Linux. So set this as default
in u-boot for keystone devices
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 33 +
arch/arm/include/asm/arch-keystone/hardware.h |1 +
2
On 14-12-07 05:30 PM, Michael Trimarchi wrote:
Hi
Il 07/dic/2014 02:24 Steve Rae s...@broadcom.com ha scritto:
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v2:
removed unrelated changes as
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae s...@broadcom.com
---
Changes in v3:
clean up return statement as per Michael Trimarchi
mich...@amarulasolutions.com
Changes in v2:
removed unrelated changes as per Felipe Balbi
On Tue, Nov 18, 2014 at 10:42:23AM -0800, Vikas Manocha wrote:
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Nov 18, 2014 at 10:42:22AM -0800, Vikas Manocha wrote:
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Applied to u-boot/master after adding a hunk to
arch/arm/cpu/armv7/Makefile,
On Mon, Dec 01, 2014 at 12:27:54PM -0800, Vikas Manocha wrote:
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Nov 18, 2014 at 10:42:24AM -0800, Vikas Manocha wrote:
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Applied to u-boot/master, thanks!
--
Tom
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On Mon, Dec 01, 2014 at 12:27:53PM -0800, Vikas Manocha wrote:
It is done to make space available for driver model memory.
Signed-off-by: Vikas Manocha vikas.mano...@st.com
Applied to u-boot/master, thanks!
--
Tom
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Tom,
I found a compiling error for board mx53loco, undefined reference to
`disable_sata_clock'. Not sure if this is related to recent patches from
Nikita.
York
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On Tue, Dec 09, 2014 at 11:40:11AM -0800, Steve Rae wrote:
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae s...@broadcom.com
my reviewed by remains :-)
Reviewed-by: Felipe Balbi ba...@ti.com
---
Changes in v3:
clean up
On Mon, Dec 8, 2014 at 4:19 PM, Jeroen Hofstee jer...@myspectrum.nl wrote:
Hi,
A while ago [1], a RFC was posted to disable workaround for
besides others, errata 430973. It is a bit unclear to me which
revision actually need this workaround, but as suggested in
[2] also enabling this
From: Kevin Hilman khil...@linaro.org
When CONFIG_TRACE is disabled, linking fails with:
common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to
`trace_early_init'
To fix, wrap the call to trace_early_init() with #ifdef CONFIG_TRACE.
Cc: Simon Glass s...@chromium.org
Cc: Tom
Hyungwon Hwang human.hw...@samsung.com writes:
This is v11 of the patchset adding support Odroud XU3 board.
I finally got around to testing this on top of v2015.01-rc3 on my XU3.
As I mentioned earlier, I had to enable the USB and networking options
so I could dhcp/tftp but after that it works
Simon Glass s...@chromium.org writes:
On 8 December 2014 at 18:27, Kevin Hilman khil...@kernel.org wrote:
[...]
So is secure-mode enabled before BL2 is started? Or do you mean BL2 is
where secure-mode is enabled? If it's done in BL2, and if the
hardkernel folks are willing to sign BL2
Hi Kevin,
On 9 December 2014 at 17:03, Kevin Hilman khil...@kernel.org wrote:
Simon Glass s...@chromium.org writes:
On 8 December 2014 at 18:27, Kevin Hilman khil...@kernel.org wrote:
[...]
So is secure-mode enabled before BL2 is started? Or do you mean BL2 is
where secure-mode is
On Wed, 2014-12-03 at 14:20 -0800, Simon Glass wrote:
Hi Peter,
On 3 December 2014 at 13:53, Peter Howard p...@northern-ridge.com.au wrote:
On Wed, 2014-12-03 at 06:38 -0700, Simon Glass wrote:
Hi Peter,
On 2 December 2014 at 14:59, Peter Howard p...@northern-ridge.com.au
wrote:
Hi Peter,
On 9 December 2014 at 17:13, Peter Howard p...@northern-ridge.com.au wrote:
On Wed, 2014-12-03 at 14:20 -0800, Simon Glass wrote:
Hi Peter,
On 3 December 2014 at 13:53, Peter Howard p...@northern-ridge.com.au
wrote:
On Wed, 2014-12-03 at 06:38 -0700, Simon Glass wrote:
Hi Kevin,
On 9 December 2014 at 16:03, Kevin Hilman khil...@kernel.org wrote:
From: Kevin Hilman khil...@linaro.org
When CONFIG_TRACE is disabled, linking fails with:
common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to
`trace_early_init'
To fix, wrap the call to
Hi,
On 9 December 2014 at 11:19, SimonH simon.hoin...@codethink.co.uk wrote:
Hi Simon,
On 04/12/14 15:53, Simon Glass wrote:
[715.979284 HC 0xd2]
This is a reboot command - EC_CMD_REBOOT_EC. I wonder how/why your
U-Boot might issue that command?
From my investigation, Coreboot is issuing
Dear Kevin,
On Tue, 09 Dec 2014 15:36:00 -0800
Kevin Hilman khil...@kernel.org wrote:
Hyungwon Hwang human.hw...@samsung.com writes:
This is v11 of the patchset adding support Odroud XU3 board.
I finally got around to testing this on top of v2015.01-rc3 on my XU3.
As I mentioned
On 12/09/2014 01:38 AM, Alison Wang wrote:
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change
Hello Hyungwon Hwang,
On Tue, Dec 9, 2014 at 4:58 PM, Hyungwon Hwang human.hw...@samsung.com wrote:
Dear Kevin,
On Tue, 09 Dec 2014 15:36:00 -0800
Kevin Hilman khil...@kernel.org wrote:
Hyungwon Hwang human.hw...@samsung.com writes:
This is v11 of the patchset adding support Odroud XU3
Hi, York,
On 12/09/2014 01:38 AM, Alison Wang wrote:
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash first.
Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang alison.w...@freescale.com
York,
On 12/09/2014 01:38 AM, Alison Wang wrote:
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash first.
Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang
Hi, York,
On 10/29/2014 11:26 PM, Chao Fu wrote:
From: Chao Fu b44...@freescale.com
Configure ls1021a scfg register for QSPI clock initalization.
Signed-off-by: Chao Fu b44...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
I should probably explain the people involved here. Joshua did most of
the porting work. I (Chris) picked it up to finish things off and to
do some more testing. I'll also be the one trying to get this accepted
upstream.
Because my employer paid for us to do the work I've signed with my work
Dear Suriyan,
On Tue, 09 Dec 2014 18:29:56 -0800
Suriyan Ramasami suriya...@gmail.com wrote:
Hello Hyungwon Hwang,
On Tue, Dec 9, 2014 at 4:58 PM, Hyungwon Hwang
human.hw...@samsung.com wrote:
Dear Kevin,
On Tue, 09 Dec 2014 15:36:00 -0800
Kevin Hilman khil...@kernel.org wrote:
Add the following configuration:
o CONFIG_SYS_GENERIC_BOARD
o CONFIG_DISPLAY_BOARDINFO
Signed-off-by: Chris Packham judge.pack...@gmail.com
---
Builds, pings and boots a kernel. Any other testing needed?
include/configs/P2041RDB.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi Tom,
On 7 December 2014 at 19:01, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
On Sun, 7 Dec 2014 14:44:21 -0700
Simon Glass s...@chromium.org wrote:
#endif
diff --git a/arch/x86/include/asm/linkage.h
b/arch/x86/include/asm/linkage.h
new file mode 100644
index
From: Thierry Reding tred...@nvidia.com
Implement the powergate API that allows various power partitions to be
power up and down.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
From: Thierry Reding tred...@nvidia.com
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Simon Glass s...@chromium.org
---
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