On Thu, Dec 18, 2014 at 9:19 PM, Tom Rini tr...@ti.com wrote:
On Thu, Dec 11, 2014 at 11:55:05AM +0100, Belisko Marek wrote:
Hi,
I'm using latest u-boot master
(9b416a9f4ca7cf5ac4d5f7143d67edde7f7d7326) running on beaglebone
(white). This board has watchdog enabled by default for 60 secs
The fsl_immap.h header file had been included in common.h
header file. So remove duplicated header.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c|1 -
drivers/ddr/fsl/fsl_ddr_gen4.c |1 -
drivers/ddr/fsl/util.c |1 -
3 files changed, 0
On 23/11/2014 04:52, Peng Fan wrote:
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0x', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.
Also include an err message when unsupported mxc_clock type is
On Sat, 13 Dec 2014 12:00:44 +0100
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 12-12-14 21:25, Siarhei Siamashka wrote:
On Sun, 23 Nov 2014 14:43:13 +0100
Hans de Goede hdego...@redhat.com wrote:
The A31s only has one dram channel, so do not bother with trying to
initialize
a
On Tue, 16 Dec 2014 21:31:33 +0100
Hans de Goede hdego...@redhat.com wrote:
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 9 +++--
On Tue, 16 Dec 2014 21:31:34 +0100
Hans de Goede hdego...@redhat.com wrote:
The A23 (sun8i) requires different values for these then sun6i, so make them
function parameters.
Signed-off-by: Hans de Goede hdego...@redhat.com
What happens if A23 does not get these special k and m parameters,
On Tue, 16 Dec 2014 21:31:35 +0100
Hans de Goede hdego...@redhat.com wrote:
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.
Signed-off-by:
On Thu, 18 Dec 2014 19:12:13 +
Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote:
The sun8i boot0 code fills the DRAM with a random pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not
On Tue, 16 Dec 2014 21:31:38 +0100
Hans de Goede hdego...@redhat.com wrote:
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Can the commit message have more detailed information about the precise
location of the original
This commit adds a dump command of DDR PHY parameters of UniPhier
SoC family. It might not be used very often for the regular operation
but it would be useful when something goes wrong with DDR memories.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Masahiro Yamada (3):
ARM: UniPhier: add DDR PHY training code
ARM: UniPhier: add dump command of DDR PHY parameters
ARM: UniPhier: display boot swap pin status by pinmon command
arch/arm/cpu/armv7/uniphier/Kconfig| 7 +
arch/arm/cpu/armv7/uniphier/Makefile
This information would be useful enough.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
index
This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
arch/arm/cpu/armv7/uniphier/Makefile | 1 +
arch/arm/cpu/armv7/uniphier/ddrphy_training.c | 144 +
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.
Also we now call the hw_watchdog_init() function so that we override
the value already
The current current watchdog timeout of 12 seconds is a bit small for
booting into Linux, especially when using a NFS based rootfs. So lets
change this timeout to a more defensive value of 30 seconds.
Also we now call the hw_watchdog_init() function so that we override
the value already
On 19 December 2014 at 10:46, Masahiro Yamada yamad...@jp.panasonic.com wrote:
To enjoy driver-model on sandbox, using device tree is recommended.
While we are here, change sandbox_config to sandbox_defconfig too.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Hi Emil,
On 07/12/2014 18:59, Emil Renner Berthing wrote:
Signed-off-by: Emil Renner Berthing u-b...@esmil.dk
---
arch/arm/Kconfig | 5 +
arch/arm/include/asm/arch-mx5/iomux-mx51.h | 19 ++
arch/arm/include/asm/mach-types.h | 13 +
Jagan,
On Fri, 19 Dec 2014 18:43:37 +0530
Jagan Teki jagannadh.t...@gmail.com wrote:
On 19 December 2014 at 10:46, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
To enjoy driver-model on sandbox, using device tree is recommended.
While we are here, change sandbox_config to
Hello Simon,
On Thu, 18 Dec 2014 11:26:12 -0700, Simon Glass s...@chromium.org
wrote:
This is an attempt to tidy up the early SPL code in an attempt to pave
the way for driver model in SPL:
- Avoid setting up SDRAM before board_init_f()
- Avoid touching global_data before board_init_f()
By
On Thu, Dec 18, 2014 at 05:21:21PM -0700, Simon Glass wrote:
This is an attempt to tidy up the early SPL code in an attempt to pave
the way for driver model in SPL:
- Avoid setting up SDRAM before board_init_f()
- Avoid touching global_data before board_init_f()
- Allow board_init_f() to
On 14/12/2014 16:34, Jan Luebbe wrote:
The weak mxs_adjust_memory_params function is called from spl_mem_init.c,
so it must be linked into the SPL to have an effect. Move it from
mx23_olinuxino.c to spl_boot.c.
This change was verified by reading back the register values.
Signed-off-by:
On 04/12/2014 13:04, Stefan Roese wrote:
Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.
This problem was introduced with this patch:
e25fbe3f (gw_ventana: Move the DCD settings to spl code)
On 04/12/2014 09:56, Christian Gmeiner wrote:
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, MD:
On 12/12/2014 15:33, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
On 02/12/2014 02:55, Peng Fan wrote:
Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power
Signed-off-by: Peng Fan peng@freescale.com
---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
On 04/12/2014 09:55, Christian Gmeiner wrote:
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, MD:
On 02/12/2014 02:55, Peng Fan wrote:
Add pinmux settings and implement board_ehci_hcd_init
Signed-off-by: Peng Fan peng@freescale.com
---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=
DENX Software
Hi,
On 18-12-14 19:59, Ian Campbell wrote:
On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote:
@@ -128,7 +128,8 @@
#define SUN6I_CPUCFG_BASE 0x01f01c00
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
-#define
Hi Tom, Albert,
On 19 December 2014 at 07:40, Tom Rini tr...@ti.com wrote:
On Thu, Dec 18, 2014 at 05:21:21PM -0700, Simon Glass wrote:
This is an attempt to tidy up the early SPL code in an attempt to pave
the way for driver model in SPL:
- Avoid setting up SDRAM before board_init_f()
-
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by
On 12/09/2014 02:32 PM, Murali Karicheri wrote:
pci ports are used as root complex in Linux. So set this as default
in u-boot for keystone devices
Signed-off-by: Murali Karicherim-kariche...@ti.com
---
arch/arm/cpu/armv7/keystone/init.c| 33 +
Hi,
On 19-12-14 11:03, Siarhei Siamashka wrote:
On Tue, 16 Dec 2014 21:31:34 +0100
Hans de Goede hdego...@redhat.com wrote:
The A23 (sun8i) requires different values for these then sun6i, so make them
function parameters.
Signed-off-by: Hans de Goede hdego...@redhat.com
What happens if A23
Hi,
On 19-12-14 11:06, Siarhei Siamashka wrote:
On Tue, 16 Dec 2014 21:31:35 +0100
Hans de Goede hdego...@redhat.com wrote:
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h,
Hi,
On 18-12-14 20:17, Ian Campbell wrote:
On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote:
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Signed-off-by: Hans de Goede hdego...@redhat.com
+/*
+ * Note this code uses
Hi,
On 18-12-14 20:12, Ian Campbell wrote:
On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote:
The sun8i boot0 code fills the DRAM with a random pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, but it seems like a good
Hi,
On 19-12-14 11:08, Siarhei Siamashka wrote:
On Thu, 18 Dec 2014 19:12:13 +
Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote:
The sun8i boot0 code fills the DRAM with a random pattern before comparing
it at different offsets to do columns,
This patches add support for VSC9953, a Vitesse L2 Switch IP
which is integrated in the T1040/T1020 Freescale SoCs.
About Device:
=
The Seville Gigabit Ethernet switch core contains eight 10/100/1000 Mbps
Ethernet ports and two 10/100/1000/2500 Mbps ports. It provides a rich
set of
U-boot assumes that all FMAN ports have a PHY. Some SoCs (like T1040)
have fixed links. This means that the ports are connected MAC to MAc
and there is no Ethernet PHY attatched. This patch initializes a
FMAN MAC even if it doesn't have a PHY attached.
Signed-off-by: Codrin Ciubotariu
If SerDes is configured to connect L2 Switch ports from T1040
over SGMII or QSGMII, the two FMAN fixed ports (FM1@DTSEC1 and FM2@DTSEC2)
that are connected to two L2 swtch ports must be enabled. These
ports don't have PHYs and must be treated accordingly.
Signed-off-by: Codrin Ciubotariu
This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
is integrated in Freescale T1040 and T1020 SoCs.
The L2 switch has 10 Ethernet ports: 2 internal fixed-links
(ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
The external ports may be connected to PHYs over QSGMII and
The number of supported serdes protocols on Freescale SoCs
has increased over time. Until now, an u64 variable have been
initialized on boot with the configured protocols. However,
since this number has increased (enum srds_prtcl has more
than 64 values), 64 bits are no longer sufficient to hold
Freescale's T1040qds board may be configured to have up to
5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports,
2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2),
connected to other two ports from an intergrated
VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link
ports have
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: If65224646f737270dad1ef3558a400a002e9d4b6
---
arch/powerpc/cpu/mpc8xxx/cpu.c| 7 +++
arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
2 files changed, 10 insertions(+)
diff --git
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: I911b61580681f4b042b1f280a6a60ebf91d9ab13
---
board/freescale/t1040qds/eth.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 06d9086..c6fc146
This patch configures and initializes the L2 switch on T1040rdb board.
The external L2 switch ports may be connected to PHYs only over
QSGMII, for T1040rdb.
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: I56ae23192daa882c66d04b64b9a7d32531a13db0
---
Some Freescale SoCs like T1020 and T1040 have an integrated
L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs
over SGMII and QSGMII.
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: Idadad19d469efc45f03c6f8884c3647e02b28df4
---
This patch configures and initializes the L2 switch on T1040QDS board.
The L2 switch ports must be initialized according to the SerDes
protocols.
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Change-Id: I329f9cc1b1be745da23151e78831d8a3219b7f97
---
Freescale's T1040qds board may be configured to have up to
5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports,
2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2),
connected to other two ports from an intergrated
VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link
ports have
Hi,
On 19-12-14 11:20, Siarhei Siamashka wrote:
On Tue, 16 Dec 2014 21:31:38 +0100
Hans de Goede hdego...@redhat.com wrote:
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Can the commit message have more detailed
Hi Anatolij Ian,
Here is v2 of my patch-series to make the video-mode configurable on sunxi
and use EDID where available.
In version 2 I've switched to using the existing infra in videomodes.c
as much as possible, including using the standard video-mode env. variable,
and the existing functions
Add pixelclock_khz and refresh fields to ctfb_res_modes:
1) pixelclocks are usually referred to in hz, not picoseconds, and e.g
pll-s are also typically programmed in hz, not ps. Converting between the
2 leads to rounding differences, add a pixelclock_khz field to directly
store the *exact*
Add modes useful for hd-tvs and modern monitors.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/videomodes.c | 4
drivers/video/videomodes.h | 6 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
The timings for the modes defined in videomodes.c differ (significantly)
from vesa standard timings for these modes.
This commit adds a version with the proper std timings for these modes,
since I do not want to cause regressions, boards which want to use the standard
timings need to define
Add a video_edid_dtd_to_ctfb_res_modes helper function to convert an EDID
detailed timing to a struct ctfb_res_modes.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/videomodes.c | 73 ++
drivers/video/videomodes.h | 4 +++
Add support for the standard video-mode environment variable using the
videomodes.c video_get_ctfb_res_modes() helper function.
This will allow users to specify the resolution e.g. :
setenv video-mode sunxi:video-mode=1280x1024-24@60
saveenv
Also make the reserved fb mem slightly larger to
Add a video_get_ctfb_res_modes() helper function, which uses
video_get_video_mode() to parse the 'video-mode' environment variable and then
looks up the matching mode in res_mode_init and returns the matching mode.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/videomodes.c |
Add DDC EDID support and use it to automatically select the native mode of
the attached monitor. This can be disabled by adding edid=0 as option
to the video-mode env. variable.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/include/asm/arch-sunxi/display.h | 85
Add a helper function to check the checksum of an EDID data block.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
common/edid.c | 12
include/edid.h | 9 +
2 files changed, 21 insertions(+)
diff --git a/common/edid.c b/common/edid.c
index e66108f..df797fc 100644
---
Switch from fb_videomode to ctfb_res_modes and use the predefined videotimings
from videomodes.c, rather then defining our own.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/Makefile | 2 +-
drivers/video/sunxi_display.c | 41
Add 2 helper functions to get strings, reps. ints from the options value
returned by video_get_video_mode() / video_get_ctfb_res_modes().
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/videomodes.c | 60 +-
Allow the user to specify hpd=0 as option in the video-mode env. variable,
if hpd is set to 0 then the hdmi output will be brought up even if no cable
is connected.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/video/sunxi_display.c | 26 +-
1 file changed,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/pci.c | 2 ++
1 file changed, 2 insertions(+)
Please can you always add a commit message even if only one line?
Regards,
Simon
On 12/19/2014 01:44 AM, Chunhe Lan wrote:
The fsl_immap.h header file had been included in common.h
header file. So remove duplicated header.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
Did you test this patch? Please rebase and compile for powerpc and arm
platforms.
York
Master send to / receive from 10-bit addressed slave devices
can be supported by software layer without any hardware change
because the LSB 8bit of the slave address is treated as data part.
Master Send to a 10bit-addressed slave chip is performed like this:
DIRFormat
M-S 0 +
To store 10bit chip address, the variable type should not be uchar,
but uint.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Heiko Schocher h...@denx.de
Cc: Simon Glass s...@chromium.org
---
common/cmd_i2c.c | 22 +++---
1 file changed, 11 insertions(+), 11
10bit addressing can be supported by purely software.
It seems reasonable enough to handle 10bit-addressing within
i2c-uclass.c just like we have already supported offset address there.
Masahiro Yamada (2):
cmd_i2c: change variable type for 10bit addressing support
dm: i2c: support 10bit
Hi Tom and Masahiro,
Neither my collegue nor I could reproduce the problem you encountered with
our patch and the build line, LANG=C make -j8
CROSS_COMPILE=arm-linux-gnueabi- ph1_ld4_defconfig all. Any
suggestions on other ways to fix the false error and not break paralell
builds would be
On 19 December 2014 at 06:39, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Jagan,
On Fri, 19 Dec 2014 18:43:37 +0530
Jagan Teki jagannadh.t...@gmail.com wrote:
On 19 December 2014 at 10:46, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
To enjoy driver-model on sandbox, using
On 19 December 2014 at 11:34, Masahiro Yamada yamad...@jp.panasonic.com wrote:
To store 10bit chip address, the variable type should not be uchar,
but uint.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Heiko Schocher h...@denx.de
Cc: Simon Glass s...@chromium.org
---
Hi Masahiro,
On 19 December 2014 at 11:34, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Master send to / receive from 10-bit addressed slave devices
can be supported by software layer without any hardware change
because the LSB 8bit of the slave address is treated as data part.
Master
Hi BIn,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
Newer x86 Platform Controller Hub chipset starts to integrate NS16550
compatible PCI UART devices. The board configuration file needs to
supply the PCI UART vendor ID and device ID via CONFIG_PCI_UART_DEV
if we want to
The gd will be cleared at first so we don't need to set arch.tbl to 0.
In addition, the checks later against lastinc also work fine with an
initial value of 0 here. This also brings us in line with sunxi code
for example.
Signed-off-by: Tom Rini tr...@ti.com
---
The save_boot_params function here is the same as the default weak one
from arch/arm/cpu/armv7/start.S, drop.
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Vince Bridgers vbrid...@opensource.altera.com
Cc: Chin Liang See cl...@altera.com
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini
In both SPL and non-SPL cases we will make a call to timer_init() early
on and do not need to call it again within s_init().
Signed-off-by: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/am33xx/board.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
Prior to this change we set the gd pointer early so that we can store
data in it. This becomes problematic for DM changes as well as being
odd in general. Re-work the code paths so that we don't need to set the
gd pointer so early and instead can rely upon the normal setting of it.
In order to
In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms. As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.
Cc: Peter Howard p...@northern-ridge.com.au
Signed-off-by: Tom Rini
Hi Bin,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
This new API pci_early_find_devices() is derived from the generic
version of pci_find_devices() with modifications required in the
early phase (like hose, config space access routines).
Signed-off-by: Bin Meng
On Fri, 2014-12-19 at 16:53 -0500, Tom Rini wrote:
In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms. As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.
Cc: Peter Howard
Hi Simon,
On Sat, Dec 20, 2014 at 1:40 AM, Simon Glass s...@chromium.org wrote:
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/pci.c | 2 ++
1 file changed, 2 insertions(+)
Please can you always add a commit
Hi Simon,
On Sat, Dec 20, 2014 at 5:53 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
This new API pci_early_find_devices() is derived from the generic
version of pci_find_devices() with modifications required in the
early
On Friday, December 19, 2014 at 10:52:53 PM, Tom Rini wrote:
The save_boot_params function here is the same as the default weak one
from arch/arm/cpu/armv7/start.S, drop.
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Vince Bridgers vbrid...@opensource.altera.com
Cc: Chin Liang See
Hi Simon,
On Sat, Dec 20, 2014 at 5:52 AM, Simon Glass s...@chromium.org wrote:
Hi BIn,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
Newer x86 Platform Controller Hub chipset starts to integrate NS16550
compatible PCI UART devices. The board configuration file needs to
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is
Hi Bin,
On 19 December 2014 at 19:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Dec 20, 2014 at 5:53 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
This new API pci_early_find_devices() is derived from the
Hi Bin,
On 19 December 2014 at 19:43, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Dec 20, 2014 at 5:52 AM, Simon Glass s...@chromium.org wrote:
Hi BIn,
On 19 December 2014 at 00:19, Bin Meng bmeng...@gmail.com wrote:
Newer x86 Platform Controller Hub chipset starts to integrate
Hi Simon,
On Sat, Dec 20, 2014 at 12:56 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 December 2014 at 19:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Dec 20, 2014 at 5:53 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 December 2014 at 00:19, Bin Meng
Hi Simon,
On Sat, Dec 20, 2014 at 1:00 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 December 2014 at 19:43, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Dec 20, 2014 at 5:52 AM, Simon Glass s...@chromium.org wrote:
Hi BIn,
On 19 December 2014 at 00:19, Bin Meng
On 20 December 2014 at 02:18, Simon Glass s...@chromium.org wrote:
On 19 December 2014 at 06:39, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
Jagan,
On Fri, 19 Dec 2014 18:43:37 +0530
Jagan Teki jagannadh.t...@gmail.com wrote:
On 19 December 2014 at 10:46, Masahiro Yamada
Hi Simon,
2014-12-20 6:34 GMT+09:00 Simon Glass s...@chromium.org:
Hi Masahiro,
On 19 December 2014 at 11:34, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
Master send to / receive from 10-bit addressed slave devices
can be supported by software layer without any hardware change
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