Hello Stefan,
Am 09.03.2015 16:49, schrieb Stefan Roese:
Without this patch, the IMX watchdog will not be initialized. And therefor
not active. This patch fixes this by calling hw_watchdog_init() also when
CONFIG_IMX_WATCHDOG is defined.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue, this is a workaround.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
drivers/pci/fsl_pci_init.c | 17 +
include/configs/T208xQDS.h | 1
I hope my last message didn't get lost during that outage last month.
In the mean time, I had to finagle the HardKernel code to work with
GCC 5.0 which ended up being only 1 line change which I may end up
encountering in mainline if I ever get far enough.
After transferring the CONFIG_MMC_TRACE
Hi,
On 04-03-15 08:44, Aleksei Mamlin wrote:
This patch add support for Wexler TAB7200 tablet.
The Wexler TAB7200 is a A20 based tablet with 7 inch display(800x480),
capacitive touchscreen(5 fingers), 1G RAM, 4G NAND, micro SD card slot,
mini HDMI port, 3.5mm audio plug, 1 USB OTG port and 1
This change adds driver model support to software emulated
i2c bus driver. To bind the driver, proper device-tree node
must be defined, with the following attributes:
- alias: to keep proper bus order
- compatible: 'soft-i2c'
- clock-frequency [Hz]
- clock-pin, data-pin: gpio phandles
/* Define
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Simon Glass s...@chromium.org
Cc: Heiko Schocher h...@denx.de
---
drivers/i2c/Kconfig | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
This patchset enables driver model support for software i2c bus driver.
It was tested on Trats2 and Odroid U3 devices.
It can be tested on any other device by just modifying the dts file,
first by disabling the hardware i2c bus and then, as it is described
in the Kconfig help entry, setup
When Beagle X15 is connected to Gigabit switch, it takes
more time to finish auto-negotiation than on a 10/100 switch.
The default 4 second limit times-out more often than not. This is
observed when testing with a D-Link DGS-1008A desktop switch.
Increase the auto-negotiation time-out for
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Mike Frysinger vap...@gentoo.org
Cc: Simon Glass s...@chromium.org
Cc: Heiko Schocher h...@denx.de
---
drivers/i2c/Kconfig | 43 +++
1 file changed, 43
The build break was caused by one of my previous commit:
'odroid: defconfig: disable memset at malloc init'
It removes the dts from odroid defconfig - rebase mistake.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
configs/odroid_defconfig | 1 +
On Tue, Mar 10, 2015 at 3:08 AM, feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
CPU_RELEASE_ADDR should be defined when CONFIG_ARMV8_MULTIENTRY is used.
Signed-off-by: David Feng feng...@phytium.com.cn
As asked earlier: how can I test this with FVP or the base model?
Hi,
On 08-03-15 10:04, Ian Campbell wrote:
On Sat, 2015-03-07 at 15:04 +0100, Hans de Goede wrote:
Fix a type in board/sunxi/Kconfig which caused VIDEO_LCD_PANEL_I2C to be
typo
Heh, so I made a typo in the word typo, fixed :)
+#define CONFIG_VIDEO_LCD_I2C_BUS 1 /* NA, but necessary
Hi,
On 03/03/2015 05:24 PM, Przemyslaw Marczak wrote:
This is the implementation of driver model regulator uclass api.
To use it, the CONFIG_DM_PMIC is required with driver implementation,
since it provides pmic devices basic I/O API.
The regulator framework is based on a 'struct
Hi,
On Tue, Mar 10, 2015 at 7:08 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 09-03-15 08:44, Chen-Yu Tsai wrote:
Hi Hans,
This series fixes otg support on the A23 q8h tablets. It adds support
for the AXP's (AXP221/223 for now) VBUS detection function.
I've tested this with a USB
Hi Przemyslaw,
The build break was caused by one of my previous commit:
'odroid: defconfig: disable memset at malloc init'
It removes the dts from odroid defconfig - rebase mistake.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Hi,
On 09-03-15 08:44, Chen-Yu Tsai wrote:
Hi Hans,
This series fixes otg support on the A23 q8h tablets. It adds support
for the AXP's (AXP221/223 for now) VBUS detection function.
I've tested this with a USB wireless keyboard dongle, which works fine.
More importantly, I'm using this and
This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis
On Tue, 2015-03-10 at 12:38 +0100, Hans de Goede wrote:
Or at least #define it to some obviously bogus value (e.g. ~0UL).
That is a good idea, I've changed it to -1 in my personal tree.
With that:
Acked-by: Ian Campbell i...@hellion.org.uk
___
Hi Simon,
Do you know what will be the timeframe of when someone may be able to look at
this in more detail. I will be able to help test any updates if needed
Thanks,
Tom
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Monday, March 09,
Hi Stefan,
On Fri, Mar 6, 2015 at 10:43 AM, Stefan Roese s...@denx.de wrote:
This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error
upon U-Boot update:
MMC write: dev # 0, block # 2, count 711 ... mmc write failed
With this patch reverted it looks just fine:
MMC write:
Hi Scott,
Le Mon, 9 Mar 2015 18:51:03 -0500, Scott Wood scottw...@freescale.com
a écrit :
On Thu, 2015-03-05 at 07:46 +0100, Albert ARIBAUD (3ADEV) wrote:
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..cb23972
Hi Fabio,
On 10.03.2015 14:29, Fabio Estevam wrote:
This patch breaks eMMC on my TQMa6S (i.MX6SOLO). With it I get this error
upon U-Boot update:
MMC write: dev # 0, block # 2, count 711 ... mmc write failed
With this patch reverted it looks just fine:
MMC write: dev # 0, block # 2, count
Sure, I understand from seeing all of the patches you submit. I
thought I'd at least ask in case it was something easy.
I'll continue to look into it. Thanks for submitting those links.
I didn't try any other sdcard since the card does work fine with
Hardkernel's old pre-built binaries.
On Tue,
On Monday, March 09, 2015 at 10:59:34 PM, Dinh Nguyen wrote:
On 3/4/15 7:21 AM, Marek Vasut wrote:
On Monday, March 02, 2015 at 05:28:05 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
On Tuesday, March 10, 2015 at 08:35:46 AM, Peng Fan wrote:
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.
Change the char reserved3[59] to char reserved3[56].
Signed-off-by: Peng Fan peng@freescale.com
This should probably be applied to 2015.04 .
Hello Nathan,
On 03/10/2015 12:30 PM, Nathan wrote:
I hope my last message didn't get lost during that outage last month.
In the mean time, I had to finagle the HardKernel code to work with
GCC 5.0 which ended up being only 1 line change which I may end up
encountering in mainline if I ever
I have transferred to Socionext Inc.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a0de3d..26780f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -159,7 +159,7 @@
Hi,
On 03/10/2015 05:52 PM, Guillaume Gardet wrote:
Le 28/02/2015 08:59, Minkyu Kang a écrit :
Joonyoung,
On 26/02/15 00:22, Guillaume GARDET wrote:
Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch
On Tue, Mar 10, 2015 at 10:25:03PM +, Tom Warren wrote:
Albert – are you getting these emails? I know they’re bouncing from
the list (need to find a mailer that doesn’t use MIME64), but I
haven’t heard back from you for the last 2 PRs.
FWIW, you can make git send-email do the sending of
On Wednesday, March 11, 2015 at 01:58:37 AM, Peng Fan wrote:
Hi, Marek
Hi!
On 3/10/2015 9:45 PM, Marek Vasut wrote:
On Tuesday, March 10, 2015 at 08:35:46 AM, Peng Fan wrote:
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.
Change the char
Hi,
I have a board using SPI flash for it's boot-loader and environment,
I'm currently based of u-boot 2014.01. In my boards config file I have
the following
#define CONFIG_SILENT_CONSOLE
#define CONFIG_SILENT_U_BOOT_ONLY
#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
#define
Hi, Marek
On 3/10/2015 9:45 PM, Marek Vasut wrote:
On Tuesday, March 10, 2015 at 08:35:46 AM, Peng Fan wrote:
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.
Change the char reserved3[59] to char reserved3[56].
Signed-off-by: Peng Fan peng@freescale.com
Hi Simon,
Sorry for my late reply.
2015-03-04 9:18 GMT+09:00 Simon Glass s...@chromium.org:
Hi Masahiro,
On 19 January 2015 at 05:12, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
This tool can move CONFIG macros from C headers (include/configs/*.h)
to defconfigs (configs/*_defconfig)
On Tue, 2015-03-10 at 03:50 -0500, Bansal Aneesh-B39320 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, March 05, 2015 10:38 PM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
Subject: Re: [U-Boot, 1/2, v4]
On Tue, 2015-03-10 at 12:52 -0500, Bansal Aneesh-B39320 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, March 10, 2015 10:34 PM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431;
Kushwaha Prabhakar-B32579
Subject:
resend with Tom's new email address
Hi Tom,
We've build-up a small collection of fixes for sunxi.
Please pull u-boot-sunxi/master into master, highlights:
1) 2 bug fixes
2) 1 regression fix
3) Add support for a couple of new boards
The following changes since commit
Enable pcf driver to control the pcf chip present
at address 0x21 on i2c1.
Signed-off-by: Vignesh R vigne...@ti.com
---
include/configs/dra7xx_evm.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, March 10, 2015 10:34 PM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431;
Kushwaha Prabhakar-B32579
Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND
secure boot
Hi, Marek
On 3/11/2015 10:03 AM, Marek Vasut wrote:
On Wednesday, March 11, 2015 at 01:58:37 AM, Peng Fan wrote:
Hi, Marek
Hi!
On 3/10/2015 9:45 PM, Marek Vasut wrote:
On Tuesday, March 10, 2015 at 08:35:46 AM, Peng Fan wrote:
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this support with the existing U-Boot Designware MAC driver
so that the ethernet port on Intel Galileo board can be used.
Signed-off-by: Bin Meng
Resending as some issue in my mail-box.
Regards,
Prabhakar
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, March 11, 2015 10:01 AM
To: 'Zhao Qiang'; u-boot@lists.denx.de; Sun York-R58495
Subject: RE: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for
I have transferred to Socionext Inc.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
doc/git-mailrc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 025c0b3..5f8438e 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@
I have transferred to Socionext Inc.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
doc/git-mailrc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 025c0b3..5f8438e 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@
I have transferred to Socionext Inc.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a0de3d..26780f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -159,7 +159,7 @@
Thanks, Tom. Should I send future PRs to you instead of Albert?
On Mar 10, 2015 5:55 PM, Tom Rini tr...@konsulko.com wrote:
On Tue, Mar 10, 2015 at 10:25:03PM +, Tom Warren wrote:
Albert – are you getting these emails? I know they’re bouncing from
the list (need to find a mailer that
Hi Zhao,
Can you please rephrase the subject.
No need to mention T2080QDS twice in the subject
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhao Qiang
Sent: Tuesday, March 10, 2015 2:55 PM
To: u-boot@lists.denx.de; Sun York-R58495
Cc: Zhao
Resending because some issue in my mail-box.
Regards,
Prabhakar
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Wednesday, March 11, 2015 10:01 AM
To: 'Zhao Qiang'; u-boot@lists.denx.de; Sun York-R58495
Subject: RE: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS
Hi Yehuda, Tom, Simon,
2015-03-07 0:12 GMT+09:00 Tom Rini tr...@konsulko.com:
On Thu, Mar 05, 2015 at 06:20:35PM +, Yehuda Yitschak wrote:
Hey Tom
In arch/arm/dts/Makfile: line 56
DTC_FLAGS += -R 4 -p 0x1000
this tell the dtc tool to add a 4K padding to the device tree blob.
i
TI's pcf8575 is a 16-bit I2C based GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os should be high before being used as inputs.
This driver is based
On Tue, Mar 10, 2015 at 08:41:21PM +0530, Vignesh R wrote:
TI's pcf8575 is a 16-bit I2C based GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os
On 03/10/2015 09:25 AM, Gupta Ruchika-R66431 wrote:
Hi York,
-Original Message-
From: Sun York-R58495
Sent: Tuesday, March 10, 2015 9:45 PM
To: Rana Gaurav-B46163; u-boot@lists.denx.de
Cc: Wood Scott-B07421; Gupta Ruchika-R66431; Bansal Aneesh-B39320
Subject: Re: [PATCH] Add
On Tue, Mar 10, 2015 at 04:00:54PM +0100, Hans de Goede wrote:
resend with Tom's new email address
No worries, mutt still hightlights the old one :)
Hi Tom,
We've build-up a small collection of fixes for sunxi.
Please pull u-boot-sunxi/master into master, highlights:
1) 2 bug fixes
2)
Hi York,
-Original Message-
From: Sun York-R58495
Sent: Tuesday, March 10, 2015 9:45 PM
To: Rana Gaurav-B46163; u-boot@lists.denx.de
Cc: Wood Scott-B07421; Gupta Ruchika-R66431; Bansal Aneesh-B39320
Subject: Re: [PATCH] Add bootscript support to esbc_validate.
On 03/10/2015
On 03/10/2015 01:38 AM, Gaurav Rana wrote:
1. Default environment will be used for secure boot flow
which can't be edited or saved.
2. Command for secure boot is predefined in the default
environment which will run on autoboot (and autoboot is
the only option allowed in case of secure
Hi Tom,
We've build-up a small collection of fixes for sunxi.
Please pull u-boot-sunxi/master into master, highlights:
1) 2 bug fixes
2) 1 regression fix
3) Add support for a couple of new boards
The following changes since commit 44c8fd3abaded5bf18a48947c6d1286927cbdf2b:
common: cmd_elf:
Hi,
On 03/10/2015 02:14 PM, Nathan wrote:
Sure, I understand from seeing all of the patches you submit. I
thought I'd at least ask in case it was something easy.
I'll continue to look into it. Thanks for submitting those links.
I didn't try any other sdcard since the card does work fine
On DRA72 EVM cpsw slave1 is muxed with VIN, therefore switch cpsw to use
slave0 using pcf driver.
DRA72 has only one cpsw phy(phy#3). Hence, set phy_id to 3 for slave0,
in case of DRA72 EVM.
Signed-off-by: Vignesh R vigne...@ti.com
---
board/ti/dra7xx/evm.c | 13 +++--
1 file changed, 11
Hi,
This adds driver for pcf8575 in uboot. The driver supports basic
read and write operations on pcf gpio pins.
The first patch adds the driver, second patch and third patch
switches cpsw to use slave0 on DRA72 EVM.
Tested pcf driver on DRA72 EVM by probing pcf lines and cpsw by
runnning
On Tue, Mar 10, 2015 at 08:41:22PM +0530, Vignesh R wrote:
Enable pcf driver to control the pcf chip present
at address 0x21 on i2c1.
Signed-off-by: Vignesh R vigne...@ti.com
---
include/configs/dra7xx_evm.h | 4
1 file changed, 4 insertions(+)
diff --git
Bonjour Scott,
Le Tue, 10 Mar 2015 13:49:46 -0500, Scott Wood
scottw...@freescale.com a écrit :
On Tue, 2015-03-10 at 13:54 +0100, Albert ARIBAUD wrote:
Hi Scott,
Le Mon, 9 Mar 2015 18:51:03 -0500, Scott Wood scottw...@freescale.com
a écrit :
On Thu, 2015-03-05 at 07:46 +0100,
Hi
I have downloaded u-boot-arm-02251ee.tar.gz and built locally.
The resulting MLO and U-Boot cannot boot my TI J6 EVM.
I had a U-Boot SPL 2013.04 (Sep 24 2014 - 00:00:28) - U-boot/MLO pair working
with a device tree on the same EVM.
Any clues are appreciated. - thanks
Regards
Naveen
On Tue, Mar 10, 2015 at 07:20:04PM +, Korupol, Naveen (EXT) wrote:
Hi
I have downloaded u-boot-arm-02251ee.tar.gz and built locally.
The resulting MLO and U-Boot cannot boot my TI J6 EVM.
I had a U-Boot SPL 2013.04 (Sep 24 2014 - 00:00:28) - U-boot/MLO pair working
with a device
Hi
I have downloaded u-boot-arm-02251ee.tar.gz and built locally.
The resulting MLO and U-Boot cannot boot my TI J6 EVM.
I had a U-Boot SPL 2013.04 (Sep 24 2014 - 00:00:28) - U-boot/MLO pair working
with a device tree on the same EVM.
Any clues are appreciated. - thanks
Regards
Naveen
Please
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, March 10, 2015 11:29 PM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431;
Kushwaha Prabhakar-B32579
Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND
secure boot
On Tue, 2015-03-10 at 13:54 +0100, Albert ARIBAUD wrote:
Hi Scott,
Le Mon, 9 Mar 2015 18:51:03 -0500, Scott Wood scottw...@freescale.com
a écrit :
On Thu, 2015-03-05 at 07:46 +0100, Albert ARIBAUD (3ADEV) wrote:
+ while (left) {
+ if (read_single_page(dst, page) = 0) {
+
On Tue, 2015-03-10 at 13:27 -0500, Bansal Aneesh-B39320 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, March 10, 2015 11:29 PM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431;
Kushwaha Prabhakar-B32579
Subject:
On Tue, Mar 10, 2015 at 04:00:09PM +0530, Sekhar Nori wrote:
When Beagle X15 is connected to Gigabit switch, it takes
more time to finish auto-negotiation than on a 10/100 switch.
The default 4 second limit times-out more often than not. This is
observed when testing with a D-Link DGS-1008A
Hi Heiko,
On 10.03.2015 07:17, Heiko Schocher wrote:
Hello Stefan,
Am 09.03.2015 16:49, schrieb Stefan Roese:
Without this patch, the IMX watchdog will not be initialized. And
therefor
not active. This patch fixes this by calling hw_watchdog_init() also when
CONFIG_IMX_WATCHDOG is defined.
Before add CONFIG_SYS_MALLOC_F and CONFIG_SYS_MALLOC_F_LEN,
uboot will complains CPU: Temperature: Can't find sensor device.
This is because DM and DM_THERMAL are enabled, but SYS_MALLOC_F
is not configured.
After applying this patch, uboot can correctly detect the temperature.
U-Boot
This patch is to support reading temperature for mx6slevk board.
Signed-off-by: Peng Fan peng@freescale.com
---
configs/mx6slevk_defconfig| 4
configs/mx6slevk_spinor_defconfig | 4
include/configs/mx6slevk.h| 7 +++
3 files changed, 15 insertions(+)
diff --git
Without this patch, the IMX watchdog will not be initialized. And therefor
not active. This patch fixes this by calling hw_watchdog_init() also when
CONFIG_IMX_WATCHDOG is defined.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Simon Glass s...@chromium.org
Cc: Fabio Estevam
Commit f022d36e8a4517b2a9d25ff2d75bd2459d0c68b1 introduces
error register offset.
Change the char reserved3[59] to char reserved3[56].
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/mmc/fsl_esdhc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Albert – are you getting these emails? I know they’re bouncing from the list
(need to find a mailer that doesn’t use MIME64), but I haven’t heard back from
you for the last 2 PRs.
Should I send these to Tom Rini instead? Please let me know.
Tom
From: Tom Warren
From: Stephen Warren swar...@nvidia.com
This should make it more clear why there appear to be C pre-processor
symbols in the file that contain mixed case. They're really error
messages.
Suggested-by: Simon Glass s...@chromium.org
Signed-off-by: Stephen Warren swar...@nvidia.com
---
On Wed, Mar 4, 2015 at 12:35 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 3 March 2015 at 19:41, Joe Hershberger joe.hershber...@ni.com wrote:
Take a pass at plumbing errors through to the users of the network stack
Currently only the start() function errors will be returned from
On Wed, Mar 4, 2015 at 12:35 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 3 March 2015 at 19:41, Joe Hershberger joe.hershber...@ni.com wrote:
Stop forcing drivers to call net_process_received_packet() - formerly
called NetReceive(). Now the uclass will handle calling the driver for
Hi Joe,
On 10 March 2015 at 16:28, Joe Hershberger joe.hershber...@gmail.com wrote:
On Wed, Mar 4, 2015 at 12:35 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 3 March 2015 at 19:41, Joe Hershberger joe.hershber...@ni.com wrote:
Stop forcing drivers to call
1. Default environment will be used for secure boot flow
which can't be edited or saved.
2. Command for secure boot is predefined in the default
environment which will run on autoboot (and autoboot is
the only option allowed in case of secure boot) and it
looks like this:
#define
From: Ying Zhang b40...@freescale.com
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, March 05, 2015 10:38 PM
To: Bansal Aneesh-B39320
Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431
Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND
secure boot target for P3041
On Thu,
Le 28/02/2015 08:59, Minkyu Kang a écrit :
Joonyoung,
On 26/02/15 00:22, Guillaume GARDET wrote:
Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup
soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec
keyboard working again on Samsung Chromebook
On Tue, Mar 10, 2015 at 6:31 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 10 March 2015 at 16:28, Joe Hershberger joe.hershber...@gmail.com
wrote:
On Wed, Mar 4, 2015 at 12:35 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 3 March 2015 at 19:41, Joe Hershberger
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