On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote:
By default the legacy segments (Ah-Bh, Eh-Fh)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote:
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.
Hi Bin,
On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote:
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng bmeng...@gmail.com
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
the text base address. Since it is deprecated, just remove it and use
CONFIG_SYS_TEXT_BASE directly.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Kconfig
2015-04-28 12:45 GMT+02:00 Bin Meng bmeng...@gmail.com:
Hi Francesco,
On Tue, Apr 28, 2015 at 4:40 PM, Francesco Lucconi lucc...@gmail.com
wrote:
Here you have the 512 bytes of MBR within the Virtual Disk Image (VID) of
virtualbox. As you can notice there's not clearly the string Error!
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com
Increase max sizes for OOB, Page size and eccpos to
suit for Micron MT29F32G08 part
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
---
include/linux/mtd/mtd.h | 2 +-
include/linux/mtd/nand.h | 4 ++--
2 files
Added initial nand driver support for arasan nand flash
controller.This supports nand erase,nand read, nand write
This uses the hardware ECC for read and write operations
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
---
drivers/mtd/nand/Makefile |1 +
Hi Jagan,
I didn't get chance to look at the series. Could you give me some time till
next week as I am little busy this week.
Regards,
Siva
-Original Message-
From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
Sent: Monday, April 27, 2015 8:32 PM
To: u-boot@lists.denx.de; Siva
Hi Siva,
On 28 April 2015 at 18:21, Siva Durga Prasad Paladugu
siva.durga.palad...@xilinx.com wrote:
Hi Jagan,
I didn't get chance to look at the series. Could you give me some time till
next week as I am little busy this week.
No issues, If something that I send it for v2 I will let you
On 28 April 2015 at 00:24, Hans de Goede hdego...@redhat.com wrote:
Hi Simon,
Thanks for the reviews.
On 28-04-15 05:20, Simon Glass wrote:
Hi Hans,
On 26 April 2015 at 03:51, Hans de Goede hdego...@redhat.com wrote:
Now that all sunxi boards are using driver-model for gpio (*), we can
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Since all x86 boards have been converted to use DM_SPI and
DM_SPI_FLASH, move them to arch/Kconfig x86 section.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/Kconfig | 2 ++
arch/x86/Kconfig | 6 --
2 files
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Let arch/x86/Kconfig prompt board vendor first, then select
the board model under that vendor. This way arch/x86/Kconfig
only needs concern board vendor and leave the supported target
list to board/vendor/Kconfig.
Signed-off-by:
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
fix the indention of its help text.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig | 8
1 file changed, 4 insertions(+), 4
On 28 April 2015 at 04:37, Bin Meng bmeng...@gmail.com wrote:
It should be #ifdef instead of #if.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/lib/tables.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Simon Glass s...@chromium.org
On Tuesday, April 28, 2015 at 10:59:16 AM, Michal Simek wrote:
On 09/05/2014 08:46 AM, Siva Durga Prasad Paladugu wrote:
Update the ci_udc driver to support bulk transfer
and also added capability of having multiple dtds
if requested data is more thank 16K.
These changes are tested for
On Tuesday, April 28, 2015 at 09:12:09 AM, Ramneek Mehresh wrote:
Add support for DWC3 XHCI controller driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Applied all, thanks!
Best regards,
Marek Vasut
___
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On 26 April 2015 at 07:52, Bin Meng bmeng...@gmail.com wrote:
Hi Gabriel,
On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
The correct GPIOBASE address on the baytrail is 0x48
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Reviewed-by: Bin Meng
On 26 April 2015 at 07:54, Bin Meng bmeng...@gmail.com wrote:
On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau cont...@huau-gabriel.fr wrote:
There are 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau
On 26 April 2015 at 08:08, Bin Meng bmeng...@gmail.com wrote:
On Sat, Apr 25, 2015 at 11:13 PM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Update the
On 25 April 2015 at 14:18, Gabriel Huau cont...@huau-gabriel.fr wrote:
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
- Fix ordering of include header
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files
Hi Gabriel,
On 25 April 2015 at 14:17, Gabriel Huau cont...@huau-gabriel.fr wrote:
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes for v2:
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Move platform-specific options under in arch/x86/Kconfig forward right
after the board-specific options but before any architecture-specific
options. When it comes to the same Kconfig option, board-specific one
takes take the
Hi Francesco,
On Tue, Apr 28, 2015 at 4:40 PM, Francesco Lucconi lucc...@gmail.com wrote:
Here you have the 512 bytes of MBR within the Virtual Disk Image (VID) of
virtualbox. As you can notice there's not clearly the string Error!
mentioned on previous screenshot.
About MBR building to ease
On 24 April 2015 at 07:34, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 24-04-15 14:42, Simon Glass wrote:
Hi Hans,
On 23 April 2015 at 10:15, Simon Glass s...@chromium.org wrote:
Hi Hans,
On 23 April 2015 at 00:55, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 22-04-15
On Mon, Apr 27, 2015 at 02:52:49PM -0600, Simon Glass wrote:
Hi Tom,
On 25 April 2015 at 11:54, Tom Rini tr...@konsulko.com wrote:
On Sat, Apr 25, 2015 at 11:46:43AM -0600, Simon Glass wrote:
The descriptor provided with the FSP does not seem to work. Update the
instructions to use the
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Correct call to reset_cpu() which was missing a parameter!
- Tidy up reset calls to do the correct reset type
arch/x86/cpu/ivybridge/cpu.c
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/lib/fsp/fsp_common.c | 7 ---
It is useful to be able to keep track of the available CPUs in a multi-CPU
system. This uclass is mostly intended for use with SMP systems.
The uclass provides methods for getting basic information about each CPU.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Change header
Add a function to return the address of the Interrupt Descriptor Table.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/interrupts.c| 5 +
arch/x86/include/asm/interrupt.h | 2 ++
2 files changed, 7 insertions(+)
diff --git
Signed-off-by: Peter Howard phow...@gme.net.au
---
configs/omapl138_lcdk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 8f19721..4445c38 100644
--- a/configs/omapl138_lcdk_defconfig
+++
Some variants of the Gumstix Pepper board use DDR3 memory instead of
DDR2. This adds a machine variant to support these DDR3-based boards
which can be built as 'pepper_ddr3_defconfig' rather than the normal
'pepper_defconfig'.
Signed-off-by: Ash Charles ashchar...@gmail.com
---
On 19 April 2015 at 22:05, Simon Glass s...@chromium.org wrote:
The MRC image is incorrect, or at least this one now does not seem to
work. Fix it.
Signed-off-by: Simon Glass s...@chromium.org
---
doc/README.x86 | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-x86.
On Tue, Apr 28, 2015 at 04:25:44PM -0700, Ash Charles wrote:
Some variants of the Gumstix Pepper board use DDR3 memory instead of
DDR2. This adds a machine variant to support these DDR3-based boards
which can be built as 'pepper_ddr3_defconfig' rather than the normal
'pepper_defconfig'.
This driver supports multi-core init and sets up the CPU frequencies
correctly.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/baytrail/Makefile | 1 +
arch/x86/cpu/baytrail/cpu.c | 206 +++
We don't need to support really old x86 CPUs, so drop this code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/lapic.c | 20
arch/x86/include/asm/lapic.h | 7 ---
2 files changed, 12 insertions(+), 15 deletions(-)
diff
Since we do these sorts of operations a lot, it is useful to have a simpler
API, similar to clrsetbits_le32().
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/include/asm/msr.h | 19 +++
1 file changed, 19 insertions(+)
diff --git
Hi Tom,
There is actually an EEPROM on new boards that we'd like to use in the
future in order to detect that we should use DDR3 (and frankly,
everything will be DDR3 going forward). We still don't have
everything sorted in hardware and at the factories for programming the
eeprom though. This
When we start up additional CPUs we want them to use the same Global
Descriptor Table. Store the address of this in global_data so we can
reference it later.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/cpu.c
Most modern x86 CPUs include more than one CPU core. The OS normally requires
that these 'Application Processors' (APs) be brought up by the boot loader.
Add the required support to U-Boot to init additional APs.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
Add a subset of this header file from Linux 4.0 to support atomic operations
in U-Boot.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/include/asm/atomic.h | 115 ++
1 file changed,
This permits init of additional CPU cores after relocation and when driver
model is ready.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/cpu.c| 37 +
arch/x86/include/asm/cpu.h| 14 ++
Before adding one more function, create a separate header to help reduce
the size of common.h. Add the missing function comments and tidy up.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Use capitals for the header guard
- Change 'print' to 'Print' in comment
Add a function similar to print_size() that works for frequencies. It can
handle from Hz to GHz.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Correct bugs in number output
include/display_options.h | 11 +++
lib/display_options.c | 38
Try to make it a little clearer.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
common/board_f.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index
Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This
enables multi-core support in Linux.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/dts/minnowmax.dts | 20
configs/minnowmax_defconfig | 4
2 files changed,
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Rename CONFIG_SFI to CONFIG_GENERATE_SFI_TABLE and
This is annoying during development and serves no useful purpose since
warnings are clearly displayed now that we are using Kbuild. Remove this
option.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/config.mk | 2 +-
1
Add a simple command which provides access to a list of available CPUs along
with descriptions and basic information.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
common/Kconfig | 8
common/Makefile | 1 +
Provide access to this x86 instruction from C code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Remove unnecessary \t\n after mfence assembler instruction
arch/x86/include/asm/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/cpu.h
Add MSR numbers for the fixed MTRRs.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/include/asm/mtrr.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/mtrr.h
Some device tree nodes do not have compatible strings but do require
drivers. This is pretty rare, and somewhat unfortunate. Add a function
to permit creation of a driver for any device tree node.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/lists.c | 9
This printf() should not have made it into the code.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/x86/cpu/baytrail/valleyview.c
On 20 April 2015 at 07:07, Simon Glass s...@chromium.org wrote:
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.
Signed-off-by: Simon Glass s...@chromium.org
---
The following changes since commit 1733259d25015c28c47990ec11af99b3f62f811c:
Merge branch 'master' of git://git.denx.de/u-boot-video (2015-04-20 09:13:52
-0400)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/quark/quark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.
We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power
Dear Joe,
In message CANr=Z=YxsT-VOje5jA0k00BSxNROXBOPXMG-Q_8_7jAYN=f...@mail.gmail.com
you wrote:
I noticed you asked for a reference to the original hush code that is the
origin for U-Boot's adaptation. I couldn't find a reply to that question. I
also haven't been able to find anything
Hi Tom,
A few bug fixes.
The following changes since commit cc555bd4f40a652471df4a3621d45ee57df0ca11:
Merge branch 'master' of git://git.denx.de/u-boot-spi (2015-04-28
07:28:43 -0400)
are available in the git repository at:
http://git.denx.de/u-boot-dm.git
for you to fetch changes up to
On Wed, Apr 29, 2015 at 09:05:57AM +1000, Peter Howard wrote:
Signed-off-by: Peter Howard phow...@gme.net.au
---
configs/omapl138_lcdk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 8f19721..4445c38
This series adds a new CPU uclass which is intended to be useful on any
architecture. So far it has a very simple interface and a command to show
CPU details.
This series also introduces multi-core init for x86. It is implemented and
enabled on Minnowboard MAX, a single/dual-core Atom board. The
If regular NAND booting fails to find a valid uImage in the
kernel partition in NAND, try to boot using a zImage and dtb found
in a UBI volume in the rootfs partition. This is the NAND analog
of mmc zImage booting for device-tree based kernels.
Signed-off-by: Ash Charles ashchar...@gmail.com
This series collects several board-enablement fixes for the Gumstix
Overo as well as switching to BCH8 for NAND ECC, updating the UBI
boot sequence for DTB-based boots, and correcting a RAM configuration
for Overo COMs of Revision 0.
This series follows after the series previously submitted:
From: Arun Bharadwaj a...@gumstix.com
Signed-off-by: Arun Bharadwaj a...@gumstix.com
Signed-off-by: Ash Charles ashchar...@gmail.com
---
board/overo/overo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 2845e7c..3f14b03 100644
---
From: Arun Bharadwaj a...@gumstix.com
Overo boards with board revision 0 use a 256MB RAM + 256MB NAND chip.
For an unknown reason, these boards fail to boot a 3.17.8 kernel based
on the RAM size configuration in u-boot. As a workaround, fake out the
RAM setting in u-boot (discussion [1]).
[1]
The Gumstix Arbor43C expansion board [1] uses a customized device tree
file. When this expansion board is detected, load this file.
[1] https://store.gumstix.com/index.php/products/635/
Signed-off-by: Ash Charles ashchar...@gmail.com
---
board/overo/overo.c | 1 +
1 file changed, 1
Signed-off-by: Ash Charles ashchar...@gmail.com
---
board/overo/overo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 3f14b03..d5ac1ad 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -193,6 +193,7 @@ int misc_init_r(void)
Overo COMs have NAND flash that requires 4-bit ECC or better except for
the first sector which can use 1-bit ECC. The boot ROM expects to load
a payload from NAND written using 1-bit hardware-based ECC. In short,
write SPL to NAND something like this (4 times for redundancy):
# nandecc hw
#
The code is split up into spl.c, overo.c and common.c (which
has the code common to both)
Signed-off-by: Arun Bharadwaj a...@gumstix.com
---
board/overo/Makefile | 6 +-
board/overo/common.c | 355 +++
board/overo/overo.c | 117 +
This is the v2 of the two-patch series. v1 can be found here:
http://lists.denx.de/pipermail/u-boot/2015-April/211651.html
The only change in this version is that the earlier version missed printing
the board revision, so fixed that.
Arun Bharadwaj (2):
This separates the SPL-specific code
Hi Bin,
On 28 April 2015 at 02:16, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass s...@chromium.org wrote:
Add a function to return the address of the Interrupt Descriptor Table.
Signed-off-by: Simon Glass s...@chromium.org
---
Hi Bin,
On 26 April 2015 at 22:58, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass s...@chromium.org wrote:
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.
Signed-off-by: Simon Glass s...@chromium.org
---
Hi Bin,
On 26 April 2015 at 22:56, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass s...@chromium.org wrote:
The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.
We can use port 0xcf9 to initiate reset
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR
This could happen if we are being chainloaded by Coreboot with LPAE
enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
arch/arm/lib/cache-cp15.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/lib/cache-cp15.c
I am new to this project. But I am so interested with it and I want to dive
into it. Where should I start ?
--
This is my life,but world of us~~
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
On 27 April 2015 at 08:56, haikun.w...@freescale.com
haikun.w...@freescale.com wrote:
On 4/24/2015 11:55 PM, Simon Glass wrote:
Hi Haikun,
On 24 April 2015 at 07:22, Haikun Wang haikun.w...@freescale.com wrote:
Atmel DataFlash chips have commands different from common spi
flash commands.
Hi,
On 24 April 2015 at 22:33, Simon Glass s...@chromium.org wrote:
These functions now rely on uclass_find_first/next_device() and assume that
they will either return failure (-ve error code) or a device. In fact,
coming to the end of a list is not considered failure and they return 0
in
This is because the gd pointer is not set early enough anymore,
such that the i2c_set_bus_num in get_board_revision can safely
execute. This results in a console hang at SPL and the boot does
not proceed.
This piece of code is anyway necessary only for really old Overo
boards with revision
On Mon, Apr 27, 2015 at 11:30:43PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
There are users of Cuboxi and Hummingboard that use these boards without
connecting them to a USB/serial adapter.
Allow such usage by allowing the HDMI port to act as stdout and
On Mon, Apr 27, 2015 at 11:30:44PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Let Solidrun's logo appear on Cuboxi and Hummingboard by default.
Signed-off-by: Rabeeh Khoury rab...@solid-run.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
On Mon, Apr 27, 2015 at 11:30:41PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Add HDMI output using PLL5 as the source for the IPU DI clocks,
and accurate VESA timings.
These settings are based on the patch from Soeren Moch sm...@web.de
submitted for the
On Mon, Apr 27, 2015 at 11:30:42PM -0300, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Enable USB Host1 port.
Signed-off-by: Rabeeh Khoury rab...@solid-run.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
[snip]
diff --git a/include/configs/mx6cuboxi.h
Hi Tom,
please pull from u-boot-imx, thanks !
The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
Prepare v2015.04 (2015-04-13 10:53:03 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-imx.git master
for you to fetch changes up to
On 28 April 2015 at 08:04, Simon Glass s...@chromium.org wrote:
On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote:
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final
On 28 April 2015 at 08:05, Simon Glass s...@chromium.org wrote:
On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote:
By default the legacy segments (Ah-Bh, Eh-Fh)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F
The MX6 has OTP bits specifying the processor speed grade as well as
temperature grade.
This series adds functions to return this information as well as adds the
details to the CPU info displayed.
Additionally we use the temperature grade to replace the hard-coded limits
in imx_thermal.c
I
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
(OCOTP_CFG3[17:16]).
Display this value to make it clear the difference regarding the CPU speed
currently running at vs the max speed allowed per grade. Note that the power
on CPU speed is determined by OCOTP_CFG4[18].
I
On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam feste...@gmail.com wrote:
Hi Tom,
On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini tr...@konsulko.com wrote:
Since we have FEC do we really need to add ASIX as well? Also, what
I can remove it if needed. Just kept the same as done in the Solidrun's
On 28 April 2015 at 08:12, Simon Glass s...@chromium.org wrote:
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
the text base address. Since it is deprecated, just remove it and use
CONFIG_SYS_TEXT_BASE
On 28 April 2015 at 08:12, Simon Glass s...@chromium.org wrote:
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
fix the indention of its help text.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
On Fri, Apr 24, 2015 at 12:20:30PM +0200, Daniel Schwierzeck wrote:
The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71:
Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23
14:56:47 -0400)
are available in the git repository at:
On Tue, Apr 28, 2015 at 01:47:35PM +0530, Jagannadha Sutradharudu Teki wrote:
Hi Tom,
Please pick this PR.
thanks!
Jagan.
The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06:
serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400)
are available
On Thu, Apr 23, 2015 at 07:17:51PM -0700, York Sun wrote:
Tom,
I am having trouble cloning git repositories. I hope this pull request was
generated correctly. I saw fatal: read error: Connection reset by peer when
creating this pull request.
The following changes since commit
On Fri, Apr 24, 2015 at 09:37:02AM -0600, Simon Glass wrote:
Hi Tom,
The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71:
Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23
14:56:47 -0400)
are available in the git repository at:
Hi Tom,
On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini tr...@konsulko.com wrote:
Since we have FEC do we really need to add ASIX as well? Also, what
I can remove it if needed. Just kept the same as done in the Solidrun's U-boot.
devices did you test this with for USB? I grabbed a Sandisk USB
On 28 April 2015 at 07:53, Simon Glass s...@chromium.org wrote:
On 26 April 2015 at 07:52, Bin Meng bmeng...@gmail.com wrote:
Hi Gabriel,
On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
The correct GPIOBASE address on the baytrail is 0x48
Signed-off-by:
On 28 April 2015 at 07:53, Simon Glass s...@chromium.org wrote:
On 26 April 2015 at 07:54, Bin Meng bmeng...@gmail.com wrote:
On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
There are 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS
On 28 April 2015 at 07:59, Simon Glass s...@chromium.org wrote:
On 26 April 2015 at 08:08, Bin Meng bmeng...@gmail.com wrote:
On Sat, Apr 25, 2015 at 11:13 PM, Gabriel Huau cont...@huau-gabriel.fr
wrote:
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau
On 28 April 2015 at 08:12, Simon Glass s...@chromium.org wrote:
On 27 April 2015 at 09:22, Bin Meng bmeng...@gmail.com wrote:
Move platform-specific options under in arch/x86/Kconfig forward right
after the board-specific options but before any architecture-specific
options. When it comes to
On 28 April 2015 at 08:13, Simon Glass s...@chromium.org wrote:
On 28 April 2015 at 04:37, Bin Meng bmeng...@gmail.com wrote:
It should be #ifdef instead of #if.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/lib/tables.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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