+Wolfgang, +Tom,
On Thu, Jun 4, 2015 at 8:09 PM, Bin Meng bmeng...@gmail.com wrote:
New microcode for BayTrail-I D0 stepping.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Looks that this patch is still pending on mailing list admin's
approval as its size exceeds the 100KB limit thus not
Hi Joe,
2015-05-30 6:23 GMT+09:00 Joe Hershberger joe.hershber...@ni.com:
This option allows the 'make *_defconfig' step to run against a former
repo state, while the savedefconfig step runs against the current repo
state. This is convenient for the case where something in the Kconfig
has
-Original Message-
From: Nikhil Badola [mailto:nikhil.bad...@freescale.com]
Sent: Tuesday, May 12, 2015 2:58 PM
To: u-boot@lists.denx.de
Cc: Badola Nikhil-B46172
Subject: [PATCH] drivers:usb:fsl: Return if USB_MAX_CONTROLLER_COUNT
is incorrect
Return if USB_MAX_CONTROLLER_COUNT
Hi Simon,
On Fri, Jun 5, 2015 at 2:31 AM, Simon Glass s...@chromium.org wrote:
Hi,
On 4 June 2015 at 10:27, Andrew Bradford and...@bradfordembedded.com wrote:
Hi Bin,
On 06/04 22:21, Bin Meng wrote:
Hi Simon,
On Thu, Jun 4, 2015 at 8:12 PM, Bin Meng bmeng...@gmail.com wrote:
This
Hi Joe,
2015-06-05 2:54 GMT+09:00 Joe Hershberger joe.hershber...@gmail.com:
Hi Masahiro-san,
On Thu, Jun 4, 2015 at 12:29 PM, Masahiro Yamada
yamada.masah...@socionext.com wrote:
Hi.
2015-06-04 7:55 GMT+09:00 Joe Hershberger joe.hershber...@gmail.com:
On Wed, Jun 3, 2015 at 5:26 PM,
From: Rob Herring r...@kernel.org
Currently, u-boot will always fixup the DT memory node on ARM. If the dtb
has correct memory information, then we don't want or need u-boot to touch
the memory node. Allow platforms to skip this by not filling in dram bank
information.
Signed-off-by: Rob Herring
Hi Tom,
On 12 May 2015 at 14:55, Simon Glass s...@chromium.org wrote:
With driver model SPL support in place the remaining driver difference
between U-Boot proper and SPL is that SPL does not support device tree.
This series adds this support, using a Rockchip board as an example.
I'd like to
Fix clamp macro redefined warning, and clamp type check warnings.
Signed-off-by: Angelo Dureghello ang...@sysam.it
---
drivers/spi/cf_qspi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c
index 834c5bd..c4bafe0 100644
---
From: Mark Langsdorf mark.langsd...@gmail.com
Enable full 48-bit LBA48 data reads by passing the upper word of the
LBA block pointer in bytes 9 and 10 of the FIS.
This allows uboot to load data from any arbitrary sector on a drive
with 2 or more TB of available data connected to an AHCI
From: Mark Langsdorf mark.langsd...@gmail.com
Signed-off-by: Mark Langsdorf mark.langsd...@gmail.com
Signed-off-by: Andre Przywara o...@andrep.de
---
common/cmd_scsi.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index
From: Mark Langsdorf mark.langsd...@gmail.com
The Calxeda Midway part has A15 cores, which do not have the Highbank
A9's SCU used there for resetting the chip.
Add code to distinguish between the A9 and the A15 and invoke the
appropriate register writes to support the newer part.
Andre: rework
From: Mark Langsdorf mark.langsd...@gmail.com
The Calxeda highbank SOC needs a custom sequence to bring up SATA links,
so override ahci_link_up with custom function to handle combophy setup.
Signed-off-by: Mark Langsdorf mark.langsd...@gmail.com
Signed-off-by: Richard Gibbs
Signed-off-by: Rob
From: Mark Langsdorf mark.langsd...@gmail.com
The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can
From: Rob Herring r...@kernel.org
On the highbank platform the SoC's management controller firmware
will probe the DRAM modules and populates the initial device tree with
the correct values. Therefore the memory sizes in are already correct,
so remove U-Boot's DRAM bank setup so the memory node
From: Rob Herring r...@kernel.org
Andre: assign names to the magic values
Signed-off-by: Rob Herring r...@kernel.org
Signed-off-by: Andre Przywara o...@andrep.de
---
board/highbank/highbank.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/board/highbank/highbank.c
This series aims to upstream fixes that have been in the Calxeda
firmware version of U-Boot for ages.
The first two patches fix reset, both for Highbank and Midway.
Patches 3-5 add support for larger hard disks, so U-Boot can now
access sectors from beyond 2 TB on larger disks.
Patch 6 and 7 teach
Hi.
2015-06-04 7:55 GMT+09:00 Joe Hershberger joe.hershber...@gmail.com:
On Wed, Jun 3, 2015 at 5:26 PM, Tom Rini tr...@konsulko.com wrote:
On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe Hershberger wrote:
Hi Tom,
On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini tr...@konsulko.com wrote:
On Wed,
Hi Masahiro-san,
On Thu, Jun 4, 2015 at 12:29 PM, Masahiro Yamada
yamada.masah...@socionext.com wrote:
Hi.
2015-06-04 7:55 GMT+09:00 Joe Hershberger joe.hershber...@gmail.com:
On Wed, Jun 3, 2015 at 5:26 PM, Tom Rini tr...@konsulko.com wrote:
On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe
Hi,
On 4 June 2015 at 10:27, Andrew Bradford and...@bradfordembedded.com wrote:
Hi Bin,
On 06/04 22:21, Bin Meng wrote:
Hi Simon,
On Thu, Jun 4, 2015 at 8:12 PM, Bin Meng bmeng...@gmail.com wrote:
This is a temparory hacking for testing U-Boot on a newer version
MinnowMax board.
Hi.
Sorry for my late reply.
2015-06-04 17:07 GMT+09:00 Lars Poeschel poesc...@lemonage.de:
On Wed, Jun 03, 2015 at 11:20:25AM -0400, Tom Rini wrote:
On Wed, Jun 03, 2015 at 04:36:06PM +0200, Lars Poeschel wrote:
On Tue, Jun 02, 2015 at 10:34:34AM -0400, Tom Rini wrote:
On Mon, Jun 01,
Sorry, I've been busy with T210 stuff. I'll try to take a look at it before the
EOW.
IIRC, there was some push-back from Stephen on boot scripts, etc. Have these
concerns all been addressed? Have you gotten Acks?
Tom
-Original Message-
From: s...@google.com [mailto:s...@google.com]
Hi Tom,
On 4 June 2015 at 09:42, Tom Warren twar...@nvidia.com wrote:
Sorry, I've been busy with T210 stuff. I'll try to take a look at it before
the EOW.
Great to see progress on T210.
IIRC, there was some push-back from Stephen on boot scripts, etc. Have these
concerns all been
I have seen btrfs patches for u-boot flying around a year ago or so then
it went silent. Is there any efforts ongoing to add btrfs support to u-boot?
Jocke
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hi Bin,
After applying both the patches, I am able to get the u-boot prompt
with u-boot.rom .
Thanks for these wonderful patches.
This is good news! I believe you can continue your work for the ACPI
support now :)
Sure. Thanks a lot for making this possible.
Regards,
Saket Sinha
Hi Bin,
On 06/04 22:21, Bin Meng wrote:
Hi Simon,
On Thu, Jun 4, 2015 at 8:12 PM, Bin Meng bmeng...@gmail.com wrote:
This is a temparory hacking for testing U-Boot on a newer version
MinnowMax board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/minnowmax.dts | 2
Simon,
Tried applying your patchset. Two or three had minor 'git am' conflicts that
were easy to resolve with 'patch', but #11 (tegra: Allow board-specific init)
conflicts with Mashiro's move of board.c to board2.c in mach-tegra:
Author: Masahiro Yamada yamada.masah...@socionext.com
Date:
From: Markus Niebel markus.nie...@tq-group.com
This series extends the Kconfig options for TQMa6 to
enable removal of CONFIG_SYS_EXTRA_OPTIONS for this boards.
To enable env device / boot device configuration the first patch
includes the Kconfig generated header in the board configuration
Hi Simon,
On Thu, Jun 4, 2015 at 8:12 PM, Bin Meng bmeng...@gmail.com wrote:
This is a temparory hacking for testing U-Boot on a newer version
MinnowMax board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/minnowmax.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 4 June 2015 at 02:47, Simon Glass s...@chromium.org wrote:
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree
On 12 May 2015 at 00:18, Gabriel Huau cont...@huau-gabriel.fr wrote:
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
Acked-by: Simon Glass s...@chromium.org
---
Changes in v3:
- Rebase to the origin/master
Changes in v2:
- Fix ordering of include header
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass
On 4 June 2015 at 02:47, Simon Glass s...@chromium.org wrote:
On 3 June 2015 at 18:15, Bin Meng bmeng...@gmail.com wrote:
On Thu, Jun 4, 2015 at 12:37 AM, and...@bradfordembedded.com wrote:
From: Andrew Bradford andrew.bradf...@kodakalaris.com
Baytrail physically maps the first 2 GB of SDRAM
On 4 June 2015 at 03:38, Simon Glass s...@chromium.org wrote:
Hi Masahiro,
On 29 May 2015 at 06:57, Masahiro Yamada yamada.masah...@socionext.com
wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
I also noticed British English spelling standardise and behaviour,
but
On 25 May 2015 at 23:27, Gabriel Huau cont...@huau-gabriel.fr wrote:
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Changes in v4:
- Rebase
Hi Saket,
On Thu, Jun 4, 2015 at 10:05 PM, Saket Sinha saket.sinh...@gmail.com wrote:
Hi Bin,
I've created two patches to include a D0 stepping microcode for
BayTrail-I. The microcode was generated from the microcode header in
the coreboot source tree.
The first patch is waiting for the
On 4 June 2015 at 02:47, Simon Glass s...@chromium.org wrote:
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create
Hi Tom,
On 13 May 2015 at 07:45, Simon Glass s...@chromium.org wrote:
This series expands Nyan-big support:
- Enable Chrome OS EC, so that the keyboard works
- Add some extra clock and pre-kernel init required for reliable operation
- Add Chrome OS environment variables, including 'run
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Drop v1 patches already applied
- Add asm/io.h inclusion
On 4 June 2015 at 03:03, Simon Glass s...@chromium.org wrote:
On 31 May 2015 at 00:57, Bin Meng bmeng...@gmail.com wrote:
We should ignore those regions whose size is negative. These are
typically optional and unused regions (like GbE and platform data).
Signed-off-by: Bin Meng
On 4 June 2015 at 02:47, Simon Glass s...@chromium.org wrote:
On 1 June 2015 at 07:07, Bin Meng bmeng...@gmail.com wrote:
FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig | 1 +
1 file changed, 1 insertion(+)
From: Markus Niebel markus.nie...@tq-group.com
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
Changes for v2:
- regenerate defconfigs
board/tqc/tqma6/Kconfig | 19 +++
configs/tqma6q_mba6_mmc_defconfig | 2 +-
configs/tqma6q_mba6_spi_defconfig | 3 ++-
From: Markus Niebel markus.nie...@tq-group.com
this is needed later to have Kconfig generated
stuff as define.
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
include/configs/tqma6.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/tqma6.h
From: Markus Niebel markus.nie...@tq-group.com
Now that we have the Kconfig based CPU type selection,
use this to fill the IMX_CONFIG automatically
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
Changes for v2:
- regenerate defconfigs
board/tqc/tqma6/Kconfig | 4
From: Markus Niebel markus.nie...@tq-group.com
This is the first patch to remove the
CONFIG_SYS_EXTRA_OPTIONS.
This patch implements CPU type selection from Kconfig.
Further Kconfig stuff is added later.
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
Changes in v2:
- regenerate
From: Markus Niebel markus.nie...@tq-group.com
this finally removes the need for extra settings in
defconfig
Signed-off-by: Markus Niebel markus.nie...@tq-group.com
---
Changes for v2:
- add default for new choice
- regenerate defconfigs
board/tqc/tqma6/Kconfig | 14 ++
Hi Bin,
I've created two patches to include a D0 stepping microcode for
BayTrail-I. The microcode was generated from the microcode header in
the coreboot source tree.
The first patch is waiting for the list moderator's approval as it
exceeds the mailing list size. The second patch is at
Hi,
The genboardsconfig.py script reports a growing list of warnings:
WARNING: no status info for 'axs103'
WARNING: no maintainers for 'axs103'
WARNING: no status info for 'at91sam9g20ek_2mmc'
WARNING: no maintainers for 'at91sam9g20ek_2mmc'
WARNING: no status info for 'at91sam9rlek_mmc'
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to add Kconfig options to be used by arch/x86/cpu/config.mk
arch/x86/Kconfig | 15
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is
On 06/04 18:28, Bin Meng wrote:
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- New patch to add Kconfig options to be used by arch/x86/cpu/config.mk
On 06/04 18:28, Bin Meng wrote:
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the
On 06/04 18:28, Bin Meng wrote:
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move
On Wed, Jun 03, 2015 at 11:20:25AM -0400, Tom Rini wrote:
On Wed, Jun 03, 2015 at 04:36:06PM +0200, Lars Poeschel wrote:
On Tue, Jun 02, 2015 at 10:34:34AM -0400, Tom Rini wrote:
On Mon, Jun 01, 2015 at 05:09:11PM +0200, poesc...@lemonage.de wrote:
From: Lars Poeschel
From: Lars Poeschel poesc...@lemonage.de
This add a Kconfig entry that allows to set the board revision in
menuconfig. So the deprecated CONFIG_SYS_EXTRA_OPTIONS is no longer
needed for this boad.
Signed-off-by: Lars Poeschel poesc...@lemonage.de
---
arch/arm/Kconfig | 19
Add support for Lightwriter SL50 series board, a small, robust and portable
Voice Output Communication Aids (VOCA) designed to meet the particular and
changing needs of people with speech loss resulting from a wide range of
acquired, progressive and congenital conditions.
Signed-off-by: Enric
This patch series adds support for SL50 board based on TI AM335x SoC.
Changes since v2:
- Rebased with current mainline.
- Keep the TI copyright header on some files.
- Add SPDX tags instead the full verbage.
- Set default fdtfile to am335x-sl50.dtb (instead uses am33xx-sl50.dtb)
Changes
Hi Bin,
On 1 June 2015 at 06:31, Bin Meng bmeng...@gmail.com wrote:
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree u-boot,no-apm-finalize under /config node if we don't want
to do that.
On 1 June 2015 at 07:07, Bin Meng bmeng...@gmail.com wrote:
FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig | 1 +
1 file changed, 1 insertion(+)
Acked-by: Simon Glass s...@chromium.org
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the
On 31 May 2015 at 00:57, Bin Meng bmeng...@gmail.com wrote:
We should ignore those regions whose size is negative. These are
typically optional and unused regions (like GbE and platform data).
Signed-off-by: Bin Meng bmeng...@gmail.com
---
tools/ifdtool.c | 2 +-
1 file changed, 1
Hi Simon,
On Thu, Jun 4, 2015 at 4:59 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 1 June 2015 at 06:31, Bin Meng bmeng...@gmail.com wrote:
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the
Hi Bin,
On 2 June 2015 at 19:20, Bin Meng bmeng...@gmail.com wrote:
The following error is observed on QEMU x86.
= print ipaddr
ipaddr=192.168.178.66
= ping 192.168.178.1
*** ERROR: `ipaddr' not set
ping failed; host 192.168.178.1 is not alive
The issue was introduced in commit fd30563.
On 3 June 2015 at 18:15, Bin Meng bmeng...@gmail.com wrote:
On Thu, Jun 4, 2015 at 12:37 AM, and...@bradfordembedded.com wrote:
From: Andrew Bradford andrew.bradf...@kodakalaris.com
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF
and additional SDRAM is mapped from
Hi Masahiro,
On 29 May 2015 at 06:57, Masahiro Yamada yamada.masah...@socionext.com wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
---
I also noticed British English spelling standardise and behaviour,
but I kept them.
I am not sure if it is justified to fix them...
Hi Gabriel,
On 25 May 2015 at 23:30, gabriel huau cont...@huau-gabriel.fr wrote:
Hi Simon,
I just submitted a new version of the patch, actually, when I tried to use
the GPIO on the header I saw a typo in the code.
To test it, you have to define these nodes in the device tree (should be
Hi Gabriel,
On 26 May 2015 at 08:41, Gabriel Huau cont...@huau-gabriel.fr wrote:
Hi Andy,
On 05/26/2015 01:01 AM, Andy Pont wrote:
Hi Gabriel,
soc_gpio_s5_0@0 {
gpio-offset = 0x80 0;
pad-offset = 0x1d0;
mode-gpio;
Hi,
On 04-06-15 00:55, Joe Hershberger wrote:
On Wed, Jun 3, 2015 at 5:26 PM, Tom Rini tr...@konsulko.com wrote:
On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe Hershberger wrote:
Hi Tom,
On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini tr...@konsulko.com wrote:
On Wed, Jun 03, 2015 at 08:12:16PM
Adding the mux data, manual and virtual mode
settings for BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
board/ti/beagle_x15/mux_data.h |
Enable IO delay recalibration sequence.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
board/ti/beagle_x15/board.c | 14 +++---
include/configs/beagle_x15.h | 4
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git
From: Nishanth Menon n...@ti.com
Adding the mux data, manual and virtual mode
settings for DRA7-evm.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
In addition to the regular mux configuration, certain pins of DRA7
require to have virtual mode also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.
Provide easy to use macro to do the same.
For
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This IODelay module has it's own register space that is
independent of the control module.
It is advocated strongly in TI's official documentation considering
Enabling IO delay recalibration sequence for DRA7 EVM.
UART and I2C are configured before IO delay recalibration sequence
as these are used earlier and safe to use.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
board/ti/dra7xx/evm.c| 14
Now all manual mode configurations are done as part of
IO delay recalibration sequence, remove the hack done for
CPSW.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h | 25 -
board/ti/dra7xx/evm.c | 66
In addition to the regular mux configuration, certain pins of DRA7
require to have manual mode also programmed, when predefined
delay characteristics cannot be used for the interface.
struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along
SoCs such as DRA7 family from Texas Instruments include a highly
configurable hardware block called the IOdelay block. This block
allows very specific custom fine tuning for electrical characteristics
of IO pins that are necessary for functionality and device lifetime
requirements.
IODelay module
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 9
This is a temparory hacking for testing U-Boot on a newer version
MinnowMax board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/minnowmax.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index
Hi Saket,
On Thu, Jun 4, 2015 at 11:23 AM, Simon Glass s...@chromium.org wrote:
Hi John,
On 3 June 2015 at 18:13, Bin Meng bmeng...@gmail.com wrote:
Hi,
On Thu, Jun 4, 2015 at 5:44 AM, John Hawley john.haw...@intel.com wrote:
Ok some more data points. I tested with the FSP3 Gold that
Hello,
I can see the command 'mmc erase blk# cnt' fails with a DAT0 timeout on iMX6
boards when run over the eMMC.
= mmc dev 2
= mmc erase 4000 1000
MMC erase: dev # 2, block # 16384, count 4096 ... Timeout waiting for
DAT0 to go high!
mmc erase failed
0 blocks erase: ERROR
I reproduced it
Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
84 matches
Mail list logo
