Hi Liviu,
You can add my Tested-by or Reviewed-by to this patch at your preference.
Thanks,
Ryan.
On 16 October 2015 at 15:41, Liviu Dudau wrote:
> Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
> Declare a secondary memory bank and set the sizes
Hi Liviu,
These patches work well for me, so at the very least, you can add my
Test-by for both:
Tested-by: Ryan Harkin
But...
I ran checkpatch.pl across your patches and this one throws a few trivial
warnings, mostly about 80 character lines and a few like this:
From: Fabio Estevam
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.
Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.
From: Fabio Estevam
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.
Signed-off-by: Fabio Estevam
---
Changes since v7:
- None
arch/arm/mach-mvebu/mbus.c | 2 +-
drivers/mtd/mtdcore.c | 2 +-
Tom Rini writes:
> On Fri, Oct 16, 2015 at 03:09:02PM -0500, Felipe Balbi wrote:
>> Felipe Balbi writes:
>> > Fix the following build break:
>> >
>> > drivers/usb/host/xhci-omap.c:35:5: error: ‘board_usb_init’ aliased to
>> > external symbol ‘__board_usb_init’
Felipe Balbi writes:
> Fix the following build break:
>
> drivers/usb/host/xhci-omap.c:35:5: error: ‘board_usb_init’ aliased to
> external symbol ‘__board_usb_init’
> int board_usb_init(int index, enum usb_init_type init)
> ^
>
> Signed-off-by: Felipe Balbi
Felipe Balbi writes:
> fix the following build warnings:
>
> drivers/usb/dwc3/core.c: In function ‘dwc3_uboot_init’:
> drivers/usb/dwc3/core.c:625:6: warning: ‘dev’ is used uninitialized in this
> function [-Wuninitialized]
> mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK,
On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov
wrote:
> On some systems, UART initialization is performed before running U-Boot.
> This commit allows to skip UART re-initializaion on those systems
>
> Signed-off-by: Sergey Temerkhanov
>
From: Fabio Estevam
Add the SPI NOR protection mechanism from the kernel.
This code is based on the work from Brian Norris
From: Fabio Estevam
Use the log2 and fls64 header files directly from the kernel.
Signed-off-by: Fabio Estevam
---
Changes since v7:
- None
include/asm-generic/bitops/fls64.h | 36 +++
include/linux/bitops.h | 9 ++
On Fri, Oct 16, 2015 at 03:09:02PM -0500, Felipe Balbi wrote:
> Felipe Balbi writes:
> > Fix the following build break:
> >
> > drivers/usb/host/xhci-omap.c:35:5: error: ‘board_usb_init’ aliased to
> > external symbol ‘__board_usb_init’
> > int board_usb_init(int index, enum
On 10/15/2015 6:32 PM, Gong Qianyu wrote:
From: Mingkai Hu
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, October 15, 2015 10:20 PM
> To: Bansal Aneesh-B39320 ; u-boot@lists.denx.de
> Cc: Wood Scott-B07421 ; Gupta Ruchika-R66431
>
> -Original Message-
> From: Kushwaha Prabhakar-B32579
> Sent: Friday, October 16, 2015 12:08 PM
> To: Gong Qianyu-B52263; u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Wang Huan-B18965;
On Thu, 2015-10-15 at 17:58 -0400, Tom Rini wrote:
> On Thu, Oct 15, 2015 at 03:56:09PM +, Joakim Tjernlund wrote:
> > On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
> > > On Thu, 2015-10-01 at 08:57 +, Joakim Tjernlund wrote:
> > > > On Wed, 2015-09-30 at 21:35 +0200, Marek
Hi Stefan,
On 16/10/2015 08:32, Stefan Agner wrote:
> Hi Stefano,
>
> This patch did not make it into the git tree, however my patch which
> followed that one (and which fixed the same issue on colibri_vf only),
> did make it...
>
> Sorry, my comment below was somewhat confusing. I descided
The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
endianness before the job is submitted.
2. The read/write of physical addresses
Hello Ezequiel,
Am 09.10.2015 um 14:30 schrieb Heiko Schocher:
Hello Ezequiel,
Am 09.10.2015 um 06:01 schrieb Heiko Schocher:
Hello Ezequiel,
Am 08.10.2015 um 17:54 schrieb Ezequiel Garcia:
Heiko,
On 8 October 2015 at 11:54, Heiko Schocher wrote:
[..]
Currently I have a
Hi Stefano,
This patch did not make it into the git tree, however my patch which
followed that one (and which fixed the same issue on colibri_vf only),
did make it...
Sorry, my comment below was somewhat confusing. I descided afterwards to
just send a seperate one for colibri_vf.
Could you also
Hello,
The following changes since commit 1275456d31cc130738775dca19b0a2ab1374cfbd:
Merge branch 'master' of git://git.denx.de/u-boot-arm (2015-10-15 17:45:39
-0400)
are available in the git repository at:
git://git.denx.de/u-boot-arm master
for you to fetch changes up to
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian
---
v3:
-
Convert dma_alloc_coherent to use memalign.
Signed-off-by: Thomas Chou
---
v2
use memalign.
v3
check memalign() return for out of memory.
v4
use malloc_cache_aligned().
v5
use invalidate_dcache_range() as Marek suggested.
v6
defer assignment of handle as Marek
On 10/15/2015 6:32 PM, Gong Qianyu wrote:
From: Mingkai Hu
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang
Signed-off-by: Hou Zhiqiang
Hi Tom,
there is still a missing bug fix to be merged for the release:
http://patchwork.ozlabs.org/patch/528422/
Same fix were already merged for the other vf610 board (colibri_vf).
Can you pick it ? Anyway, I have also merged it into u-boot-imx if you
prefer to pull from my tree.
Dear Tom,
The following changes since commit f861f51c4673d35908e4e330a86c81d7d909b51c:
ls102xa: Fix reset hang (2015-10-12 12:56:32 -0400)
are available in the git repository at:
http://git.denx.de/u-boot-samsung
for you to fetch changes up to 2308ea7c6fe003f699f4648d4ac3bb030fdc64d0:
Hi Tom,
there is still a missing bug fix to be merged for the release:
http://patchwork.ozlabs.org/patch/528422/
Same fix were already merged for the other vf610 board (colibri_vf).
Can you pick it ? Anyway, I have also merged it into u-boot-imx if you
prefer to pull from my tree.
>From f22064087684b04d6d6ff105a4766a0902d361a8 Mon Sep 17 00:00:00 2001
From: Chin Liang See
Date: Thu, 15 Oct 2015 13:56:45 +0800
Subject: [PATCH 1/5] spi: cadence_qspi: Ensure spi_calibration is run
when
sclk change
Ensuring spi_calibration is run when there is a change of
>From 4a91b5a380e7d3178d4378df79224442c79278bb Mon Sep 17 00:00:00 2001
From: Chin Liang See
Date: Fri, 16 Oct 2015 16:35:10 +0800
Subject: [PATCH v4 2/5] spi: cadence_qspi: Fix fdt read of
spi-max-frequency
Fix the fdt read for spi-max-frequency as it's contained
in the child
>From 0f8976e33533826d0df360c0ce01a5efd428b663 Mon Sep 17 00:00:00 2001
From: Chin Liang See
Date: Thu, 15 Oct 2015 13:57:27 +0800
Subject: [PATCH v4 3/5] spi: cadence_qspi: Ensure check for max
frequency in
place
Ensure the intended SCLK frequency not exceeding the maximum
Hello Ladislav,
On Mon, Oct 12, 2015 at 6:09 PM, Ladislav Michl wrote:
> Used NAND chips requires at least 4-bit error correction, so use BCH8
> as it is what kernel uses.
>
> Signed-off-by: Ladislav Michl
>
Thanks for the patch. It looks good to me.
> -Original Message-
> From: Prabhakar [mailto:prabha...@freescale.com]
> Sent: Friday, October 16, 2015 2:28 PM
> To: Gong Qianyu-B52263; u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Wang
> -Original Message-
> From: Prabhakar [mailto:prabha...@freescale.com]
> Sent: Friday, October 16, 2015 2:20 PM
> To: Gong Qianyu-B52263; u-boot@lists.denx.de
> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Xie Shaohui-
> B21989; Song Wenbin-B53747; Wood Scott-B07421; Wang
>From bfc8c2402323353205bc39fa90395417e7ef868c Mon Sep 17 00:00:00 2001
From: Chin Liang See
Date: Thu, 15 Oct 2015 13:57:42 +0800
Subject: [PATCH v4 4/5] arm: dts: socfpga: Increase the
spi-max-frequency for
QSPI flash
With a working QSPI calibration, the SCLK can now run up
>From 3b86e60182b87a96f2e5e2236df7a877c9a8c468 Mon Sep 17 00:00:00 2001
From: Chin Liang See
Date: Thu, 15 Oct 2015 14:04:39 +0800
Subject: [PATCH v4 5/5] lib, fdt: Adding fdtdec_get_u32 function
Adding fdtdec_get_u32 function which is the
unsigned version for fdtdec_get_int
On Fri, Oct 16, 2015 at 06:55:58AM +, Joakim Tjernlund wrote:
> On Thu, 2015-10-15 at 17:58 -0400, Tom Rini wrote:
> > On Thu, Oct 15, 2015 at 03:56:09PM +, Joakim Tjernlund wrote:
> > > On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
> > > > On Thu, 2015-10-01 at 08:57 +,
On Fri, Oct 16, 2015 at 09:39:50AM +0200, stefano wrote:
> Hi Tom,
>
> there is still a missing bug fix to be merged for the release:
>
> http://patchwork.ozlabs.org/patch/528422/
>
> Same fix were already merged for the other vf610 board (colibri_vf).
>
> Can you pick it ? Anyway, I
> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
> Sent: Friday, September 04, 2015 5:46 AM
> To: Gong Qianyu-B52263
> Cc: Joe Hershberger; u-boot; Hu Mingkai-B21284
> Subject: Re: [U-Boot] [PATCH] net/eth: fix a bug in on_ethaddr()
>
> Hi Gong,
>
> On
On 16 October 2015 at 04:56, Heiko Schocher wrote:
> Hello Ezequiel,
>
>
> Am 09.10.2015 um 14:30 schrieb Heiko Schocher:
>>
>> Hello Ezequiel,
>>
>> Am 09.10.2015 um 06:01 schrieb Heiko Schocher:
>>>
>>> Hello Ezequiel,
>>>
>>> Am 08.10.2015 um 17:54 schrieb Ezequiel Garcia:
I have the need to erase our eMMC from U-Boot on our custom board due to
a hard wired boot up configuration. Our design is based on the Freescale
i.MX6Q SabreSD Board reference design. The bottom line is the U-Boot
command "mmc erase" is failing with the error "Timeout waiting for DAT0
to go
Hi Jagan,
On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
>> Based on the implementation from Brian Norris
>> for the Linux kernel:
>> https://patchwork.ozlabs.org/patch/513041/
>
> This patch is still under review, will see how it moves.
On Fri, Oct 16, 2015 at 10:40 AM, Fabio Estevam wrote:
> On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
>
>>> Based on the implementation from Brian Norris
>>> for the Linux kernel:
>>>
On Fri, 2015-10-16 at 07:47 -0400, Tom Rini wrote:
> On Fri, Oct 16, 2015 at 06:55:58AM +, Joakim Tjernlund wrote:
> > On Thu, 2015-10-15 at 17:58 -0400, Tom Rini wrote:
> > > On Thu, Oct 15, 2015 at 03:56:09PM +, Joakim Tjernlund wrote:
> > > > On Tue, 2015-10-06 at 11:17 +, Joakim
From: Fabio Estevam
Use the log2 and fls64 header files from the kernel.
Signed-off-by: Fabio Estevam
---
Changes since v6:
- Newly introduced in this series
include/asm-generic/bitops/fls64.h | 36 +++
include/linux/bitops.h
From: Fabio Estevam
Add the SPI NOR protection mechanism from the kernel.
This code is based on the work from Brian Norris
From: Fabio Estevam
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.
Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.
From: Fabio Estevam
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.
Remove the is_power_of_2() definition from compat.h.
Signed-off-by: Fabio Estevam
---
Changes since v6:
- Newly introduced in
On 16 October 2015 at 18:58, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Add the SPI NOR protection mechanism from the kernel.
>
> This code is based on the work from Brian Norris
>
>
On 16 October 2015 at 18:58, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
> status register that can protect selected regions of the SPI NOR.
>
> Take these bits into account when
On 16 October 2015 at 19:20, Otavio Salvador
wrote:
> On Fri, Oct 16, 2015 at 10:40 AM, Fabio Estevam wrote:
>> On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
>>
Based on the implementation from Brian Norris
On 16 October 2015 at 20:59, Jagan Teki wrote:
> On 16 October 2015 at 18:58, Fabio Estevam wrote:
>> From: Fabio Estevam
>>
>> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
>> status register that can
On 2015-10-06 11:27 AM, Paul Gortmaker wrote:
> On 2015-10-05 08:53 PM, Paul Gortmaker wrote:
>> [Re: [U-Boot] [PATCH 5/5] sbc8641d: enable and test
>> CONFIG_SYS_GENERIC_BOARD] On 04/10/2015 (Sun 01:45) Masahiro Yamada wrote:
>>
>
> [...]
>
>>
>>>
>>> Any plan about this patch?
>>>
>>> I
On Fri, Oct 16, 2015 at 04:51:53PM +0900, Minkyu Kang wrote:
> Dear Tom,
>
> The following changes since commit f861f51c4673d35908e4e330a86c81d7d909b51c:
>
> ls102xa: Fix reset hang (2015-10-12 12:56:32 -0400)
>
> are available in the git repository at:
>
>
On Fri, Oct 16, 2015 at 09:44:41AM +0200, Albert ARIBAUD wrote:
> Hello,
>
> The following changes since commit 1275456d31cc130738775dca19b0a2ab1374cfbd:
>
> Merge branch 'master' of git://git.denx.de/u-boot-arm (2015-10-15 17:45:39
> -0400)
>
> are available in the git repository at:
>
>
On Sat, Oct 17, 2015 at 02:13:57AM +0200, Marek Vasut wrote:
> The following changes since commit 1275456d31cc130738775dca19b0a2ab1374cfbd:
>
> Merge branch 'master' of git://git.denx.de/u-boot-arm (2015-10-15 17:45:39
> -0400)
>
> are available in the git repository at:
>
>
On Fri, Oct 09, 2015 at 04:38:39PM -0400, Anthony Felice wrote:
> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> (vf610: refactor DDRMC code).
>
> Signed-off-by: Anthony Felice
On Tuesday, October 13, 2015 at 03:04:44 AM, Thomas Chou wrote:
> Hi Marek,
Hi!
> On 10/12/2015 09:29 PM, Marek Vasut wrote:
> > On Monday, October 12, 2015 at 03:12:18 PM, Thomas Chou wrote:
> >> Hi Marek,
> >>
> >> On 10/12/2015 06:30 PM, Marek Vasut wrote:
> >>> There are also
On Wednesday, October 14, 2015 at 03:48:21 AM, Thomas Chou wrote:
> Hi Marek,
Hi!
> >>> On 10/12/2015 06:32 PM, Marek Vasut wrote:
> Wouldn't invalidate_dcache_range() be enough here ? You don't care
> about
> the data in the newly allocated area at this point I guess -- either
>
On Tuesday, October 13, 2015 at 02:17:53 AM, Thomas Chou wrote:
> Hi Marek,
Hi!
> On 10/12/2015 09:46 PM, Marek Vasut wrote:
> > On Monday, October 12, 2015 at 02:55:03 PM, Thomas Chou wrote:
> >> Hi Marek,
> >
> > Hi Thomas,
> >
> >> On 10/12/2015 06:32 PM, Marek Vasut wrote:
> >>> Wouldn't
On Friday, October 16, 2015 at 12:12:16 PM, Chin Liang See wrote:
Hi!
> From f22064087684b04d6d6ff105a4766a0902d361a8 Mon Sep 17 00:00:00 2001
> From: Chin Liang See
> Date: Thu, 15 Oct 2015 13:56:45 +0800
> Subject: [PATCH 1/5] spi: cadence_qspi: Ensure spi_calibration is run
On Friday, October 16, 2015 at 12:13:24 PM, Chin Liang See wrote:
> From 4a91b5a380e7d3178d4378df79224442c79278bb Mon Sep 17 00:00:00 2001
> From: Chin Liang See
> Date: Fri, 16 Oct 2015 16:35:10 +0800
> Subject: [PATCH v4 2/5] spi: cadence_qspi: Fix fdt read of
>
On Friday, October 16, 2015 at 12:16:15 PM, Chin Liang See wrote:
> From 3b86e60182b87a96f2e5e2236df7a877c9a8c468 Mon Sep 17 00:00:00 2001
> From: Chin Liang See
> Date: Thu, 15 Oct 2015 14:04:39 +0800
> Subject: [PATCH v4 5/5] lib, fdt: Adding fdtdec_get_u32 function
>
>
On Friday, October 16, 2015 at 10:29:07 AM, Thomas Chou wrote:
> Convert dma_alloc_coherent to use memalign.
>
> Signed-off-by: Thomas Chou
Reviewed-by: Marek Vasut
Thanks!
Best regards,
Marek Vasut
___
U-Boot
On Wednesday, October 14, 2015 at 03:38:39 AM, Thomas Chou wrote:
> Convert cache flush to use dm cpu data.
>
> The original cache flush functions are written in assembly
> and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult
> to convert to use cache configuration in dm cpu data which
The following changes since commit 1275456d31cc130738775dca19b0a2ab1374cfbd:
Merge branch 'master' of git://git.denx.de/u-boot-arm (2015-10-15 17:45:39
-0400)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git
for you to fetch changes up to
This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.
Author:Yen Lin
Signed-off-by: Yen Lin
Signed-off-by: Tom Warren
---
Changes in v2:
-
Hi Linus,
On 16 October 2015 at 15:23, Linus Walleij wrote:
> On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov
> wrote:
>
>> On some systems, UART initialization is performed before running U-Boot.
>> This commit allows to skip UART
On Thursday, October 15, 2015 at 05:13:36 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
>
> Update the L2 AUX CTRL settings for the SoCFPGA.
>
> Enabling D and I prefetch bits helps improve SDRAM performance on the
> platform.
>
> Also, we need
On Monday, October 12, 2015 at 06:59:04 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
>
> We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
> order for the SPL to use SD/MMC.
>
> Signed-off-by: Dinh Nguyen
On Fri, Oct 16, 2015 at 04:27:31PM -0600, Simon Glass wrote:
> Hi Linus,
>
> On 16 October 2015 at 15:23, Linus Walleij wrote:
> > On Wed, Oct 14, 2015 at 6:55 PM, Sergey Temerkhanov
> > wrote:
> >
> >> On some systems, UART initialization is
On 10/17/2015 06:56 AM, Marek Vasut wrote:
But nios2 cpu with 4 bytes
dcache line size does not support this instruction. So we don't
implement the invalidate_dcache_range/all() in u-boot yet.
Where did you find this information ?
Please find it on the foot note of table 7, page 8 of "Nios
Hi Marek,
On 10/17/2015 07:03 AM, Marek Vasut wrote:
I would suggest the "cache alignment check and skip" be removed from
cache flush ops, and say out the DMA buffer allocation rule loudly in
README, and enforce it by guardianship.
What exactly do you envision by this "guardianship" ?
I
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