Add USB EHCI support for ls1012aqds platform
Signed-off-by: Rajat Srivastava
Signed-off-by: Rajesh Bhagat
---
Changes in v2:
- None
.../include/asm/arch-fsl-layerscape/immap_lsch2.h |1 +
include/configs/ls1012aqds.h |5 +
include/usb/ehci-ci.h
Access settings for USB2 IP is added through CSU register.
Added CSU ID for USB2, reg: CSL23_REG[8:0]
Signed-off-by: Rajesh Bhagat
---
Changes in v2:
- None
.../include/asm/arch-fsl-layerscape/ns_access.h|2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/in
This adds the required code to set up a ULPI USB port, for
new NXP USB PHY used in QorIQ platforms.
To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
have to be set in the board configuration file.
Signed-off-by: Rajesh Bhagat
---
Changes in v2:
- Changes return value from -1 to ulp
Adds USB EHCI support for ls1012qds by adding the support
for NXP ULPI PHY and adding the support it configuration
files. Also enables, USB2 IP in ns access defines.
Rajesh Bhagat (3):
drivers: usb: fsl: add USB ULPI init code
config: ls1012aqds: Add USB EHCI support for ls1012aqds
armv8: ls
From: Rajesh Bhagat
Implements the logic to calculate the optimal usb maximum trasfer blocks
instead of sending USB_MAX_XFER_BLK blocks which is 65535 and 20 in case
of EHCI and other USB protocols respectively.
It defines USB_MIN_XFER_BLK/USB_MAX_XFER_BLK trasfer blocks that should
be checked f
Performs code cleanup by making common function for usb_stor_read/write
and implements the logic to calculate the optimal usb maximum trasfer blocks
instead of sending USB_MAX_XFER_BLK blocks which is 65535 and 20 in case
of EHCI and other USB protocols respectively.
Rajesh Bhagat (2):
common:
Performs code cleanup by making common function for usb_stor_read/
usb_stor_write. Currently only difference in these fucntions is call
to usb_read_10/usb_write_10 scsi commands.
Signed-off-by: Rajesh Bhagat
---
Changes in v4:
- Adds code to make common function for read/write
common/usb_stor
On 08.06.2016 14:07, Bin Meng wrote:
Now that we have set up pin control in cpu_init_r(), remove the
duplicated codes in the broadwell gpio driver.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lis
On 08.06.2016 14:07, Bin Meng wrote:
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:
- Pin's PADs only gets configured when GPIO driver is probed, which
is not done by default. This leaves the board in a partially
functional state as we
On 08.06.2016 14:07, Bin Meng wrote:
These are generic and should be turned on on coreboot and qemu-x86.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/lis
On 08.06.2016 14:07, Bin Meng wrote:
This updates the device-tree-bindings doc for x86-pinctrl driver:
- clarify "gpio-offset" is required only when "mode-gpio" is set
- correct property name "pull-strength"
- use tab instead of space at several places
Signed-off-by: Bin Meng
Reviewed-
On 08.06.2016 14:07, Bin Meng wrote:
At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
prov
On 08.06.2016 14:07, Bin Meng wrote:
As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the
The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot en
On 08.06.2016 14:07, Bin Meng wrote:
Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.
Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Ro
On 08.06.2016 14:07, Bin Meng wrote:
The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.
On 09.06.2016 04:55, Simon Glass wrote:
This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.
This makes firefly-rk3288 boot again.
Fixes: abeb272 ("tiny-printf: Support snprintf()")
Signed-off-by: Simon Glass
Reviewed-
Hello,
Am 08.06.2016 um 21:50 schrieb kri...@nmdps.net:
Küldve az én HTC-mről
- Továbbított üzenet -
Feladó: kri...@nmdps.net
Címzett:
Tárgy: u-boot
Dátum: Sze, jún. 8, 2016 19:12
Dear developer,
I own a bananapi m2, on which u-boot does not boot up since commit
90b7fc924adfe7f1745dc
On Wednesday 08 June 2016 08:49 PM, Andrew F. Davis wrote:
> The kernel can now use DT to reserve memory carveouts and
> these areas are now the default for drivers that need reserved
> memory, so reserving more here is unneeded and any memory reserved
> this way will be wasted.
>
> Signed-off-b
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, June 08, 2016 7:29 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Sriram Dash ; albert.u.b...@aribaud.net;
> prabha...@freescale.com; york sun ; Rajat Srivastava
>
> Subject: Re: [PATCH 1/3] drivers:
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, June 08, 2016 7:25 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: s...@chromium.org; york sun ; Sriram Dash
>
> Subject: Re: [PATCH v3] common: usb_storage : Implement logic to calculate
> optimal
>
This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.
This makes firefly-rk3288 boot again.
Fixes: abeb272 ("tiny-printf: Support snprintf()")
Signed-off-by: Simon Glass
---
Changes in v2:
- Correct the 'Fixes' line
lib/
This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.
This makes firefly-rk3288 boot again.
Fixes: 5c411d8 tiny-printf: Support snprintf()
Signed-off-by: Simon Glass
---
lib/tiny-printf.c | 4 +++-
1 file changed, 3 inser
On Tue, 2016-06-07 at 07:41 +0200, Boris Brezillon wrote:
> On Mon, 06 Jun 2016 18:54:03 -0500
> Scott Wood wrote:
>
> > Of course the driver model
> > is probably the long-term solution.
>
> Definitely, and talking about things that need to be reworked, do you
> know why u-boot is using its own
On 06/07/2016 06:47 AM, Max Krummenacher wrote:
> follow parameter name change (nand to mtd) to fix compiler error.
>
> Signed-off-by: Max Krummenacher
>
> ---
>
> Changes in v2:
> - Patch v1 1/1 went into master, but Scott's patch series syncing
> with kernel v4.6 introduced an additional co
Hi,
On Wed, 8 Jun 2016 22:13:50 +0200
Hans de Goede wrote:
> Hi,
>
> On 08-06-16 20:23, Bernhard Nortmann wrote:
> > The patch converts one of the "reserved" fields in the sunxi SPL
> > header to a fel_uEnv_length entry. When booting over USB ("FEL
> > mode"), this enables the sunxi-fel utility
Hi Max,
On Tue, Jun 7, 2016 at 1:46 PM, Max Krummenacher wrote:
> nand torture currently works on exactly one nand block which is specified
> by giving the byteoffset to the beginning of the block.
>
> Extend this by allowing for a second parameter specifying the byte size
> to be tested.
>
> e.g
Hi Max,
On Tue, Jun 7, 2016 at 12:57 PM, Max Krummenacher wrote:
> Hi Benoît,
>
> Thank you for your review.
You're welcome.
> I wanted to wait for Scott's patchseries to make it into master to
> allow for potential needed
> changes.
No problem.
> 2016-05-31 22:21 GMT+02:00 Benoît Thébaudeau
On Wed, Jun 8, 2016 at 5:50 AM, Stefano Babic wrote:
> Add Phytec-i.MX6 SOM with NAND
>
> Support:
>- 1GB RAM
>- Ethernet
>- SPI-NOR Flash
>- NAND (1024 MB)
>- external SD
>- UART
>
> Signed-off-by: Stefano Babic
Reviewed-by: Fabio Estevam
_
Hi Tom,
Here are some more UniPhier updates for -rc2.
- Add eMMC boot suuport for new ARMv8 SoCs
- Misc fixes
Please pull!
The following changes since commit b104b3dc1dd90cdbf67ccf3c51b06e4f1592fe91:
Prepare v2016.07-rc1 (2016-06-06 17:43:54 -0400)
are available in the git repository at:
2016-06-08 18:02 GMT+09:00 Masahiro Yamada :
> I noticed secondary CPUs sometimes fail to wake up, and the root
> cause is that the sev instruction wakes up slave CPUs before the
> preceding the register write is observed by them.
>
> The read-back of the accessed register does not guarantee the or
2016-06-07 21:03 GMT+09:00 Masahiro Yamada :
>
>
>
> Masahiro Yamada (5):
> ARM: uniphier: check return code of setenv()
> ARM: uniphier: do not overwrite fdt_file environment
> ARM: uniphier: do not overwrite bootmode environment
> ARM: uniphier: do not erase when updating U-Boot image in
2016-06-04 22:39 GMT+09:00 Masahiro Yamada :
> This function is shared between PH1-LD11 and PH1-LD20. The difference
> is the boot-mode latch for the USB boot mode.
>
> Signed-off-by: Masahiro Yamada
Applied to u-boot-uniphier/master.
--
Best Regards
Masahiro Yamada
2016-06-04 22:39 GMT+09:00 Masahiro Yamada :
> The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
> from an eMMC device. They are useful to reduce the memory footprint
> of SPL, rather than compiling the whole MMC framework.
>
> Signed-off-by: Masahiro Yamada
Applied to u-boot-u
Hi Hans!
Am 08.06.2016 um 22:13 schrieb Hans de Goede:
Hi,
[...]
This patch looks good to me.
Siarhei any comments from your side ? If not then I'll add this to
u-boot-sunxi/next.
Regards,
Hans
Thanks for looking into it. One small thing I only noticed after posting
the patch: The last "re
Hi Vanessa,
On Wed, Jun 8, 2016 at 3:17 PM, Vanessa Maegima wrote:
> Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
> we should better use imx_ddr_size() function, which automatically
> determines the RAM size.
>
> Signed-off-by: Vanessa Maegima
Thanks for the patch:
Acked-b
Hi Marco,
On Wed, Jun 8, 2016 at 3:05 PM, Marco Franchi wrote:
> Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
> in the kernel.
>
> This problem occurs because the kernel uses this pin in PWM mode and U-Boot
> does not configure the backlight pin as GPIO functionali
Hi Marco,
On 08/06/2016 20:05, Marco Franchi wrote:
> Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
> in the kernel.
>
> This problem occurs because the kernel uses this pin in PWM mode and U-Boot
> does not configure the backlight pin as GPIO functionality.
>
> So
Küldve az én HTC-mről
- Továbbított üzenet -
Feladó: kri...@nmdps.net
Címzett:
Tárgy: u-boot
Dátum: Sze, jún. 8, 2016 19:12
Dear developer,
I own a bananapi m2, on which u-boot does not boot up since commit
90b7fc924adfe7f1745dcf6a1dabb9e77aa762a7.
The console is repeating:
U-Boot 20
Hi,
On 08-06-16 20:23, Bernhard Nortmann wrote:
The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time reque
Old revisions of Utilite (based on cmfx6) do not have a dedicated
card detect pin. But the card is removable by the user and card
detection can be realized with polling (e.g. supported by Linux).
Add the broken-cd property to the mmc device tree instead of the
non-removable property to make card d
Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
in the kernel.
This problem occurs because the kernel uses this pin in PWM mode and U-Boot
does not configure the backlight pin as GPIO functionality.
So fix the problem by explicitly configuring the backlight pin as GPI
Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.
Signed-off-by: Vanessa Maegima
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +-
include/configs/mx6qsabreauto.h | 1
Hi Vanessa,
On 08/06/2016 20:17, Vanessa Maegima wrote:
> Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
> we should better use imx_ddr_size() function, which automatically
> determines the RAM size.
>
> Signed-off-by: Vanessa Maegima
> ---
> board/freescale/mx6qsabreauto/mx6
The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot en
From: Brian Norris
These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.
If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling
From: Maxime Ripard
Add the NAND controller definition to sun5i.dtsi.
Signed-off-by: Maxime Ripard
Signed-off-by: Boris Brezillon
---
arch/arm/dts/sun5i.dtsi | 49 +
1 file changed, 49 insertions(+)
diff --git a/arch/arm/dts/sun5i.dtsi b/arch/a
Hello,
This patch series is adding the normal sunxi NAND controller driver to
u-boot.
It's based on the Linux driver, with a few adaptions to make it work
in Linux.
It's based on Scott's series syncing the MTD/NAND frameworks with
Linux 4.6 [1].
Best Regards,
Boris
[1]https://patchwork.ozlabs
We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.
The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
board/sunxi/board.c|5 +-
drivers/mtd
Enable the NAND controller in the sun5i-r8-chip.dts.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
arch/arm/dts/sun5i-a10s.dtsi | 14 ++
arch/arm/dts/sun5i-a13-olinuxino.dts | 15 +++
arch/arm/dts/sun5i-r8-chip.dts | 15 +++
3 files
We need some macros to manipulate the NAND controller clock.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/ar
Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
drivers/mtd/nand/nand_ids.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 561d2cd..ce0a14e 100644
--- a/drivers
This improves the cread_line() function so that it will correctly
process the 'Home', 'End', 'Delete' and arrow key escape sequences
produced by various terminal emulators. This makes command line editing
a more pleasant experience.
The previous code only supported the cursor keys and the 'Home' k
Hello Mr.Bin,
May I know what is the issue , if you could explain I can fix
this in my target and could provide the patch. I am stuck up with this
issue and couldn't able to proceed further.
Thanks a lot:)
Mit Freundlichen Grüßen
VinothKumar
+49 1798909072
On Wed, Jun 8, 2016 at 7:00 AM
The kernel can now use DT to reserve memory carveouts and
these areas are now the default for drivers that need reserved
memory, so reserving more here is unneeded and any memory reserved
this way will be wasted.
Signed-off-by: Andrew F. Davis
---
include/configs/ti_armv7_keystone2.h | 1 -
1 fi
On 06/08/2016 10:22 AM, Rajesh Bhagat wrote:
> This adds the required code to set up a ULPI USB port, for
> new NXP USB PHY used in QorIQ platforms.
>
> To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
> have to be set in the board configuration file.
>
> Signed-off-by: Rajesh Bhagat
On 06/08/2016 06:12 AM, Sriram Dash wrote:
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, June 06, 2016 6:21 PM
>> To: Sriram Dash ; u-boot@lists.denx.de
>> Cc: york sun ; albert.u.b...@aribaud.net; Rajesh Bhagat
>>
>> Subject: Re: [PATCH v2 1/5] arm64:
On 06/08/2016 06:09 AM, Rajesh Bhagat wrote:
>
>
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Wednesday, June 08, 2016 8:38 AM
>> To: Rajesh Bhagat ; u-boot@lists.denx.de
>> Cc: s...@chromium.org; york sun ; Sriram Dash
>>
>> Subject: Re: [PATCH v3] common:
On 06/08/2016 11:44 AM, Rajesh Bhagat wrote:
>
>
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, June 06, 2016 6:24 PM
>> To: Rajat Srivastava ; u-boot@lists.denx.de
>> Cc: l.majew...@samsung.com; s...@chromium.org; albert.u.b...@aribaud.net;
>> prabha..
On 06/08/2016 06:44 AM, Simon Glass wrote:
> Hi Marek,
>
> On 7 June 2016 at 20:02, Marek Vasut wrote:
>> On 06/08/2016 04:43 AM, Simon Glass wrote:
>>> Hi Marek,
>>
>> Hi!
>>
>>> On 25 May 2016 at 05:26, Marek Vasut wrote:
On 05/25/2016 05:29 AM, Simon Glass wrote:
> Hi Marek,
>
>>
On Wed, Jun 08, 2016 at 07:47:12AM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 7 Jun 2016 21:18:17 -0300 (BRT), Carlos Santos wrote:
>
> > There is already a configuration that makes FIT optional (CONFIG_FIT)
> > but it is partially broken because it does not really remove
> > FIT-related
On 06/08/2016 07:14 AM, Alison Wang wrote:
To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT
image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-
These are generic and should be turned on on coreboot and qemu-x86.
Signed-off-by: Bin Meng
---
configs/coreboot-x86_defconfig | 2 ++
configs/qemu-x86_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 2fa1
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:
- Pin's PADs only gets configured when GPIO driver is probed, which
is not done by default. This leaves the board in a partially
functional state as we must initialize PADs correctly to get
p
Now that we have set up pin control in cpu_init_r(), remove the
duplicated codes in the broadwell gpio driver.
Signed-off-by: Bin Meng
---
drivers/gpio/intel_broadwell_gpio.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpio/intel_broadwell_gpio.c
b/drivers/gpio/intel_broa
This fixes several issues in the pinctrl driver, and add SD controller
card detect pin's PADs configuration to the device tree, so that
Linux kernel SDHC driver is able to identify an inserted SD card.
Testing was done on MinnowMax board, by booting Linux kernel and check
dmesg log to see if SD ca
Hi,
On Wed, Jun 8, 2016 at 8:02 PM, vinoth eswaran wrote:
> Hello Mr.Bin,
>
> May I know what is the issue , if you could explain I can fix
> this in my target and could provide the patch. I am stuck up with this
> issue and couldn't able to proceed further.
I've just sent out a series that
This updates the device-tree-bindings doc for x86-pinctrl driver:
- clarify "gpio-offset" is required only when "mode-gpio" is set
- correct property name "pull-strength"
- use tab instead of space at several places
Signed-off-by: Bin Meng
---
doc/device-tree-bindings/gpio/intel,x86-pinctrl
Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.
Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.
Signed-off-by: Bin Meng
---
arch/x86/dts/bayleybay.dts | 5 +
arch/
At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
provides a config option fsp,emmc-boot-mode
The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.
Signed-off-by: Bin Meng
---
drivers/gpio/intel_ich6_gpio.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.
As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD contro
Hello
Nice to see new entry to boot.
I would like to know if sdcard wired in spi mode can working with this spi boot
support.
Why put sdcard in spi when i have an sdcard slot? :)
Just to solder it for bypass crappy sdcard socket pin contact then boot from
usb.
microsd was cheap in 512mb size or
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hello,
On Wed, 8 Jun 2016 02:56:41 -0700 (PDT)
boob...@gmail.com wrote:
> Hello
>
> Nice to see new entry to boot.
> I would like to know if sdcard wired in spi mode can working with
> this spi boot support.
No, it can't. The SPI protocol used by the SD card is different
from the SPI protocol u
From: Yuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.
Signed-off-by: Yuan Yao
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks.
--
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arc
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
---
configs/ls2080aqds_nand_defconfig | 9 +++
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
board/freescale/ls2080aq
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
Changed in v4:
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan Yao
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
Changed in v6:
remove CONFIG_CMD_SF.
---
include/configs/ls2080aqds.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/confi
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7 ---
inc
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm/i
From: Yuan Yao
Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao
---
New add in v3.
---
drivers/i2c/i2c_core.c | 5 +
drivers/i2c/mxc_i2c.c | 27 +++
include/i2c.h | 3 +++
3 files c
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Yuan Yao (10):
drivers: i2c: mxc: Add early init
armv8: ls2080aqds: Select QSPI CLK div via SCFG
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_nand_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/config
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan Yao
Hi Heiko,
On 06/07/2016 09:31 AM, Heiko Schocher wrote:
> move CONFIG_BOOTDELAY into a Kconfig option. Used for this
> purpose the moveconfig.py tool in tools.
That's great! Finally, someone did this long long patch!
It has been sitting in my queue for about a year... and I never
had the time to
Hi Heiko,
On 06/07/2016 09:31 AM, Heiko Schocher wrote:
> Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips.
>
> Signed-off-by: Heiko Schocher
> Reviewed-by: Tom Rini
>
> ---
>
> Changes in v3: None
> Changes in v2:
> - add Reviewed-by from Tom Rini
>
> drivers/mmc/omap_
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, June 06, 2016 6:24 PM
> To: Rajat Srivastava ; u-boot@lists.denx.de
> Cc: l.majew...@samsung.com; s...@chromium.org; albert.u.b...@aribaud.net;
> prabha...@freescale.com; york sun ; Mingkai Hu
> ; Rajesh Bhaga
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v4:
Merged the below patch into one:
board: fr
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arc
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
board/freescale/ls2080aq
From: Yuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.
Signed-off-by: Yuan Yao
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded clocks.
--
From: Yuan Yao
Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao
---
New add in v3.
---
drivers/i2c/i2c_core.c | 5 +
drivers/i2c/mxc_i2c.c | 27 +++
include/i2c.h | 3 +++
3 files c
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 99b0551..f917484 100644
---
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Yuan Yao (10):
drivers: i2c: mxc: Add early init
armv8: ls2080aqds: Select QSPI CLK div via SCFG
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm/i
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7 ---
inc
1 - 100 of 115 matches
Mail list logo
