Re: [U-Boot] Raspberry Pi Compute Module 1 mini-UART

Hi Matthias, Thank you very much for your help. Unfortunately I'm still a little stuck. Matthias Brugger wrote > 1) as you found out U-Boot is using an embedded device tree. The device > tree it > uses is specified in configs/rpi_* > I suppose you are using rpi_3_defconfig, so your device-tree

[U-Boot] [RESEND PATCH] arm: imx6: cm_fx6: Enable DM SPI and SPI_FLASH, fix SPL build errors

From: Suniel Mahesh Enable driver model for SPI and SPI_FLASH to remove the following compile warning on CM-FX6 SOM: = WARNING == This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release.

Re: [U-Boot] [PATCH 1/3] mtd: rawnand: denali-spl: Add missing hardware init

On 11/27/19 11:20 AM, Masahiro Yamada wrote: > On Tue, Nov 26, 2019 at 5:25 PM Marek Vasut wrote: diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index dbaba3cab2..b8b29812aa 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++

Re: [U-Boot] GPT overlap on i.MX6

Hi Jagan, > Hi, > > I have created GPT table start from 8MB for kernel, roots etc. > something like > > PartStart LBA End LBA Name > Attributes > Type GUID > Partition GUID > 1 0x4000 0x00023fff "boota" > attrs:

Re: [U-Boot] [PATCH 2/5] Revert "ata: fsl_ahci: Add sata DM support for Freescale powerpc socs"

Hi Peng, On 27.11.19 11:02, Peng Ma wrote: This reverts commit 1ee494291880fd51ef0c5f7342e072bdb069d7ff. I'm missing an explanation for this revert (or even better for this whole patch-set). Why are you doing this? Is the new DM driver causing problems? Thanks, Stefan Signed-off-by: Peng

Re: [U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts

On Wed, Nov 27, 2019 at 8:56 AM Ley Foon Tan wrote: > > Add device tree files for Agilex SoC platform. > > socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains > Uboot specific DT properties. > > socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux >

Re: [U-Boot] [PATCH 1/3] mtd: rawnand: denali-spl: Add missing hardware init

On Tue, Nov 26, 2019 at 5:25 PM Marek Vasut wrote: > >> diff --git a/drivers/mtd/nand/raw/denali_spl.c > >> b/drivers/mtd/nand/raw/denali_spl.c > >> index dbaba3cab2..b8b29812aa 100644 > >> --- a/drivers/mtd/nand/raw/denali_spl.c > >> +++ b/drivers/mtd/nand/raw/denali_spl.c > >> @@ -173,6

[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

Some generic PX30 SoMs found in the wild use UART3 as their debug output instead of UART2 (used for MMC) and UART5. Make it possible to use UART3 as early debug output, with the associated clock and pinmux configuration. Two sets of output pins are supported (M0/M1) so a Kconfig option to select

[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order

According to the PX30 TRM, the iomux registers come first, before the pull and strength control registers. Signed-off-by: Paul Kocialkowski --- arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git

[U-Boot] [PATCH 4/5] Revert "configs: enable sata device module in T2080QDS"

This reverts commit 02dc1599ba0b16eb21ba0c206e5b6f38fe7b67a7 Just reverts some configs about sata to fit fsl_sata.c Signed-off-by: Peng Ma --- configs/T2080QDS_NAND_defconfig | 4 configs/T2080QDS_SDCARD_defconfig | 4 configs/T2080QDS_SECURE_BOOT_defconfig| 4

[U-Boot] [PATCH 5/5] ata: fsl_sata: Update fsl sata header file

The variable(dma_flag) will be used by both fsl_ahci.c and fsl_sata.c, Now we support the fsl_sata.c to DM mode and revert fsl_ahci.c(This variable declare here). So we should Add this changed. Signed-off-by: Peng Ma --- drivers/ata/fsl_sata.h | 1 + 1 file changed, 1 insertion(+) diff --git

[U-Boot] [PATCH 2/5] Revert "ata: fsl_ahci: Add sata DM support for Freescale powerpc socs"

This reverts commit 1ee494291880fd51ef0c5f7342e072bdb069d7ff. Signed-off-by: Peng Ma --- drivers/ata/Kconfig| 10 - drivers/ata/Makefile |1 - drivers/ata/fsl_ahci.c | 1030 drivers/ata/fsl_sata.h |1 - 4 files changed, 1042 deletions(-)

[U-Boot] [PATCH 3/5] arch: powerpc: Rewrite the sata node to fit the driver

The sata of our powerpc platform are updated. This changed is to fit the driver init Signed-off-by: Peng Ma --- arch/powerpc/dts/t2080.dtsi | 15 --- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index

[U-Boot] [PATCH 1/5] Revert "powerpc: mpc85xx: delete FSL_SATA for T2080QDS board."

This reverts commit 856b9cdb53f0e6c8d98f81cf71ef363c16b0aa0e. Signed-off-by: Peng Ma --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8cc82f80b4..6fc6ea8fef

Re: [U-Boot] [PATCH v2 2/3] env: Tidy up some of the env code

On Wed, Nov 27, 2019 at 10:39 AM James Byrne wrote: > > On 27/11/2019 05:52, AKASHI Takahiro wrote: > > On Thu, Nov 21, 2019 at 02:32:47PM +, James Byrne wrote: > >> This commit tidies up a few things in the env code to make it safer and > >> easier to extend: > >> > >> - The hsearch_r()

Re: [U-Boot] [PATCH v3 06/22] ram: rockchip: add common code for sdram driver

Hi Kever/YouMin, On Fri, Nov 15, 2019 at 8:43 AM Kever Yang wrote: > > There are some function like os_reg setting, capacity detect functions, > can be used as common code for different Rockchip SoCs, add a > sdram_common.c for all these functions. > > Signed-off-by: YouMin Chen >

Re: [U-Boot] [PATCH v2 2/3] env: Tidy up some of the env code

On 27/11/2019 05:52, AKASHI Takahiro wrote: On Thu, Nov 21, 2019 at 02:32:47PM +, James Byrne wrote: This commit tidies up a few things in the env code to make it safer and easier to extend: - The hsearch_r() function took a 'struct env_entry' as its first parameter, but only used the

[U-Boot] [PATCH v3] board_f.c: Insure gd->new_bootstage alignment

In reserve_bootstage(), in case size is odd, gd->new_bootstage is not aligned. In bootstage_relocate(), the platform hangs when getting access to data->record[i].name. To avoid this issue, make gd->new_bootstage 16 byte aligned. To insure that new_bootstage is 16 byte aligned (at least needed for

Re: [U-Boot] [PATCH v5 078/101] x86: Enable pinctrl in SPL and TPL

Hi Simon, On Mon, Nov 25, 2019 at 12:12 PM Simon Glass wrote: > > If these phases are used we typically want to enable pinctrl in then, so > that pad setup and GPIO access are possible. > > Signed-off-by: Simon Glass > --- > > Changes in v5: > - Correct build error in chromebook_samus_tpl > >

Re: [U-Boot] [PATCH v5 076/101] spi: ich: Add Apollo Lake support

On Mon, Nov 25, 2019 at 12:12 PM Simon Glass wrote: > > Add support for Apollo Lake to the ICH driver. This involves adjusting the > mmio address and skipping setting of the bbar. > > Signed-off-by: Simon Glass > --- > > Changes in v5: None > Changes in v4: > - apollolake -> Apollo Lake > >

Re: [U-Boot] [PATCH v3 2/2] drivers: usb: host: Add BRCM xHCI driver

On 11/26/19 7:41 PM, Vladimir Olovyannikov wrote: Hi, [...] > +#define USBAXI_AWCACHE 0xF > +#define USBAXI_ARCACHE 0xF > +#define USBAXI_AWPROT0x8 > +#define USBAXI_ARPROT0x8 > +#define USBAXIWR_SA_VAL ((USBAXI_AWCACHE <<

[U-Boot] [PATCH v2] board_f.c: Insure gd->new_bootstage alignment

In reserve_bootstage(), in case size is odd, gd->new_bootstage is not aligned. In bootstage_relocate(), the platform hangs when getting access to data->record[i].name. To avoid this issue, make gd->new_bootstage 16 byte aligned. To insure that new_bootstage is 16 byte aligned (at least needed for

Re: [U-Boot] [PATCH] board_f.c: Insure gd->new_bootstage alignment

Hi Heinrich On 11/26/19 6:41 PM, Heinrich Schuchardt wrote: > On 11/26/19 1:16 PM, Patrick DELAUNAY wrote: >> Hi, >> >>> From: Patrice CHOTARD >>> Sent: lundi 25 novembre 2019 14:48 >>> >>> In reserve_bootstage(), in case size is odd, gd->new_bootstage is not >>> aligned. In >>>

[U-Boot] GPT overlap on i.MX6

Hi, I have created GPT table start from 8MB for kernel, roots etc. something like PartStart LBA End LBA Name Attributes Type GUID Partition GUID 1 0x4000 0x00023fff "boota" attrs: 0x0004 type:

[U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts

Add device tree files for Agilex SoC platform. socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains Uboot specific DT properties. socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux (kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc) Signed-off-by: Ley Foon Tan

[U-Boot] [PATCH v8 14/19] ddr: altera: agilex: Add SDRAM driver for Agilex

Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Add compatible "intel,sdr-ctl-agilex". v4: - Fixed checkpatch warnings v3: - Use sdmmc_soc64.* - Change compatible string to use "intel"

[U-Boot] [PATCH v8 18/19] configs: socfpga: Move Stratix10 and Agilex common CONFIGs

Move Stratix10 and Agilex common CONFIGs to socfpga_soc64_common.h. Signed-off-by: Ley Foon Tan --- ...ratix10_socdk.h => socfpga_soc64_common.h} | 8 +- include/configs/socfpga_stratix10_socdk.h | 193 +- 2 files changed, 7 insertions(+), 194 deletions(-) copy

[U-Boot] [PATCH v8 11/19] cache: Add Arteris Ncore cache coherent unit driver

Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Move CCU driver to DM.

[U-Boot] [PATCH v8 19/19] arm: socfpga: agilex: Enable Agilex SoC build

Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v7: - Move CONFIG_DW_WDT_CLOCK_KHZ to _soc64_common.h - Use fdtimage filename from CONFIG_DEFAULT_DEVICE_TREE v6: - Include socfpga_soc64_common.h. v5: - Enable NCORE_CACHE v3: - Disable

[U-Boot] [PATCH v8 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz

CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. ---

[U-Boot] [PATCH v8 09/19] clk: agilex: Add clock driver for Agilex

Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Use agilex-clock.h from Linux instead of using

[U-Boot] [PATCH v8 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code

Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Move #include to top of header file. v5: - Revert CLKMGR_INTOSC_HZ to 460MHz. --- .../include/mach/clock_manager_s10.h | 16 +++--

[U-Boot] [PATCH v8 04/19] arm: socfpga: agilex: Add reset manager support

Add reset manager support for Agilex. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Remove reset_reset_manager_agilex.h and use reset_manager_soc64.h. v3: - Add reset_manager_soc64.h - Convert to use defines instead of struct. ---

[U-Boot] [PATCH v8 16/19] arm: socfpga: agilex: Add SPL for Agilex SoC

Add SPL support for Agilex SoC. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Probe CCU driver with DM method. v4: - Move spl_early_init() to entry of board_init_f - Add socfpga_get_manager_addr(). - Remove SYSMGR_DMA and SYSMGR_DMA_PERIPH, already set in

[U-Boot] [PATCH v8 10/19] arm: socfpga: agilex: Add clock wrapper functions

Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary(). Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Use new macro names from agilex-clock.h. v4: - Change to use SYSMGR_SOC64* prefix. v3: - Improved

[U-Boot] [PATCH v8 05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code

Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Remove system_manager_s10.h and use system_manager_soc64.h. v4: - Change prefix from SYSMGR_S10* to

[U-Boot] [PATCH v8 13/19] ddr: altera: Restructure Stratix 10 SDRAM driver

Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v6: - Remove compatible "intel,sdr-ctl-agilex" from this patch. v3: - Change sdram_common.* to

[U-Boot] [PATCH v8 06/19] arm: socfpga: agilex: Add system manager support

Add system manager support for Agilex. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Remove system_manager_agilex.h and use system_manager_soc64.h directly. v3: - Change include filename to system_manager_soc64.h. - Move to use defines instead of struct. v2: - Include

[U-Boot] [PATCH v8 15/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC

Add socdk board support for Intel Agilex SoC Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- board/intel/agilex-socdk/MAINTAINERS | 7 +++ board/intel/agilex-socdk/Makefile| 7 +++ board/intel/agilex-socdk/socfpga.c | 7 +++ 3 files changed, 21 insertions(+)

[U-Boot] [PATCH v8 12/19] arm: agilex: Add clock handoff offset for Agilex

Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v8: - Fixed missing CONFIG_ prefix for TARGET_SOCFPGA_STRATIX10. --- arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++--

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