SPL needs DM GPIO to read the SD card-detect signal. This complements
the fix in commit 70bae02f71d4 ("arm: mvebu: clearfog: fix boot from SD
card").
Signed-off-by: Baruch Siach
---
configs/clearfog_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/clearfog_defconfig
On Sun, Dec 8, 2019 at 11:59 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
> >
> > This subsystem is present on various Intel SoCs.
> >
> > Add very basic support for taking an lpss device out of reset.
> >
> > Signed-off-by: Simon Glass
> >
> > ---
> >
> > Changes
On Sun, Dec 8, 2019 at 11:58 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
> >
> > If these phases are used we typically want to enable pinctrl in then, so
> > that pad setup and GPIO access are possible.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
>
> With of-platdata we need to create drivers for particular chips, or at
> least drivers that are separate from the standard code, since C structures
> are created by dtoc which are private to that driver.
>
> To avoid duplicating the probing
On Sun, Dec 8, 2019 at 11:58 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
> >
> > In TPL we want to reduce code size and support running with CONFIG_PCI
> > disabled. Add special code to handle this using a fixed BAR programmed
> > into the SPI on boot. Also cache
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
>
> Add support for Apollo Lake to the ICH driver. This involves adjusting the
> mmio address and skipping setting of the bbar.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> Add this method so that the memory-mapped location of the SPI flash can
> be queried.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Use the new
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> Apollo Lake (APL) only supports hardware sequencing. Add support for this
> into the SPI driver, as an option.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
>
> ---
>
> Changes in v6:
> - Add a comment as to why dev_read_bool() is
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> The Intel Fast SPI interface is similar to ICH. Add of-platdata support
> for this using the "intel,fast-spi" compatible string.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
>
On Sun, Dec 8, 2019 at 11:56 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
> >
> > This incorrectly shortens read operations if there is a maximum write size
> > but no maximum read size. Fix it.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v6: None
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
>
> This subsystem is present on various Intel SoCs.
>
> Add very basic support for taking an lpss device out of reset.
>
> Signed-off-by: Simon Glass
>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Add support for
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
>
> If these phases are used we typically want to enable pinctrl in then, so
> that pad setup and GPIO access are possible.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v6: None
> Changes in v5:
> - Correct build error in
On Sat, Dec 7, 2019 at 12:52 PM Simon Glass wrote:
>
> In TPL we want to reduce code size and support running with CONFIG_PCI
> disabled. Add special code to handle this using a fixed BAR programmed
> into the SPI on boot. Also cache the SPI flash to speed up boot.
>
> Signed-off-by: Simon Glass
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> This incorrectly shortens read operations if there is a maximum write size
> but no maximum read size. Fix it.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> We don't want to include dt-structs.h in header files, so add a note about
> that.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Add a patch to explain
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> It is useful to store the mmio base in platdata. It reduces the amount of
> casting needed. Update the code and move the struct to the C file at the
> same time, as we will need to use with of-platdata.
>
> Signed-off-by: Simon Glass
>
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> Use debug() instead of printf() to reduce code size and change a bool
> return value to the use the 'bool' type. Also drop the global data
> declaration since it not actually used. Finally, set the log category.
>
> Signed-off-by: Simon Glass
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> Move the header files into the right order.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> drivers/spi/ich.c
On Sat, Dec 7, 2019 at 12:51 PM Simon Glass wrote:
>
> Use dev_get_driver_data() to obtain the device type. It has the same
> effect and is shorter.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
On Sat, Dec 7, 2019 at 12:50 PM Simon Glass wrote:
>
> Reduce the size of the probe function but putting this code into its own
> function.
>
> Also remove the assumption that the PCH is always a parent of the SPI
> controller, as this is not the case APL platforms. Use driver model to
> find the
On Sat, Dec 7, 2019 at 12:50 PM Simon Glass wrote:
>
> It is annoying to have some of the init code in a different part of the
> file. Move ich_init_controller() to just above probe() to keep things
> together.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
On Sat, Dec 7, 2019 at 12:50 PM Simon Glass wrote:
>
> We don't normally need this on x86 unless the size of SPI flash devices is
> larger than 16MB. This can be enabled by particular SoCs as needed, since
> it adds to code size.
>
> Drop the default enabling of this option on x86.
>
>
On Sat, Dec 7, 2019 at 12:50 PM Simon Glass wrote:
>
> At present we have to have an xfer() method even if it does nothing. This
> is not correct, so fix it.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
>
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> This is used on several boards so add it to the common file. Also add a
> useful power-limit value while we are here.
>
> Reviewed-by: Bin Meng
> Signed-off-by: Simon Glass
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> At present binman does not support updating a device tree that is part of
> U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
> updated entry information. This makes binman_entry_find() work correctly.
>
> Do the same
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> At present if SPL sets up the microcode then it is still included in
> U-Boot as well. This is wasteful as microcode is large. Adjust the logic
> in the image to prevent this.
>
> Reviewed-by: Bin Meng
> Signed-off-by: Simon Glass
> ---
>
>
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
> location from where SPL must be placed in ROM. In other words, although
> SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
>
> Add a Kconfig option
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> Add these entries to the ROM so that we can list the contents of an image
> with 'binman ls'. The image-header is not essential but does speed up
> access.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> The existing work-around for positioning U-Boot in the ROM when it
> actually runs from RAM still exists and there is not obvious way to change
> this.
>
> Add a proper Kconfig option to handle this case. This also adds a new bool
> property
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> Include the IFWI section and the FSP-M binary. The FSP-T binary is not
> currently used, as CAR is set up manually.
>
> Also drop the FSP binary as this relates only to FSP1.
>
> Reviewed-by: Bin Meng
> Signed-off-by: Simon Glass
> ---
>
>
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
> Add support for these along with suitable configuration options.
>
> To make the code cleaner, adjust a few definitions in processor.h so that
> they can be used from
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> At present we don't support loading microcode with FSP2. The correct way
> to do this is by adding it to the FIT. For now, disable including
> microcode in the image.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> We don't generally have enough space to run this, so don't build it into
> TPL. This helps reduce the size of TPL.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> Many Intel SoCs require a FIT in order to boot properly. Add an option to
> include this and enable it by default.
>
> This term can be confused with FIT (Flat Image Tree) in U-Boot so the
> CONFIG option has to include 'X86'.
>
>
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> The current 'fsp' command only works with FSP1. Update it to handle FSP2
> as well. Convert everything to hex which is what U-Boot uses.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5:
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> FSP-S is used by the notify call after it has been used for silicon init.
> To avoid having to load it again, add a field to store the location.
>
> Reviewed-by: Bin Meng
> Signed-off-by: Simon Glass
> ---
>
> Changes in v6: None
> Changes
On Sun, Dec 8, 2019 at 11:11 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
> >
> > Add support for some important configuration options and FSP memory init.
> > The memory init uses swizzle tables from the device tree.
> >
> > Support for the FSP_S binary is also
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> With FSP2 we need to run silicon init early after relocation. Add a new
> hook for this.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> The FSP-S may do this but at least for coral it does not. Set this up so
> that graphics is not deathly slow.
>
> It isn't clear whether the FSP is expected to set up MTRR. It is not
> mentioned in the APL FSP document.
>
> Signed-off-by:
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> The fsp_notify() API is the same for FSP1 and FSP2. Move it into a new
> common API file.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Drop incorrect
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> At present the interrupt table is included in all phases of U-Boot. Allow
> it to be omitted, e.g. in TPL, to reduce size.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> Both versions of FSP can use the same graphics support, so move it into
> the common directory.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> This generic FSP file should include the generic FSP support header, not
> the FSP1 version. Fix it.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> These drivers are not needed on all platforms. While they are small, it
> is useful in TPL to drop then. Add Kconfig control to allow this.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in
On Sat, Dec 7, 2019 at 12:49 PM Simon Glass wrote:
>
> Add support for some important configuration options and FSP memory init.
> The memory init uses swizzle tables from the device tree.
>
> Support for the FSP_S binary is also included.
>
> Bootstage timing is used for both FSP_M and FSP_S and
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> We don't want to pull in libfdt if of-platdata is being used, since it
> reduces the available code-size saves. Also, SPI flash is seldom needed
> in TPL.
>
> Drop these options.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> At present with fsp a single DRAM bank is added which extends to the
> whole size of memory. However there is typically only 2GB of memory
> available below the 4GB boundary, and this is what is used by U-Boot while
> running in 32-bit mode.
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> Set up MTRRs for the FSP SDRAM regions to improve performance.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5:
> - Fix FST typo
>
> Changes in v4: None
> Changes in v3:
> - Move
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> This function is a bit confusing at present due to the error handling.
> Update it to remove the goto, returning errors as they happen.
>
> While we are here, use hex for the data size since this is the norm in
> U-Boot.
>
> Signed-off-by:
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> With Apollo Lake we need to support a normal cache, which almost never
> changes and a much smaller 'variable' cache which changes every time.
>
> Update the code to add a cache type, use an array for the caches and use a
> for loop to
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> This function is only used within the implementation so make it static.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Add new patch to make mrccache_update()
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> This function needs to be different for FSP2, so move the existing
> function into the fsp1 directory. Since it is only called from one file,
> drop it from the header file.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
>
On Sat, Dec 7, 2019 at 12:48 PM Simon Glass wrote:
>
> Add support for a second cache type, for Apollo Lake.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - apollolake -> Apollo Lake
>
> Changes in v3:
> - Move the
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> At present we reuse the mrc_output char * to also point to the cache
> record after it has been set up. This is confusing and doesn't save much
> data space.
>
> Add a new mrc_cache member instead.
>
> Signed-off-by: Simon Glass
>
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> It is now possible to obtain the memory map for a SPI controllers instead
> of having it hard-coded in the device tree. Update the code to support
> this.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> Change the algorithm to first find the flash device then read the
> properties using the livetree API. With this change the device is not
> probed so this needs to be done in mrccache_save().
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> This should take account of the end of the new cache record since a record
> cannot extend beyond the end of the flash region. This problem was not
> seen before due to the alignment of the relatively small amount of MRC
> data.
>
> But with
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> At present the records are 4KB in size. This is unnecessarily large when
> the SPI-flash erase size is 256 bytes. Reduce it so it will be more
> efficient with Apollo Lake's 24-byte variable-data record.
>
> Signed-off-by: Simon Glass
>
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> Update this uclass to support the needs of the Apollo Lake ITSS. It
> supports four operations.
>
> Move the uclass into a separate directory so that sandbox can use it too.
> Add a new Kconfig to control it and enable this on x86.
>
>
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
> which uses a simple 'adder' driver to test the p2sb functionality.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6:
> - Correct a few
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> Define this symbol so that we can use binman symbols correctly.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> When reseting sandbox for tests, disable mmio support since that is the
> default state.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Split out into a
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> Add a simple sandbox test for this uclass.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6:
> - Move setting of CONFIG_IRQ in sandbox to this patch
>
> Changes in v5: None
> Changes in v4:
> - Drop itss uclass
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> The Primary-to-Sideband bus (P2SB) is used to access various peripherals
> through memory-mapped I/O in a large chunk of PCI space. The space is
> segmented into different channels and peripherals are accessed by
> device-specific means
On Sat, Dec 7, 2019 at 12:47 PM Simon Glass wrote:
>
> Add a simple PMC for sandbox to permit tests to run.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - Rename power-mgr uclass to acpi-pmc
>
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> We don't expect an exception in TPL and don't need to set up interrupts in
> TPL. Drop this whole file.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Drop the
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Intel x86 SoCs have a power manager/controller which handles several
> power-related aspects of the platform. Add a uclass for this, with a few
> useful operations.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> On x86 platforms the timer is reset to 0 when the SoC is reset. Having
> this as the timer base is useful since it provides an indication of how
> long it takes before U-Boot is running.
>
> When U-Boot sets the timer base to something else,
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> We don't need to know every detail about the CPU in TPL. Drop some
> superfluous functions to reduce code size. Add a simple CPU detection
> algorithm which just supports Intel and AMD, since we only support TPL
> on Intel, so far.
>
>
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Most of the timer-calibration methods are not needed on recent Intel CPUs
> and just increase code size. Add an option to use the known-good way to
> get the clock frequency in TPL. Size reduction is about 700 bytes.
>
> Note that version 1
On Sun, Dec 8, 2019 at 10:04 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
> >
> > At present these options cannot be enabled for SPL/TPL, but this can be
> > useful in some cases. Add Kconfig options to allow it.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> >
On Sun, Dec 8, 2019 at 10:06 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
> >
> > At present the early timer init happens as soon as driver model is set up.
> > This makes it impossible to do anything that needs driver model but must
> > run before devices are probed
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> At present the early timer init happens as soon as driver model is set up.
> This makes it impossible to do anything that needs driver model but must
> run before devices are probed (as needed with Intel's FSP-S, for example).
>
> In any case
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> At present these options cannot be enabled for SPL/TPL, but this can be
> useful in some cases. Add Kconfig options to allow it.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v6:
> - Split out Kconfig change to new patch to enable full
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> When device-tree compilation fails it is sometimes tricky to see which
> line is broken, since the input file to dtc is a pre-processed version
> of the device tree.
>
> Add a line that points to the file that needs to be checked:
>
> When
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> top of 32-bit address space, so that it can be executed in place and read
> simply by copying from memory. For an 8MB ROM the mapping starts at
> 0xff80.
>
>
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Allow this driver to set up an IO address in SPL using an 'early-regs'
> property. This allows SPL to use the I2C driver without having to enable
> the full PCI stack.
>
> Also split out ofdata_to_platdata in designware driver since this is
On Sun, Dec 8, 2019 at 9:54 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
> >
> > Drivers are not allowed to use static data since they may be used in SPL
> > where BSS is not available.
> >
> > It is possible that driver model may provide support for numbering
On Sun, Dec 8, 2019 at 9:52 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
> >
> > This is hacked into the driver at present. It seems better to have it as
> > a separate driver that uses the base driver. Create a new file and put
> > the X86 code into it.
> >
> >
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Drivers are not allowed to use static data since they may be used in SPL
> where BSS is not available.
>
> It is possible that driver model may provide support for numbering devices
> in the future. But for now, move this to global_data.
>
>
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> This is hacked into the driver at present. It seems better to have it as
> a separate driver that uses the base driver. Create a new file and put
> the X86 code into it.
>
> Actually the Baytrail settings should really come from the device
On Sun, Dec 8, 2019 at 9:10 AM Bin Meng wrote:
>
> On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
> >
> > These functions are used by code outside the network support, so move them
> > to lib/ to be more accessible.
> >
> > Without this, the functions are only accessible in SPL/TPL only if
>
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> These functions are used by code outside the network support, so move them
> to lib/ to be more accessible.
>
> Without this, the functions are only accessible in SPL/TPL only if
> CONFIG_SPL/TPL_NET are defined. Many boards do not enable
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> Early in boot it is necessary to decode the PCI device/function values for
> particular peripherals in the device tree or of-platdata. This is needed
> in TPL where CONFIG_PCI is not defined.
>
> To handle this, move pci_get_devfn() into a
On Sat, Dec 7, 2019 at 12:45 PM Simon Glass wrote:
>
> If the offset is -1 this function correctly sets up a null ofnode. But if
> the offset is any other negative number (e.g. -FDT_ERR_BADPATH) then it
> does the wrong thing.
>
> An offset of -1 in ofnode indicates that the ofnode is not valid.
On Sat, Dec 7, 2019 at 12:45 PM Simon Glass wrote:
>
> At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
> is included in SPL/TPL without any control for boards. Some boards may
> want to disable this to reduce code size where GPIOs are not needed in
> SPL or TPL.
>
> Add a
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass wrote:
>
> At present PCI auto-configuration happens in U-Boot both before and after
> relocation. This is a waste of time and may mess up static addresses used
> in board_init_f(). Adjust the code to supporting doing auto-configuration
> once, after
On Sat, Dec 7, 2019 at 12:45 PM Simon Glass wrote:
>
> SPL and TPL can access information about binman entries using link-time
> symbols but this is not available in U-Boot proper. Of course it could be
> made available, but the intention is to just read the device tree.
>
> Add support for this,
On 11/9/19 9:39 AM, Heinrich Schuchardt wrote:
This patch series enables the UEFI unit tests on the sandbox.
The first patch add the missing compatible property in the device trees
which is required by on of the unit tests.
The real time clock unit test will fail if the sandbox is openend
On 11/28/19 8:20 AM, Heinrich Schuchardt wrote:
On 11/27/19 8:45 PM, Cristian Ciocaltea wrote:
On Tue, Nov 26, 2019 at 07:31:39PM +0100, Heinrich Schuchardt wrote:
On 11/24/19 9:11 PM, Cristian Ciocaltea wrote:
Currently the only way to run an EFI binary like GRUB2 is via the
'bootefi'
Provide public function efi_run_imager() which can be used to run an UEFI
image from memory.
Signed-off-by: Heinrich Schuchardt
---
cmd/bootefi.c| 51 +++-
include/efi_loader.h | 2 ++
2 files changed, 34 insertions(+), 19 deletions(-)
diff
As part of moving the parsing of command line arguments to do_bootefi()
call efi_install_fdt() with the address of the device tree instead of a
string.
If the address is EFI_FDT_USE_INTERNAL (= 0), the internal device tree
is used.
Signed-off-by: Heinrich Schuchardt
---
cmd/bootefi.c|
Export the efi_install_fdt() function.
Signed-off-by: Heinrich Schuchardt
---
cmd/bootefi.c| 2 +-
include/efi_loader.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 15b4ff9515..9d9019c269 100644
--- a/cmd/bootefi.c
+++
If the bootefi command is called without passing the address of a device
tree, the internal device tree is used. For devices with a hardware device
tree it is preferable to used the hardware device tree in this case.
Signed-off-by: Heinrich Schuchardt
---
cmd/bootefi.c | 22
A patch series has been suggested to provide secure UEFI boot via FIT
images.
This patch series exports the functions needed for the implementation.
v2:
Resend the efi_install_fdt() rework patches.
Export the efi_run_image() and efi_install_fdt().
Heinrich Schuchardt (4):
unsigned char should be called uchar and not unchar.
This fixes a build error in lib/crypto/x509_cert_parser.c.
Signed-off-by: Heinrich Schuchardt
---
include/linux/types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/types.h b/include/linux/types.h
index
Hmm, looks like the google webmail doesn't send multi-mime messages.
I didn't know that yet.
And if there is no progress, then i would look for another solution.
No problem :-)
Am Sa., 7. Dez. 2019 um 10:27 Uhr schrieb Andreas Färber :
>
> Sascha,
>
> Am 07.12.19 um 07:23 schrieb Sascha Dewald:
On Sat, Dec 07, 2019 at 09:51:22PM +0100, Heinrich Schuchardt wrote:
> On 12/6/19 10:50 PM, Tom Rini wrote:
> > On Wed, Nov 13, 2019 at 09:45:00AM +0900, AKASHI Takahiro wrote:
> >
> > > Imported from linux kernel v5.3:
> > > x509.asn1 without changes
> > > x509_akid.asn1 without changes
> >
Hi Tom,
On Fri, Dec 6, 2019 at 3:55 PM Tom Rini wrote:
>
> On Fri, Dec 06, 2019 at 03:05:55PM +0100, Simon Goldschmidt wrote:
> > On Fri, Dec 6, 2019 at 2:49 PM Giulio Benetti
> > wrote:
> > >
> > > Hello Tom, all,
> > >
> > > On 12/6/19 2:34 PM, Tom Rini wrote:
> > > > On Fri, Dec 06, 2019 at
On 12/6/19 10:50 PM, Tom Rini wrote:
On Wed, Nov 13, 2019 at 09:45:00AM +0900, AKASHI Takahiro wrote:
Imported from linux kernel v5.3:
x509.asn1 without changes
x509_akid.asn1 without changes
x509_parser.h without changes
x509_cert_parser.c with changes marked as __UBOOT__
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