Hi Atish
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Atish Patra
> Sent: Friday, February 28, 2020 5:01 AM
> To: u-boot@lists.denx.de
> Cc: Atish Patra; Alexander Graf; Anup Patel; Bin Meng; Joe Hershberger; Loic
> Pallardy; Lukas Auer; Marek Behún; Marek Vasut; Patrick
ZynqMP mini configurations works without PMU firmware that's why there is
no reason to enable the driver and check if it was probed properly.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/xilinx/zynqmp/zynqmp.c
> On 2/19/20 7:55 PM, Marek Vasut wrote:
> > From: Holger Brunck
> >
> > Add initial support for the ABB SECU board, which is an ArriaV-based
> > SoCFPGA system with ethernet and booting from Denali NAND.
> >
> > Signed-off-by: Holger Brunck
> > Cc: Ley Foon Tan
> > Cc: Simon Goldschmidt
> >
Hi Sean
This patch series become larger and larger from v1 with 11 patches to
v5 with 33 patches.
You shall just fix the suggestions from the previous version in the
next version.
Additional extra features and subsystem drivers that you want to
support, you shall send them individually instead of
Hi Sean
> Due to the large number of clocks, I decided to use the CCF. The overall
> structure is modeled after the imx code. Clocks are stored in several
> arrays. There are some translation macros (FOOIFY()) which allow for more
> dense packing. A possible improvement could be to only store
The commit 5fed97af20da ("Makefile: ensure DTB doesn't overflow into
initial stack") adds an extra check for stack size in BSS if
CONFIG_SYS_INIT_SP_BSS_OFFSET is enabled.
This check, however, doesn't make sense under the configuration where
control dtb won't be built in and it should be void in
Hi Sean
> For clocks not in the CCF, their parents will not have UCLASS_CLK, so we
> just enable them as normal. The enable count is local to the struct clk,
> but this will never result in the actual en-/dis-able op being called
> (unless the same struct clk is enabled twice).
>
> For clocks in
Hi Sean
> The Fully-Programmable Input/Output Array (FPIOA) device controls pin
> multiplexing on the K210. The FPIOA can remap any supported function to any
> multifunctional IO pin. It can also perform basic GPIO functions, such as
> reading the current value of a pin.
>
> Signed-off-by: Sean
On 04. 03. 20 3:47, Simon Glass wrote:
> Hi Michal,
>
> On Mon, 2 Mar 2020 at 23:52, Michal Simek wrote:
>>
>> On 02. 03. 20 20:47, Simon Glass wrote:
>>> Hi Michal,
>>>
>>> On Fri, 28 Feb 2020 at 04:03, Michal Simek wrote:
On 26. 02. 20 16:33, Simon Glass wrote:
> Hi Michal,
Peng,
On 26/02/20 4:31 pm, Jaehoon Chung wrote:
> Hi Faiz,
>
> On 2/26/20 5:14 PM, Faiz Abbas wrote:
>> The following patches add support for eMMC boot in TI's Am65x and J721e
>> devices.
>
> About adding deferred_probe(), i want to know Peng's opinion.
> But it's my preference. I will review
Hi Sean
> Some older processors (notably the Kendryte K210) use an older version of
> the RISC-V privileged specification. The primary changes between the old
> and new are in virtual memory, and in the merging of three separate counter
> enable CSRs. Using the new CSR on an old processor causes
Hi Jagan,
> -Original Message-
> From: Kuldeep Singh
> Sent: Thursday, February 20, 2020 10:58 PM
> To: u-boot@lists.denx.de
> Cc: Frieder Schrempf ; Stefan Roese
> ; Priyanka Jain ; Jagan Teki
> ; Stefano Babic ; Fabio
> Estevam ; Vignesh Raghavendra ;
> Kuldeep Singh ; Ashish Kumar
>
Hi Sean
> Some devices have different layouts for the fields in CTRL1 (e.g. the
Still not fix this typo in commit message
CTRL1 -> CTRL0
Thanks,
Rick
> Kendryte K210). Allow this layout to be configurable from the device tree.
> The documentation has been taken from Linux.
>
> Signed-off-by:
Hi Sean
> The Sipeed Maix series is a collection of boards built around the RISC-V
> Kendryte K210 processor. This processor contains several peripherals to
> accelerate neural network processing and other "ai" tasks. This includes a
> "KPU" neural network processor, an audio processor supporting
On 04/03/20 10:10 am, Lokesh Vutla wrote:
On 04/03/20 10:09 AM, Keerthy wrote:
The patch series enables he OSPI1 aka QSPI node.
This is a precursor for enabling QSPI boot on j721e.
How did you test this using R5 defconig?
#define CONFIG_SF_DEFAULT_BUS 1
So as to force SPI
On 04/03/20 10:09 AM, Keerthy wrote:
> The patch series enables he OSPI1 aka QSPI node.
> This is a precursor for enabling QSPI boot on j721e.
How did you test this using R5 defconig?
Thanks and regards,
Lokesh
Add ospi1 flash node required for QSPI boot.
Signed-off-by: Keerthy
---
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index
Enable the ospi1/qspi for both r5 and a72 configurations.
Signed-off-by: Keerthy
---
Changes in v2:
* Moved the pin definitions out of u-boot.dtsi to r5 and a72
based dts files.
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 12
Add assigned-clocks/rates properties for ospi1/qspi.
This is the expected rate as per ROM configuration.
Signed-off-by: Keerthy
---
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
The patch series enables he OSPI1 aka QSPI node.
This is a precursor for enabling QSPI boot on j721e.
Changes in v2:
* Moved the pin definitions out of u-boot.dtsi to r5 and a72
based dts files.
Keerthy (3):
arm: dts: k3-j721e: Enable ospi1/qspi
arm: dts: k3-j721e-mcu-wakeup: Add
>
> This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A
Hi Priyanka,
Any comments?
Best Regards,
Biwen Li
>
> Reviewed-by: Priyanka Jain
> Signed-off-by: Biwen Li
> ---
> Changes in RESEND v8:
> - fix build warning
>
> Changes in v8:
> - none
>
> Changes in v7:
>
>
> This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A
Hi Priyanka,
Any coments?
Best Regards,
Biwen Li
>
> Reviewed-by: Priyanka Jain
> Signed-off-by: Biwen Li
> ---
> Changes in RESEND v8:
> - fix build warning
>
> Changes in v8:
> - none
>
> Changes in v7:
>
Hi Andy,
On Tue, 3 Mar 2020 at 02:23, Andy Shevchenko wrote:
>
> On Tue, Mar 3, 2020 at 1:36 AM Simon Glass wrote:
> > On Mon, 2 Mar 2020 at 13:47, Andy Shevchenko
> > wrote:
> > > On Mon, Mar 2, 2020 at 9:47 PM Simon Glass wrote:
> > > > On Fri, 28 Feb 2020 at 01:47, Andy Shevchenko
> > >
Hi Michal,
On Mon, 2 Mar 2020 at 23:52, Michal Simek wrote:
>
> On 02. 03. 20 20:47, Simon Glass wrote:
> > Hi Michal,
> >
> > On Fri, 28 Feb 2020 at 04:03, Michal Simek wrote:
> >>
> >> On 26. 02. 20 16:33, Simon Glass wrote:
> >>> Hi Michal,
> >>>
> >>> On Tue, 18 Feb 2020 at 09:02, Michal
The first patch simplifies the Kconfig for hardware RNG drivers and enables
the Sandbox RNG driver for all Sandbox instances.
The second introduces a hardware random number generator driver for Amlogic
SOCs. This second patch had been sent before but the preceding patch was
missing.
Heinrich
For all sandbox systems with DM_RNG we enable RNG_SANDBOX. So we can simply
set the default to yes.
All rng drivers depend on DM_RNG. Use a single 'if' instead of individual
dependencies. Now 'make menuconfig' shows the individual drivers neatly
indented under the DM_RNG entry.
Signed-off-by:
Add support for the hardware random number generator of Amlogic SOCs.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Neil Armstrong
Reviewed-by: Sughosh Ganu
---
Resent
---
drivers/rng/Kconfig | 8 +++
drivers/rng/Makefile| 1 +
drivers/rng/meson-rng.c | 120
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.
Signed-off-by: Kever Yang
Reviewed-by: Ramon Fried
---
Changes in v3: None
drivers/usb/host/ehci-msm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/usb/host/ehci-msm.c
This patch set convert to use APIs leading with dev_ or ofnode_ which
supports live DT instead of fdt_ or fdtdec or devfdt_.
Two functions update there parameter from offset to ofnode:
- usb_get_maximum_speed()
- usb_get_dr_mode()
For V3 update:
Squesh patch 3rd~9th/9 into one patch because the
Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT.
This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use
ofnode as parameter instead of fdt offset. And all the drivers who use
these APIs update to use live dt APIs at the same time.
Signed-off-by: Kever
The fdtdec.h is no use in this file, remove the include code.
Signed-off-by: Kever Yang
---
Changes in v3: None
drivers/usb/host/dwc3-of-simple.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host/dwc3-of-simple.c
b/drivers/usb/host/dwc3-of-simple.c
index
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, March 3, 2020 8:13 PM
> To: Ley Foon Tan
> Cc: Tan, Ley Foon ; u-boot@lists.denx.de; Simon
> Goldschmidt ; See, Chin Liang
> ; Chee, Tien Fong
> Subject: Re: [PATCH] arm: socfpga: arria10: Add save_boot_params()
>
> On 3/3/20
Hi Tom,
The following changes since commit 8aad16916d04e3db0d1652cb96e840e209e19252:
Merge tag 'u-boot-stm32-20200203' of
https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2020-03-02
09:20:30 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-dm.git
On 3/3/20 4:53 PM, Lukas Auer wrote:
> On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote:
>> On 3/2/20 6:17 PM, Lukas Auer wrote:
>>> Don't move this. It is intended to be run before the IPI is cleared.
>>
>> Hm, ok. I think I moved it to after because of the 'if (!smp_function)'
>> check,
On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote:
> On 3/2/20 6:17 PM, Lukas Auer wrote:
> > On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote:
> >
> > > The IPI code could have race conditions in several places.
> > > * Several harts could race on the value of gd->arch->clint/plic
> >
On 2/19/20 7:55 PM, Marek Vasut wrote:
> From: Holger Brunck
>
> Add initial support for the ABB SECU board, which is an ArriaV-based
> SoCFPGA system with ethernet and booting from Denali NAND.
>
> Signed-off-by: Holger Brunck
> Cc: Ley Foon Tan
> Cc: Simon Goldschmidt
> ---
> V2: Use
Linux has good support for Toshiba SPI-NAND, so lets import it.
Signed-off-by: Robert Marko
Tested-by: Luka Kovacic
Cc: Luka Perkov
---
Changes from v1:
Refresh to apply due to free() to rfree() rename
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c| 1 +
Toshiba recently launched new revisions of their serial SLC NAND series.
TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements.
Basic parameters are same so lets add support for this new revision.
Datasheet:
https://business.kioxia.com/info/docget.jsp?did=58601=TC58CVG2S0HRAIJ
Hi,
Is there any way to see the traceability or registers by the command line
of the secure boot on my imx8m mini board with u-boot?
Thanks
Iñigo
commit 37304aaf60bf ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to
Kconfig") intended to support CONFIG_PREBOOT, but
include/configs/sunxi-common.h hardcodes preboot as part of internally
defined CONSOLE_STDIN_SETTINGS, silently ignoring any board-specific
CONFIG_PREBOOT.
This commit moves
A64-Teres-I board is a laptop which comes with a builtin keyboard.
The keyboard+trackpad controller pauses for 2 seconds at a firmware
prompt before loading its HID interface.
U-Boot needs to wait equally long to reliably enable the keyboard.
Tested-by: Jonas Smedegaard
Signed-off-by: Jonas
On 03. 03. 20 15:52, Andy Shevchenko wrote:
> On Tue, Mar 3, 2020 at 2:03 PM Michal Simek wrote:
>> On 03. 03. 20 10:37, Andy Shevchenko wrote:
>>> On Mon, Mar 2, 2020 at 10:36 AM Michal Simek
>>> wrote:
>
Base autodetection is failing for this case:
if test 257 -gt 3ae; then echo
On Tue, Mar 3, 2020 at 12:00 PM Wolfgang Wallner
wrote:
...
> > Wait, this is not a *name*, this is ACPI _HID. ACPI _HID, of course,
> > should be somewhere in board code.
> >
> > I was thinking myself about some U-Boot framework that actually takes
> > ACPI _HID from the driver. So, when you
Hi Andre,
Quoting Andre Przywara (2020-03-02 10:51:08)
> On Sat, 29 Feb 2020 16:58:55 +0100
> Jonas Smedegaard wrote:
>
> Hi Jonas,
>
> > commit 37304aaf60bf ("Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to
> > Kconfig") intended to support CONFIG_PREBOOT, but
> >
On Tue, Mar 3, 2020 at 2:03 PM Michal Simek wrote:
> On 03. 03. 20 10:37, Andy Shevchenko wrote:
> > On Mon, Mar 2, 2020 at 10:36 AM Michal Simek
> > wrote:
> >> Base autodetection is failing for this case:
> >> if test 257 -gt 3ae; then echo first; else echo second; fi
> >>
> >> It is because
On 3/3/20 1:58 AM, Rick Chen wrote:
> Hi Sean
>
>> This header is needed outside of the arm architecture for the designware
>> watchdog.
>>
>> Signed-off-by: Sean Anderson
>> Reviewed-by: Simon Glass
>> ---
>> This patch previously appeared as
>> https://patchwork.ozlabs.org/patch/1232411/
>>
On 3/3/20 12:25 AM, Lukasz Majewski wrote:
> Hi Marek,
Hi,
[...]
Every read operation starts at the maximum block size. When the USB
pendrive is not able to correctly serve this data read request, the
dynamic reduction of IO size is performed. Up to six tries (with
smaller
On 03. 03. 20 8:47, Michael Walle wrote:
> If there are aliases for an uclass, set the base for the "dynamically"
> allocated numbers next to the highest alias.
>
> Please note, that this might lead to holes in the sequences, depending
> on the device tree. For example if there is only an alias
On 28/01/2020 13.04, Rasmus Villemoes wrote:
> [resending with Mario's correct address, sorry for the double post]
>
> The driver correctly uses the shadow register when asked for the
> current value of an output gpio. Unfortunately, it does RMW on the
> gpdat register both when setting a gpio as
On 3/3/20 10:14 AM, Ley Foon Tan wrote:
> On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
>>
>> On 3/2/20 8:20 AM, Tan, Ley Foon wrote:
>> Hi,
>>
>> [...]
>>
On 2/26/20 8:01 PM, Ley Foon Tan wrote:
[...]
> +#define BOOTROM_SHARED_MEM_ADDR
(CONFIG_SYS_INIT_RAM_ADDR +
On 3/3/20 10:21 AM, Ley Foon Tan wrote:
> On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
>>
>> On 3/2/20 10:33 AM, Ley Foon Tan wrote:
>>> On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan wrote:
Add QSPI boot settings for Arria 10 SoCDK.
Signed-off-by: Ley Foon Tan
---
On 03. 03. 20 10:37, Andy Shevchenko wrote:
> On Mon, Mar 2, 2020 at 10:36 AM Michal Simek wrote:
>>
>> Base autodetection is failing for this case:
>> if test 257 -gt 3ae; then echo first; else echo second; fi
>>
>> It is because base for 3ae is recognized by _parse_integer_fixup_radix() as
>>
On 02. 03. 20 17:28, Tom Rini wrote:
> On Mon, Mar 02, 2020 at 08:14:14AM +0100, Michal Simek wrote:
>
>> Hi Tom,
>>
>> please pull these fixes to your tree. There is one rename patch I am
>> considering more as a fix and will be used much more in next version
>> when I am going to remove xilinx
On Mon, Mar 2, 2020 at 1:22 PM Patrick Delaunay wrote:
>
> Display TEE version at information level; this patch replaces
> debug() call to dev_info() in print_os_revision() function.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> drivers/tee/optee/core.c | 13 +++--
> 1 file changed, 7
Hi,
On 3/3/2020 4:04 PM, Keerthy wrote:
> Enable the ospi1/qspi module while at it move the corresponding
> pins to common u-boot.dtsi file.
>
> Signed-off-by: Keerthy
> ---
> .../k3-j721e-common-proc-board-u-boot.dtsi| 23 +++
> arch/arm/dts/k3-j721e-common-proc-board.dts
Hi,
> Indeed, but it's here to not give false impressions: Despite the joint code,
> the clock driver only works for one SoC at a time. Having only that one
> respective compatible string in here makes this obvious.
>
> The main reason for this approach is that the register offsets are quite
>
Add assigned-clocks/rates properties for ospi1/qspi.
This is the expected rate as per ROM configuration.
Signed-off-by: Keerthy
---
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
Add ospi1 flash node required for QSPI boot.
Signed-off-by: Keerthy
---
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 25 +++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index
Enable the ospi1/qspi module while at it move the corresponding
pins to common u-boot.dtsi file.
Signed-off-by: Keerthy
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 23 +++
arch/arm/dts/k3-j721e-common-proc-board.dts | 13 ---
2 files changed, 23 insertions(+),
The patch series enables he OSPI1 aka QSPI node.
This is a precursor for enabling QSPI boot on j721e.
Keerthy (3):
arm: dts: k3-j721e-common-proc-board-u-boot: Enable ospi1/qspi
arm: dts: k3-j721e-mcu-wakeup: Add assigned-clocks/rates properties
for ospi1/qspi
arm: dts:
On Sat, 25 Jan 2020 17:52:57 +0530
Amit Singh Tomar wrote:
Hi,
> The simplest and most generic form of a reset controller just exposes
> multiple MMIO registers, where each bit toggles a separate reset line.
> Add a generic driver to describe this kind of reset controller.
>
> This is used on
On 23/02/2020 17:25, Manivannan Sadhasivam wrote:
Hi,
> On Sat, Jan 25, 2020 at 05:52:45PM +0530, Amit Singh Tomar wrote:
>> This patch converts S900 clock driver to something common that can
>> be used for other SoCs, for instance S700(few of clk registres are same).
>>
>
> registers
>
>>
Hi Andy,
-"U-Boot" schrieb: -
>
> [snip]
>
> > > > > P.S. Briefly looking at the last ~30 patches I can say that the idea
> > > > > looks good, implementation needs more work. For example, there is
> > > > > 'linux,name' property. Shouldn't be referred at all. Linux names and
> > > > >
On Mon, Mar 2, 2020 at 10:36 AM Michal Simek wrote:
>
> Base autodetection is failing for this case:
> if test 257 -gt 3ae; then echo first; else echo second; fi
>
> It is because base for 3ae is recognized by _parse_integer_fixup_radix() as
> 10. The patch is checking all chars to make sure that
On Tue, Mar 3, 2020 at 1:36 AM Simon Glass wrote:
> On Mon, 2 Mar 2020 at 13:47, Andy Shevchenko
> wrote:
> > On Mon, Mar 2, 2020 at 9:47 PM Simon Glass wrote:
> > > On Fri, 28 Feb 2020 at 01:47, Andy Shevchenko
> > > wrote:
> > > > On Fri, Feb 28, 2020 at 1:41 AM Simon Glass wrote:
> > > >
On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
>
> On 3/2/20 10:33 AM, Ley Foon Tan wrote:
> > On Fri, Feb 21, 2020 at 9:25 AM Ley Foon Tan wrote:
> >>
> >> Add QSPI boot settings for Arria 10 SoCDK.
> >>
> >> Signed-off-by: Ley Foon Tan
> >> ---
> >> include/configs/socfpga_arria10_socdk.h
On Mon, Mar 2, 2020 at 6:40 PM Marek Vasut wrote:
>
> On 3/2/20 8:20 AM, Tan, Ley Foon wrote:
> Hi,
>
> [...]
>
> >> On 2/26/20 8:01 PM, Ley Foon Tan wrote:
> >> [...]
> >>> +#define BOOTROM_SHARED_MEM_ADDR
> >> (CONFIG_SYS_INIT_RAM_ADDR + 0x4 \
> >>> +
Hi Peter,
On 2020/3/2 下午3:57, Peter Robinson wrote:
These boards aren't ChromeOS devices so won't have a cros-ec-keyb
input as it's the keyboard available via the ChromeOS Embedded
Controller. Update them to use a USB keyboard which would actually
be available. Also enable the usb keyboard
Hi Masahiro,
On 2020/2/25 上午1:24, Masahiro Yamada wrote:
'uint' is not a primitive type. You need to include
or otherwise change it to (unsigned int).
Signed-off-by: Masahiro Yamada
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/debug_uart.h | 20 ++--
1 file
Hi,
> So either you send this patch to the kernel first, or, probably better, you
> drop this change here, and unify the name at the point where it's used
> (#ifndef CLK_ETHERNET )
But this is something mentioned in cover letter:
"Patch(9/21) uses same name for ethernet clock binding and
Hi Sean
> On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote:
>
> > On 3/2/20 4:08 AM, Rick Chen wrote:
> > > Hi Sean
> > >
> > > > The IPI code could have race conditions in several places.
> > > > * Several harts could race on the value of gd->arch->clint/plic
> > > > * Non-boot harts could
Hi,
Thanks for having a look.
> Either use `priv->soc` or the guard throughout the driver. Please don't mix
> both.
But have used #ifdef guard only where it is really necessary and to
keep implementation
clean used priv->soc.
> > +
> > +static const struct udevice_id owl_clk_ids[] = {
> > +#if
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