There is no need to clear reset reason register because it is protected by
PMUFW already which is reported when verbose log is enabled as:
pm_core.c@733 APU> No write permission to 0xFF5E0220
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 6 +-
1 file changed, 1
On 2/9/21 7:48 AM, Heinrich Schuchardt wrote:
Am 9. Februar 2021 07:19:48 MEZ schrieb Asherah Connor :
PE section table entries' SizeOfRawData must be a multiple of
FileAlignment, and thus may be rounded up and larger than their
VirtualSize.
We should not load beyond the VirtualSize, which is
Hi Tom,
I have tested this patch with Aspeed SDK as well as the U-Boot mainline
codebase on AST2500/AST2600 EVBs.
Both AST2500/AST2600 can boot to kernel normally. Thanks.
Chiawei
Tested-by: Chia-Wei Wang
> -Original Message-
> From: Tom Rini
> Sent: Thursday, February 4, 2021 10:24
Hello Patrick,
On 08.02.21 17:56, Patrick DELAUNAY wrote:
> Hi Heiko,
>
>
> On 2/8/21 12:38 PM, Heiko Schocher wrote:
>> add support for the UUU commands ACmd and UCmd.
>>
>> Enable them through the Kconfig option
>> CONFIG_FASTBOOT_UUU_SUPPORT
>>
>> base was commit in NXP kernel
>>
On 9/02/21 3:07 pm, Marek Behun wrote:
> On Tue, 9 Feb 2021 01:08:54 +
> Chris Packham wrote:
>
>> On 9/02/21 1:16 pm, Chris Packham wrote:
>>> On 9/02/21 9:18 am, Marek Behun wrote:
On Mon, 8 Feb 2021 20:11:06 +
Chris Packham wrote:
> Hi Marek,
>
> Do you
Am 9. Februar 2021 07:19:48 MEZ schrieb Asherah Connor :
>PE section table entries' SizeOfRawData must be a multiple of
>FileAlignment, and thus may be rounded up and larger than their
>VirtualSize.
>
>We should not load beyond the VirtualSize, which is "the total size of
>the section when loaded
Am 9. Februar 2021 06:30:31 MEZ schrieb AKASHI Takahiro
:
>On Mon, Feb 08, 2021 at 09:29:43PM -0700, Simon Glass wrote:
>> Hi Heinrich,
>>
>> On Mon, 8 Feb 2021 at 15:06, Heinrich Schuchardt
>wrote:
>> >
>> > UEFI test files like helloworld.efi require an architecture
>specific
>> > PE-COFF
Am 9. Februar 2021 05:29:43 MEZ schrieb Simon Glass :
>Hi Heinrich,
>
>On Mon, 8 Feb 2021 at 15:06, Heinrich Schuchardt
>wrote:
>>
>> UEFI test files like helloworld.efi require an architecture specific
>> PE-COFF header.
>
>architecture-specific
>
>>
>> For non-sandbox the PE-COFF header is
Hi Pratyush,
Thank you for the feedback. I will address this in v5.
On 1/30/2021 3:49 AM, Pratyush Yadav wrote:
> Hi,
>
> On 28/01/21 01:36PM, tkuw584...@gmail.com wrote:
>> From: Takahiro Kuwano
>>
>> For dual/quad die package devices from Spansion/Cypress, the device's
>> status needs to be
Hi Pratyush,
On 1/30/2021 3:40 AM, Pratyush Yadav wrote:
> Hi,
>
> On 28/01/21 01:36PM, tkuw584...@gmail.com wrote:
>> From: Takahiro Kuwano
>>
>> Some of Spansion/Cypress chips support volatile version of configuration
>> registers and it is recommended to update volatile registers in the
On 1/30/2021 3:17 AM, Pratyush Yadav wrote:
> On 28/01/21 01:36PM, tkuw584...@gmail.com wrote:
>> From: Takahiro Kuwano
>>
>> Some of Spansion/Cypress chips support Read/Write Any Register commands.
>> These commands are mainly used to write volatile registers and access to
>> the registers in
Hi Pratyush,
On 1/30/2021 3:08 AM, Pratyush Yadav wrote:
> On 28/01/21 01:36PM, tkuw584...@gmail.com wrote:
>> From: Takahiro Kuwano
>>
>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
>> The datasheets can be found in the following links.
>>
>>
On Mon, Feb 08, 2021 at 09:29:43PM -0700, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 8 Feb 2021 at 15:06, Heinrich Schuchardt wrote:
> >
> > UEFI test files like helloworld.efi require an architecture specific
> > PE-COFF header.
>
> architecture-specific
>
> >
> > For non-sandbox the
From: Bharat Gooty
Add tuning functionality which is needed for HS200 mode.
For HS200, program the correct needed 1.8 voltage
Signed-off-by: Bharat Gooty
Signed-off-by: Rayagonda Kokatanur
---
drivers/mmc/iproc_sdhci.c | 88 +++
1 file changed, 79
Hi Marek,
On Mon, 8 Feb 2021 at 19:49, Marek Behún wrote:
>
> Add functions ofnode_get_addr_size_index_notrans(), which is a
> non-translating version of ofnode_get_addr_size_index().
>
> Some addresses are not meant to be translated, for example those of MTD
> fixed-partitions.
>
>
Hi Heinrich,
On Mon, 8 Feb 2021 at 15:06, Heinrich Schuchardt wrote:
>
> UEFI test files like helloworld.efi require an architecture specific
> PE-COFF header.
architecture-specific
>
> For non-sandbox the PE-COFF header is chosen by the target architecture.
> For the sandbox we use the host
Hi Stefano.
On Thu, 28 Jan 2021 at 02:24, Stefano Babic wrote:
>
> Hi Simon,
>
> On 27.01.21 22:31, Simon Glass wrote:
> > Hi Stefano,
> >
> > Thank you for the offer!
> >
> > What are the advantages of hosting the meeting on a private server?
>
> No, I do not see any special advantage - I will
Hi Patrick,
On Mon, 8 Feb 2021 at 10:33, Patrick DELAUNAY
wrote:
>
> Hi Simon,
>
> 2 minor remarks,
>
> On 2/5/21 5:22 AM, Simon Glass wrote:
> > It is convenient to be able to adjust some of the flags for a GPIO while
> > leaving others alone. Add a function for this.
> >
> > Update
Hi Heinrich,
On Mon, 8 Feb 2021 at 15:18, Heinrich Schuchardt wrote:
>
> On 2/8/21 6:56 PM, Heinrich Schuchardt wrote:
> > On 2/8/21 6:08 PM, Simon Glass wrote:
> >> HI Marek,
> >>
> >> On Mon, 8 Feb 2021 at 09:10, Marek Szyprowski
> >> wrote:
> >>>
> >>> Hi Simon,
> >>>
> >>> On 06.02.2021
Add support for stack protector for UBOOT, SPL, and TPL
as well as new pytest for stackprotector
Signed-off-by: Joel Peshkin
---
Cc: Simon Glass
Cc: Heinrich Schuchardt
Changes for v9:
- Fix pytest script post-test reboot
Changes for v8:
- Fix commit message
- Force canary to UL type
On 2/8/21 7:42 PM, Andre Przywara wrote:
> On Sun, 7 Feb 2021 23:57:23 -0600
> Samuel Holland wrote:
>
> (CC:ing Simon and Kever)
>
>> Some platforms, like the Allwinner H6, do not have a separate glue layer
>> around the dwc3. Instead, they rely on the clocks/resets/phys referenced
>> from
The device_probe() function does the same thing as mtd_probe() and
mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the
probing can be made simpler by using uclass_foreach_dev_probe macro.
Signed-off-by: Marek Behún
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko
Fill in mtd->dev member with nor->dev.
This can be used by MTD OF partition parser.
Signed-off-by: Marek Behún
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
---
drivers/mtd/spi/sf_mtd.c | 1 +
drivers/mtd/spi/spi-nor-core.c | 1 +
In order for `mtd list` U-Boot command to list SPI NOR devices without
the need to run `sf probe` before, we have to probe SPI NOR devices in
mtd_probe_devices().
Signed-off-by: Marek Behún
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
---
Add support for parsing partitions defined in device-trees via the
`partitions` node with `fixed-partitions` compatible.
The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions
are defined for a MTD device via this mechanism, the code won't register
partitions for that MTD device
Currently when the SPI_FLASH_MTD config option is enabled, only one SPI
can be registered as MTD at any time - it is the last one probed (since
with old non-DM model only one SPI NOR could be probed at any time).
When DM is enabled, allow for registering multiple SPI NORs as MTDs by
utilizing the
Add functions ofnode_get_addr_size_index_notrans(), which is a
non-translating version of ofnode_get_addr_size_index().
Some addresses are not meant to be translated, for example those of MTD
fixed-partitions.
Signed-off-by: Marek Behún
Cc: Dario Binacchi
Cc: Simon Glass
---
Hello,
this patchset adds support for U-Boot to parse MTD partitions from
device-tree, and also improves support for SPI NOR access via the `mtd`
command.
Marek
Cc: Tom Rini
Cc: Dario Binacchi
Cc: Jagan Teki
Cc: Priyanka Jain
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Jagan Teki
Marek Behún
The SPI NOR flash node name in main device tree for Turris Omnia is
called `spi-nor@0`.
Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0
so that U-Boot does not try to probe the same SPI NOR device multiple
times.
Signed-off-by: Marek Behún
Cc: Stefan Roese
---
On 2/8/21 8:27 PM, Samuel Holland wrote:
> On 2/8/21 5:43 AM, Marek Vasut wrote:
>> On 2/8/21 6:57 AM, Samuel Holland wrote:
>>> Resetting an XHCI controller inside xhci_register undoes any register
>>> setup performed by the platform driver. And at least on the Allwinner
>>> H6, resetting the
On 2/8/21 5:43 AM, Marek Vasut wrote:
> On 2/8/21 6:57 AM, Samuel Holland wrote:
>> Resetting an XHCI controller inside xhci_register undoes any register
>> setup performed by the platform driver. And at least on the Allwinner
>> H6, resetting the XHCI controller also resets the PHY, which
On Tue, Feb 09, 2021 at 01:37:54AM +0200, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> Replace CONFIG_DM_I2C undefs with CONFIG_SPL_DM_I2C for the SPL build
> case. This should be moved to appropriate board defconfigs
> in the future.
>
> Signed-off-by: Igor Opaniuk
> ---
>
> (no changes
On 9/02/21 3:07 pm, Marek Behun wrote:
> On Tue, 9 Feb 2021 01:08:54 +
> Chris Packham wrote:
>
>> On 9/02/21 1:16 pm, Chris Packham wrote:
>>> On 9/02/21 9:18 am, Marek Behun wrote:
On Mon, 8 Feb 2021 20:11:06 +
Chris Packham wrote:
> Hi Marek,
>
> Do you
On Tue, 9 Feb 2021 01:08:54 +
Chris Packham wrote:
> On 9/02/21 1:16 pm, Chris Packham wrote:
> > On 9/02/21 9:18 am, Marek Behun wrote:
> >> On Mon, 8 Feb 2021 20:11:06 +
> >> Chris Packham wrote:
> >>
> >>> Hi Marek,
> >>>
> >>> Do you have this in a repo I can pull from? I've got
On Sun, 7 Feb 2021 23:57:18 -0600
Samuel Holland wrote:
Hi Samuel,
> This series adds clock, PHY, and XHCI driver support for the USB3
> controller found in the Allwinner H6 SoC. Below is a log showing it
> functioning on the Orange Pi 3.
Many thanks for sharing this! The lack of USB 3.0
On Sun, 7 Feb 2021 23:57:24 -0600
Samuel Holland wrote:
Hi,
(CC:ing Maxime and Chen-Yu)
> Pine H64 and Orange Pi 3 both provide a USB3 type A port.
> Enable it in U-Boot.
>
> Signed-off-by: Samuel Holland
That looks good to me, but the Pine H64 does not enable the USB
3.0 controller in its
On Sun, 7 Feb 2021 23:57:23 -0600
Samuel Holland wrote:
(CC:ing Simon and Kever)
> Some platforms, like the Allwinner H6, do not have a separate glue layer
> around the dwc3. Instead, they rely on the clocks/resets/phys referenced
> from the dwc3 DT node itself. Add support for enabling the
On Mon, 8 Feb 2021 12:43:52 +0100
Marek Vasut wrote:
(CC:ing Masahiro, Manni and Kever)
> On 2/8/21 6:57 AM, Samuel Holland wrote:
> > Resetting an XHCI controller inside xhci_register undoes any register
> > setup performed by the platform driver. And at least on the Allwinner
> > H6,
On Sun, 7 Feb 2021 23:57:21 -0600
Samuel Holland wrote:
Hi,
> This driver is needed for XHCI to work on the Allwinner H6 SoC. The
> driver is copied from Linux v5.10.
>
> Signed-off-by: Samuel Holland
Compared against the Linux driver, also against the version I made
myself a few months ago
On Sun, 7 Feb 2021 23:57:20 -0600
Samuel Holland wrote:
> The XHCI controller has its own clock and reset. Add them.
>
> Signed-off-by: Samuel Holland
Checked against the manual:
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/clk/sunxi/clk_h6.c | 2 ++
> 1 file changed, 2
On 9/02/21 1:16 pm, Chris Packham wrote:
> On 9/02/21 9:18 am, Marek Behun wrote:
>> On Mon, 8 Feb 2021 20:11:06 +
>> Chris Packham wrote:
>>
>>> Hi Marek,
>>>
>>> Do you have this in a repo I can pull from? I've got a couple of boards
>>> I can give this a spin on.
>>
On 9/02/21 9:18 am, Marek Behun wrote:
> On Mon, 8 Feb 2021 20:11:06 +
> Chris Packham wrote:
>
>> Hi Marek,
>>
>> Do you have this in a repo I can pull from? I've got a couple of boards
>> I can give this a spin on.
> https://gitlab.nic.cz/turris/turris-omnia-uboot/
> branch
From: Igor Opaniuk
Use CONFIG_IS_ENABLED() macro, which provides more convenient
way to check $(SPL)DM_I2C/$(SPL)DM_I2C_GPIO configs
for both SPL and U-Boot proper.
CONFIG_IS_ENABLED(DM_I2C) expands to:
- 1 if CONFIG_SPL_BUILD is undefined and CONFIG_DM_I2C is set to 'y',
- 1 if
From: Igor Opaniuk
At present if U-Boot proper uses driver model for I2C, then SPL has to
also. While this is desirable, it places a significant barrier to moving
to driver model in some cases. For example, with a space-constrained SPL
it may be necessary to enable CONFIG_SPL_OF_PLATDATA which
Hi Patrick,
On Mon, 8 Feb 2021 at 11:13, Patrick DELAUNAY
wrote:
>
> Hi Simon,
>
> On 2/5/21 5:22 AM, Simon Glass wrote:
> > Using the internal vs. external pull resistors it is possible to get
> > 27 different combinations from 3 strapping pins. Add an implementation
> > of this.
> >
> > This
From: Igor Opaniuk
At present if U-Boot proper uses driver model for I2C, then SPL has to
also. While this is desirable, it places a significant barrier to moving
to driver model in some cases. For example, with a space-constrained SPL
it may be necessary to enable CONFIG_SPL_OF_PLATDATA which
From: Igor Opaniuk
Replace CONFIG_DM_I2C undefs with CONFIG_SPL_DM_I2C for the SPL build
case. This should be moved to appropriate board defconfigs
in the future.
Signed-off-by: Igor Opaniuk
---
(no changes since v1)
include/configs/T104xRDB.h | 2 +-
include/configs/imx8mp_evk.h
Hi Patrick,
On Mon, Feb 8, 2021 at 5:06 PM Patrick DELAUNAY
wrote:
>
> Hi Igor,
>
> On 1/24/21 10:39 AM, Igor Opaniuk wrote:
> > From: Igor Opaniuk
> >
> > Add support for rpmb-dev property in optee node.
> > Prioritize that provided eMMC info from DT for RPMB operations over
> > the one
On Monday 08 February 2021 23:45:37 Marek Vasut wrote:
> On 2/8/21 11:34 PM, Pali Rohár wrote:
> > On Monday 08 February 2021 23:21:38 Pali Rohár wrote:
> > > On Monday 08 February 2021 23:15:33 Lukasz Majewski wrote:
> > > > Hi Pali,
> > > >
> > > > > Resended v2 patch series with fixed
On 2/8/21 11:34 PM, Pali Rohár wrote:
On Monday 08 February 2021 23:21:38 Pali Rohár wrote:
On Monday 08 February 2021 23:15:33 Lukasz Majewski wrote:
Hi Pali,
Resended v2 patch series with fixed commit messages
This patch series fix usbtty code (serial console via USB peripheral
Hi Jesse,
this patch should have been squashed with patch 1/4 as already suggested.
On 2/8/21 1:24 AM, Jesse Taube wrote:
Signed-off-by: Jesse Taube
Cc: Stefano Babic
Cc: Giulio Benetti
Cc: Jesse Taube
This timer driver is using GPT Timer (General Purpose Timer) available
on almost all
On Monday 08 February 2021 23:21:38 Pali Rohár wrote:
> On Monday 08 February 2021 23:15:33 Lukasz Majewski wrote:
> > Hi Pali,
> >
> > > Resended v2 patch series with fixed commit messages
> > >
> > > This patch series fix usbtty code (serial console via USB peripheral
> > > mode), fix
On 2/8/21 11:18 PM, Heinrich Schuchardt wrote:
On 2/8/21 1:52 PM, Jose Marinho wrote:
The ESRT is initialised during efi_init_objlist after
efi_initialize_system_table().
The ESRT is initially created with size for 50 FW image entries.
The ESRT is resized when it runs out of space. Every
Subject should be:
ARM: dts: imxrt1050: add gpt1 node
Please try to:
# git log arch/arm/dts/imxrt1050.dtsi
this is to see the form already used to begin commit.
In general, try to imitate what others do in commited patches.
Best regards
--
Giulio Benetti
Benetti Engineering sas
On 2/8/21 1:24
On Monday 08 February 2021 23:15:33 Lukasz Majewski wrote:
> Hi Pali,
>
> > Resended v2 patch series with fixed commit messages
> >
> > This patch series fix usbtty code (serial console via USB peripheral
> > mode), fix underlying musb peripheral code, fix compilation of
> >
Hi Jesse,
On 2/8/21 1:24 AM, Jesse Taube wrote:
This timer driver is using GPT Timer (General Purpose Timer) available
on almost all i.MX SoCs family.
Signed-off-by: Giulio Benetti
Cc: Stefano Babic
Cc: Giulio Benetti
Cc: Jesse Taube
All these ^^^ Cc in commit log are useless in this
On 2/8/21 1:52 PM, Jose Marinho wrote:
The ESRT is initialised during efi_init_objlist after
efi_initialize_system_table().
The ESRT is initially created with size for 50 FW image entries.
The ESRT is resized when it runs out of space. Every resize adds 50
additional entries.
The ESRT is
Hi Pali,
> Resended v2 patch series with fixed commit messages
>
> This patch series fix usbtty code (serial console via USB peripheral
> mode), fix underlying musb peripheral code, fix compilation of
> CONFIG_USB_DEVICE (used by usbtty), remove unused Nokia RX-51 code to
> decrease size of
Hi Jesse,
first of all thank you for helping me with this porting :-)
On 2/8/21 1:24 AM, Jesse Taube wrote:
Add basic driver support for the IMX General Purpose Timer (GPT) available
on almost all i.MX SoCs family.
Giulio Benetti (3):
timer: imx-gpt: Add timer support for i.MX SoCs family
On 2/8/21 6:56 PM, Heinrich Schuchardt wrote:
On 2/8/21 6:08 PM, Simon Glass wrote:
HI Marek,
On Mon, 8 Feb 2021 at 09:10, Marek Szyprowski
wrote:
Hi Simon,
On 06.02.2021 17:21, Simon Glass wrote:
On Thu, 4 Feb 2021 at 03:36, Marek Szyprowski
wrote:
...
Could you give me a bit more
Stefan,
these patches should probably have a different From: - i.e. the
original authors should be preserved (from the first Signed-off-by
tags), for example:
motib
Baruch Siach
heaterC
But some of these are not full names, so I don't know whether I should
resend this or not.
What do
UEFI test files like helloworld.efi require an architecture specific
PE-COFF header.
For non-sandbox the PE-COFF header is chosen by the target architecture.
For the sandbox we use the host architecture. This is not helpful for cross
compiling. Allow specifying the target architecture of the
Reviewed-by: Marek Behún
Reviewed-by: Marek Behún
Reviewed-by: Marek Behún
Reviewed-by: Marek Behún
Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.
We can simplify the code by putting the validation into separate
function.
Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
(by default
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.
Signed-off-by: Marek Behún
Cc: Stefan Roese
Cc: Phil Sutter
Cc: Mario Six
Cc: Baruch Siach
---
drivers/pci/pci_mvebu.c | 4 ++--
1 file changed, 2 insertions(+), 2
Write bdf address in a same way in mvebu_pcie_read/write_config.
Signed-off-by: Marek Behún
Cc: Stefan Roese
Cc: Phil Sutter
Cc: Mario Six
Cc: Baruch Siach
---
drivers/pci/pci_mvebu.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci_mvebu.c
Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.
Let's do it also in U-Boot.
With this commit the pci command in U-Boot prints something like:
PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.
Signed-off-by: Marek Behún
Cc: Stefan Roese
Cc: Phil Sutter
Cc: Mario Six
Cc: Baruch Siach
---
drivers/pci/pci_mvebu.c |
Hi Stefan,
this patchset continues to address the issue you tried to solve with
commit "pci: pci_mvebu: Disable config access to PCI host bridge ports".
Some code refactoring is done here so that the code looks more sane and
the underlying information is documenter.
The last patch changes the
On 2/7/21 8:37 AM, Simon Glass wrote:
Hi Alexandru,
On Thu, 4 Feb 2021 at 12:56, Alexandru Gagniuc wrote:
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API
On Mon, Feb 08, 2021 at 12:41:45PM +0100, Stefan Roese wrote:
> Hi Tom,
>
> please pull the 2nd batch of Marvell MVEBU related patches. Here the
> summary log:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Mon, Feb 08, 2021 at 11:10:09AM +, Priyanka Jain wrote:
> Dear Tom,
>
> Please find my pull-request for u-boot-fsl-qoriq/master
> https://github.com/u-boot/u-boot/pull/52/checks
>
> Summary
> Layerscape: Enable gpio
> Bug fixes & updates related to dspi, qspi, pciep, SVR mask,
>
On Sun, Feb 07, 2021 at 09:41:32PM +0100, Marek Vasut wrote:
> The following changes since commit 3936fd998668846f77468d8f6a662e906920969c:
>
> Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2021-02-06
> 09:45:58 -0500)
>
> are available in the Git repository at:
>
>
On Sun, Feb 07, 2021 at 09:10:43PM +0100, Marek Vasut wrote:
> The following changes since commit 8308a28af821d6498186b3dd7463db9874cd2daf:
>
> Merge tag 'ti-v2021.04-rc2' of
> https://gitlab.denx.de/u-boot/custodians/u-boot-ti (2021-02-05 09:39:31
> -0500)
>
> are available in the Git
On Mon, 8 Feb 2021 20:14:26 +
Chris Packham wrote:
> On 9/02/21 8:15 am, Marek Behun wrote:
> > This patch is needed on some Turris Omnia boards with Samsung DDR chips,
> > otherwise DDR training fails in ~60% of cases.
> >
> > Marvell send us this patch for testing, I have updated it a
On 08/02/21, Simon Glass wrote:
> Hi Jorge,
>
> On Sun, 7 Feb 2021 at 11:11, Jorge Ramirez-Ortiz, Foundries
> wrote:
> >
> > On 07/02/21, Simon Glass wrote:
> > > Hi Jorge,
> > >
> > > On Sat, 6 Feb 2021 at 16:05, Jorge Ramirez-Ortiz
> > > wrote:
> > > >
> > > > Enable and provision the SCP03
On Mon, 8 Feb 2021 20:11:06 +
Chris Packham wrote:
> Hi Marek,
>
> Do you have this in a repo I can pull from? I've got a couple of boards
> I can give this a spin on.
https://gitlab.nic.cz/turris/turris-omnia-uboot/
branch v2021.04-rc-mv-ddr-14.0.0
also please test branch
On 9/02/21 8:15 am, Marek Behun wrote:
> This patch is needed on some Turris Omnia boards with Samsung DDR chips,
> otherwise DDR training fails in ~60% of cases.
>
> Marvell send us this patch for testing, I have updated it a little.
>
> Please test this on other A38x boards.
>
> If it doesn't
Hi Marek,
On 9/02/21 7:34 am, Marek Behún wrote:
> This syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch
> of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
>
> There are some commits regarding DDR3 on top of version 14.0.0 in the
> mv-ddr-marvell repository (from
This patch is needed on some Turris Omnia boards with Samsung DDR chips,
otherwise DDR training fails in ~60% of cases.
Marvell send us this patch for testing, I have updated it a little.
Please test this on other A38x boards.
If it doesn't break anything on other boards, we can apply it and
From: motib
In each pattern cycle the bus state can be changed.
In order to avoid it, we need to switch back to the same bus state on
each pattern cycle.
Signed-off-by: motib
Fixed code style, removed commented code, switched to use DEBUG macros
instead of printf.
Signed-off-by: Marek Behún
btw tested on Turris Omnia
commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.
@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So
The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.
Signed-off-by: Marek Behún
---
commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.
Import this change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/ddr3_training.c
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.
The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.
the twin-die combined memory device should be treatened as X8
device and not as X16 one
Signed-off-by: Moti Buskila
Reviewed-by: Kostya Porotchkin
The default value for twin_die_combined is set to NOT_COMBINED for all
boards, as this
commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.
WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.
Signed-off-by: Moti Buskila
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.
Signed-off-by: Moti Buskila
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++
drivers/ddr/marvell/a38x/mv_ddr_topology.c | 3 ++-
2 files changed, 4
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.
- function mv_ddr_spd_die_capacity_user_get() has a bug,
since it insert a user memory enum to it,
instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.
The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration
commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.
Signed-off-by: motib
Reviewed-by: Alex Leibovich
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
---
drivers/ddr/marvell/a38x/mv_ddr_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.
Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich
Reviewed-by: Kostya Porotchkin
Signed-off-by: Marek Behún
---
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún
---
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