On 4/2/21 2:15 AM, Jaehoon Chung wrote:
Provide a man-pages for the mmc command.
Signed-off-by: Jaehoon Chung
---
Changelog on V2
- Add missing empty line
- Add bootbus's arguments descriptions
---
doc/usage/index.rst | 1 +
doc/usage/mmc.rst | 212
On Sat, Mar 27, 2021 at 7:57 PM Bin Meng wrote:
>
> Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
> adds the official DT bindings for CLINT, which uses "sifive,clint0"
> as the compatible string. "riscv,clint0" is now legacy and has to
> be kept for backward
Provide a man-pages for the mmc command.
Signed-off-by: Jaehoon Chung
---
Changelog on V2
- Add missing empty line
- Add bootbus's arguments descriptions
---
doc/usage/index.rst | 1 +
doc/usage/mmc.rst | 212
2 files changed, 213 insertions(+)
Import the iMX53 based usbarmory dts files from Linux 5.12-rc1
Signed-off-by: Peter Robinson
Cc: Andrej Rosano
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/imx53-usbarmory.dts | 225 +++
2 files changed, 227
Convert usbarmory to OF_CONTROL and DM for gpio, pin
usb support on the i.MX53 based usbarmory.
Signed-off-by: Peter Robinson
Cc: Andrej Rosano
Cc: Fabio Estevam
Cc: Stefano Babic
---
configs/usbarmory_defconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git
Convert the UDOO Neo to ethernet DM support.
Signed-off-by: Peter Robinson
Cc: Francesco Montefoschi
Cc: Breno Lima
Cc: Fabio Estevam
Cc: Stefano Babic
---
board/udoo/neo/neo.c | 63 +++---
configs/udoo_neo_defconfig | 3 ++
include/configs/udoo_neo.h
Convert UDOO Neo to use DM MMC.
Signed-off-by: Peter Robinson
Cc: Francesco Montefoschi
Cc: Breno Lima
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi | 7 +
board/udoo/neo/neo.c | 39
Import the i.MX6SX based UDOO Neo dts files from Linux 5.12-rc1
and sync the i.MX6SX pinfunc.h
Signed-off-by: Peter Robinson
Cc: Francesco Montefoschi
Cc: Breno Lima
Cc: Fabio Estevam
Cc: Stefano Babic
---
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/imx6sx-pinfunc.h
Enable OF_CONTROL and DM for gpio and pin control support
on the i.MX6SX based Udoo Neo.
Signed-off-by: Peter Robinson
Cc: Francesco Montefoschi
Cc: Breno Lima
Cc: Fabio Estevam
Cc: Stefano Babic
---
configs/udoo_neo_defconfig | 8
1 file changed, 8 insertions(+)
diff --git
From: Takahiro Kuwano
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.
The spansion_erase_non_uniform() erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.
Further, even if you detect the
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before
On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then
256 KiB
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing.
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.
Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default
Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse"
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
reflect that.
The check for rev A or later compared the BFPT header length with the
maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
was the BFPT length for both rev A and B, this check worked fine. But
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
Even when spi_nor_write_reg() has no data to write, like when executing
a write enable operation, it sets the data direction to
SPI_MEM_DATA_OUT. This trips up spi_mem_check_buswidth() because it
expects a data phase when there is none. Make sure the data direction is
set to SPI_MEM_NO_DATA when
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit
The SPI NOR core will get Octal DTR in following commits. This has
presented a significant challenge of keeping the SPL size in check on
the x530 platform.
On a previous iteration of the series, adding a set of compile-time
switches got the build working. But rebasing on the latest master breaks
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
flashes. Reviving this series after a long hiatus.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721E
Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 3e5b771045..dc53b517c1 100644
--- a/include/spi-mem.h
+++
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index
Hi Chenguanqiao,
On Fri, 2 Apr 2021 at 01:26, chenguanqiao wrote:
>
> Add functions to add size of addresses in the device tree using ofnode
> references.
>
> Signed-off-by: Chen Guanqiao
> ---
> drivers/core/ofnode.c | 9 +
> include/dm/ofnode.h | 10 ++
> 2 files changed,
On Thu, Apr 01, 2021 at 07:36:14PM +0300, Andy Shevchenko wrote:
> On Thu, Apr 1, 2021 at 7:17 PM Herbert Poetzl wrote:
>> Hello Andy!
>> Thanks for the quick feedback!
>> On Thu, Apr 01, 2021 at 04:10:57PM +0300, Andy Shevchenko wrote:
>>> On Thu, Apr 1, 2021 at 2:19 PM Herbert Poetzl wrote:
OP-TEE images are normally packaged with
type = "tee;
os = "tee";
However, fit_image_load() thinks that is somehow invalid. However if
they were declared as type = "kernel", os = "linux", fit_image_load()
would happily accept them and allow the boot to continue. There is no
The information on the OS should be contained in the FIT, as the
self-explanatory "os" property of a node under /images. Hard-coding
this to U_BOOT might send us down the wrong path later in the boot
process.
Signed-off-by: Alexandru Gagniuc
---
common/spl/spl.c | 5 +++--
1 file changed, 3
Consider the following FIT:
images {
whipple {};
};
configurations {
conf-1 {
firmware = "whipple";
};
};
Getting the 'firmware' image with fit_image_load() is not possible, as
it doesn't
U-Boot expects the FDT to be located right after the _end
linker symbol (see fdtdec.c: board_fdt_blob_setup())
The "basic" LOAD_FIT path is aware of this limitation, and relocates
the FDT at the expected location. Guessing the expected location
probably only works reliably on 32-bit arm, and it
The 'firmware' property of a config node takes precedence over the
'kernel' property. 'standalone' is deprecated. However, give users a
couple of releases where 'standalone' still works, but warns loudly.
Signed-off-by: Alexandru Gagniuc
---
common/spl/spl.c | 19 ++-
1 file
The correct FDT to use is described by the "fdt" property of the
configuration node. When the fit_unamep argument to fit_image_load()
is "fdt", we get the "/images/fdt" node. This is incorrect, as it
ignores the "fdt" property of the config node, and in most cases,
the "/images/fdt" node doesn't
Although this series focuses on SPL_LOAD_FIT_FULL, some of the fixes will
also apply to bootm, as they are sharing significant amounts of code.
Originally SPL_LOAD_FIT_FULL could not start either a linux FIT or a
u-boot image. It didn't even take FIT images generated automatically
by mkimage, as
On Thu, Apr 1, 2021 at 7:17 PM Herbert Poetzl wrote:
>
>
> Hello Andy!
>
> Thanks for the quick feedback!
>
> On Thu, Apr 01, 2021 at 04:10:57PM +0300, Andy Shevchenko wrote:
> > On Thu, Apr 1, 2021 at 2:19 PM Herbert Poetzl wrote:
>
>
> >> I'm trying to get a serial console via USB working on
>
Hello Andy!
Thanks for the quick feedback!
On Thu, Apr 01, 2021 at 04:10:57PM +0300, Andy Shevchenko wrote:
> On Thu, Apr 1, 2021 at 2:19 PM Herbert Poetzl wrote:
>> I'm trying to get a serial console via USB working on
>> STM32MP1 but I'm encountering some problems there ...
>> The u-boot
On Thu, Apr 01, 2021 at 11:18:13AM +1300, Simon Glass wrote:
> This bash code is currently showing up in the build unless 'make -s' is
> used. We don't normally show these sorts of things as they are confusing.
> Also this code was not shown before the recent refactoring of how these
> messages
On Thu, Apr 01, 2021 at 09:08:56AM -0500, Alexandru Gagniuc wrote:
> Right before v2021.04-rc5 was dropped, several patches landed that
> updated the way DM warnings are printed. A side-effect of those
> changes is that, instead of printing warnings where appropriate, the
> Makefile prints the
Add functions to add size of addresses in the device tree using ofnode
references.
Signed-off-by: Chen Guanqiao
---
drivers/core/ofnode.c | 9 +
include/dm/ofnode.h | 10 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index
I'm trying to get a serial console via USB working on
STM32MP1 but I'm encountering some problems there ...
The u-boot README suggests to add the following config
entries to the board specific .h file:
CONFIG_USB_DEVICE
CONFIG_USB_TTY
CONFIG_USBD_HS (for high speed support)
When testing the USB Ethernet Gadget I encountered some
issues on STM32MP1 which prevented the bind to work as
expected.
Basically running ...
bind /soc/usb-otg@4900 usb_ether
... results in an additional entry in 'dm uclass' like:
uclass 104: usb
0 usb-otg@4900 @ ddf2f458, seq
Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().
Signed-off-by: Dylan Jhong
---
drivers/spi/atcspi200_spi.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/atcspi200_spi.c
On Thu, Apr 01, 2021 at 11:19:27AM +1300, Simon Glass wrote:
> +Heinrich Schuchardt
>
> On Thu, 1 Apr 2021 at 10:45, Tom Rini wrote:
> >
> > On Wed, Mar 31, 2021 at 10:05:28PM +0200, Marek Vasut wrote:
> > > On 3/31/21 9:40 PM, Tom Rini wrote:
> > > > On Wed, Mar 31, 2021 at 03:26:27PM -0400,
Right before v2021.04-rc5 was dropped, several patches landed that
updated the way DM warnings are printed. A side-effect of those
changes is that, instead of printing warnings where appropriate, the
Makefile prints the script that checks for the conditions:
if [ -n "y" ]; then if [ "y y" !=
On Thu, Apr 1, 2021 at 2:19 PM Herbert Poetzl wrote:
>
>
> I'm trying to get a serial console via USB working on
> STM32MP1 but I'm encountering some problems there ...
>
> The u-boot README suggests to add the following config
> entries to the board specific .h file:
>
> CONFIG_USB_DEVICE
>
On 4/1/21 1:12 PM, Ilias Apalodimas wrote:
> On Thu, Apr 01, 2021 at 12:45:33PM +0200, Michal Simek wrote:
>> When EFI_TCG2_PROTOCOL is selected there is unwritten dependency on sha384
>> and sha512.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>>
On Thu, Apr 01, 2021 at 12:45:33PM +0200, Michal Simek wrote:
> When EFI_TCG2_PROTOCOL is selected there is unwritten dependency on sha384
> and sha512.
>
> Signed-off-by: Michal Simek
> ---
>
>
On Thu, Apr 1, 2021 at 2:44 AM Heinrich Schuchardt
wrote:
> Am 1. April 2021 01:40:06 MESZ schrieb Igor Opaniuk <
> igor.opan...@gmail.com>:
> >Hi Heinrich
> >
> >On Thu, Apr 1, 2021 at 12:36 AM Heinrich Schuchardt
> > wrote:
> >>
> >> On 3/31/21 10:16 PM, Igor Opaniuk wrote:
> >> > From: Igor
For work with EFI it is good to have GUID partitions enabled and also
option to work with UEFI variables. That's why enable both.
Signed-off-by: Michal Simek
---
configs/xilinx_versal_virt_defconfig | 2 ++
configs/xilinx_zynqmp_virt_defconfig | 3 +++
2 files changed, 5 insertions(+)
diff
When EFI_TCG2_PROTOCOL is selected there is unwritten dependency on sha384
and sha512.
Signed-off-by: Michal Simek
---
/opt/Xilinx/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin/../x86_64-petalinux-linux/usr/bin/aarch64-xilinx-linux/aarch64-xilinx-linux-ld.bfd.real:
lib/built-in.o: in function
Since that invlolves external projects and not only U-Boot, add guidance
for supported platforms
Signed-off-by: Ilias Apalodimas
---
doc/develop/uefi/uefi.rst | 58 ++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/doc/develop/uefi/uefi.rst
On 01.04.21 09:56, Anup Patel wrote:
>
>
>> -Original Message-
>> From: Heinrich Schuchardt
>> Sent: 01 April 2021 12:40
>> To: Anup Patel
>> Cc: Carl Perry ; BeagleV Beta > b...@googlegroups.com>; Drew Fustini ; Wei Fu
>>
>> Subject: Re: [BeagleV Beta] Questions about bootup
>>
>> On
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