Hi,
Error output "*Command 'gpio' failed: Error -19*" is occurring with "*gpio
status -a*"
command on Beaglebone Black.
The "gpio" command is proper till "U-Boot 2021.04-rc2".
Error message is noticed from subsequent releases on-wards.
Problem is noticed on u-boot versions from *U-Boot
Hi Jaehoon,
Many thanks for your patience and guidance. Apologies for the delay, I
got held up by other things. Our newest patch is up, and we fixed all
checkpatch.pl warnings except we didn't put our names in the MAINTAINERS
file. Many thanks for your time and help again!
Best regards,
From: Tianrui Wei
Date: Thu, 6 May 2021 11:30:20 +0800
Subject: [PATCH V4 2/2] riscv: board: Support OpenPiton SoC
This patch add board support for OpenPiton.
Signed-off-by: Tianrui Wei
Signed-off-by: Jonathan Balkind
---
arch/riscv/Kconfig | 4 +
From: Tianrui Wei
Date: Thu, 6 May 2021 11:30:20 +0800
Subject: [PATCH V4 1/2] mmc: add OpenPiton mmc support
This patch adds mmc support for OpenPiton.
Specifically, some dts bindings were not used because
our mmc controller doens't have those configuration
options, it only exposes a dummy mmap
This patch set is to add OpenPiton board support. Patches are split into
several parts:
- [PATCH 1/2] add OpenPiton support to mmc driver
- [PATCH 2/2] add support for OpenPiton board
Description
- for mmc driver, it's settings are automatically configured at hardware level.
We only need to
Hello
Can send the Marvell 88E61XXX Switch driver
And file
thanks
Hey Folks,
We wanted to put out a middle-ground proposal to help guide the discussion on
the call tomorrow.
A proposal that we have been discussing offline involves reserving a single tag
ID for the purpose of construction UEFI PI HOB List structure, and that tag
would be used to identify a
Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.
Fixes 0cfa00cdb94 (“armv8: Add workaround for USB erratum A-050106”)
Signed-off-by: Ran Wang
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8
arch/arm/cpu/armv8/fsl-layerscape/soc.c
Hi Tom,
2021年5月3日(月) 20:51 Tom Rini :
>
> On Fri, Apr 30, 2021 at 11:13:45AM -0700, Simon Glass wrote:
> > Hi Masami,
> >
> > On Thu, 29 Apr 2021 at 20:03, Masami Hiramatsu
> > wrote:
> > >
> > > Hi Simon,
> > >
> > > 2021年4月30日(金) 1:10 Simon Glass :
> > > >
> > > > Hi Masami,
> > > >
> > > > On
Hi Simon,
On Thu, May 6, 2021 at 7:37 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
> >
> > This series updates binman to handle creation of u-boot.itb image for
> > RISC-V SiFive Unleashed board.
> >
> > QEMU RISC-V remains unchanged, as binman uses a dtb
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> Currently there are 2 binman test cases using the same 172 number.
> It seems that 172_fit_fdt.dts was originally named as 170_, but
> commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
> changed its name to 172_ for no
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> It needs a space around '-a'.
>
> Signed-off-by: Bin Meng
> ---
>
> tools/binman/binman.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> It should be FDT, not FTD.
>
> Signed-off-by: Bin Meng
> ---
>
> common/Kconfig.boot | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
Hi Kishon,
On Tue, 4 May 2021 at 21:25, Kishon Vijay Abraham I wrote:
>
> Hi Simon,
>
> On 04/05/21 10:28 pm, Simon Glass wrote:
> > Hi Kishon,
> >
> > On Tue, 4 May 2021 at 04:42, Kishon Vijay Abraham I wrote:
> >>
> >> The reset framework provides devm_reset_control_get_optional()
> >> which
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> At present SiFive Unleashed board uses the Makefile to create the FIT,
> using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
> warning. Update to use binman instead.
>
> Signed-off-by: Bin Meng
>
> ---
>
>
Hi Bin,
On Wed, 5 May 2021 at 07:16, Bin Meng wrote:
>
> When using binman to generate an FIT image, these intermediate files
> "*.fit.fit" and "*.fit.itb" are generated from mkimage, which should
> be cleaned, and git ignored.
>
> While we are here, clean the map file generated by "binman -m"
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> This updates the make rules to pass OpenSBI blob to binman.
>
> Signed-off-by: Bin Meng
> ---
>
> Makefile | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass
I suppose at some point we should separate this into a variable that
we
Hi Bin,
On Wed, 5 May 2021 at 07:16, Bin Meng wrote:
>
> Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.
>
> Signed-off-by: Bin Meng
> ---
>
> tools/binman/entries.rst | 13 +
> tools/binman/etype/opensbi.py | 23 +++
>
Hi Bin,
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> It should be 171_fit_fdt_missing_prop.dts.
>
> Signed-off-by: Bin Meng
> ---
>
> tools/binman/ftest.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Are you sure you are on upstream/master? Which commit?
CI should stop errors
Hi Bin,
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> This series updates binman to handle creation of u-boot.itb image for
> RISC-V SiFive Unleashed board.
>
> QEMU RISC-V remains unchanged, as binman uses a dtb to describe the
> image format, but for QEMU RISC-V there is no dtb as dtb is
On Wed, 5 May 2021 at 08:16, Bin Meng wrote:
>
> This is wrongly referring to Intel ME, which should be ATF.
>
> Signed-off-by: Bin Meng
> ---
>
> tools/binman/etype/atf_bl31.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
Hi Igor,
On Wed, 5 May 2021 at 06:58, Igor Opaniuk wrote:
>
> Hi Simon,
>
> On Thu, Apr 29, 2021 at 7:10 PM Simon Glass wrote:
> >
> > Hi Igor,
> >
> > On Fri, 16 Apr 2021 at 01:10, Igor Opaniuk
> > wrote:
> > >
> > > From: Igor Opaniuk
> > >
> > > Introduce RSA_SOFTWARE_EXP_TINY Kconfig
Hi Rasmus,
On Mon, 3 May 2021 at 23:59, Rasmus Villemoes
wrote:
>
> On 04/05/2021 01.10, Simon Glass wrote:
> > When passing a data buffer back from a function, it is not always clear
> > who owns the buffer, i.e. who is responsible for freeing the memory used.
> > An example of this is where
Hi Sean,
On Tue, 4 May 2021 at 17:23, Sean Anderson wrote:
>
> On 5/4/21 11:26 AM, Simon Glass wrote:
> > Hi Sean,
> >
> > On Sun, 2 May 2021 at 20:55, Sean Anderson wrote:
> >>
> >> This documents how to get more detailed results from valgrind made possible
> >> by the last two commits.
> >>
>
Hi Harb,
Thanks for the idea. I am still not completely sure what benefit UUID
provides to an open project. I'd like to propose something different, more
in the spirit of open collaboration. I also worry that the word 'standard'
seems to be a synonym for UUIDs, UEFI, etc., i.e.
On 5/5/21 3:54 PM, Igor Opaniuk wrote:
From: Igor Opaniuk
s/psci_features/psci_features_req/g for the case when both
ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these
compilation issues:
drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features'
69 | static int
From: Igor Opaniuk
s/psci_features/psci_features_req/g for the case when both
ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these
compilation issues:
drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features'
69 | static int psci_features(u32 psci_func_id)
|
From: Igor Opaniuk
s/psci_features/psci_features_req/g for the case when both
ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these
compilation issues:
drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features'
69 | static int psci_features(u32 psci_func_id)
|
On Wednesday 05 May 2021 09:15:10 Stefan Roese wrote:
> Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
> avoid confusion and mixup with DDR3/4 training. This makes it clear,
> that this command is platform specific and handles the COMPHY RX
> training.
>
> Also depend
On 4/12/21 5:05 PM, Sughosh Ganu wrote:
The current capsule authentication code checks if the environment
variable capsule_authentication_enabled is set, for authenticating the
capsule. This is in addition to the check for the config symbol
CONFIG_EFI_CAPSULE_AUTHENTICATE. Remove the check for
This annotates malloc and friends so that valgrind can track the heap. To
do this, we need to follow a few rules:
* Call VALGRIND_MALLOCLIKE_BLOCK whenever we malloc something
* Call VALGRIND_FREELIKE_BLOCK whenever we free something (generally after
we have done our bookkeeping)
* Call
This documents how to get more detailed results from valgrind made possible
by the last two commits.
Signed-off-by: Sean Anderson
Reviewed-by: Simon Glass
---
(no changes since v1)
doc/arch/sandbox.rst | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git
This series adds support for running valgrind against U-Boot's internal
malloc. This allows for much more useful reports to be generated.
Changes in v2:
- Fix one branch of rEALLOc missing a VALGRING_*_BLOCK call
- Add some additional suppressions for cALLOc and rEALLOc
- Simplify calloc clearing
On 4/20/21 9:21 AM, Tom Rini wrote:
On Thu, Apr 01, 2021 at 02:01:53AM +0300, Igor Opaniuk wrote:
From: Igor Opaniuk
Adds support for:
* PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API
that allows discovering whether a specific PSCI function is implemented
and its
On 5/5/21 1:43 PM, Simon Glass wrote:
Hi Alex,
On Wed, 5 May 2021 at 11:49, Alex G. wrote:
On 5/4/21 11:58 AM, Simon Glass wrote:
Hi Alex,
On Thu, 29 Apr 2021 at 10:10, Simon Glass wrote:
Hi Alex,
On Mon, 26 Apr 2021 at 07:21, Alex G. wrote:
On 4/23/21 11:56 PM, Simon Glass
Hi Andre,
On Wed, 5 May 2021 at 06:50, Andre Przywara wrote:
>
> fdt_getprop_u32_default_node() promises to take the "cell" number into
> account when returning the value of a property array.
>
> However it actually misses out on this, always returning the first cell
> only instead. This was so
On Wed, May 5, 2021 at 10:55 AM Neil Armstrong wrote:
>
> When the PHY interface is set as TXID & RXID, the delays should be taken from
> DT,
> but first they should not be hardcoded since the PHY driver will set them.
>
> Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue
Hi Alex,
On Wed, 5 May 2021 at 11:49, Alex G. wrote:
>
>
>
> On 5/4/21 11:58 AM, Simon Glass wrote:
> > Hi Alex,
> >
> > On Thu, 29 Apr 2021 at 10:10, Simon Glass wrote:
> >>
> >> Hi Alex,
> >>
> >> On Mon, 26 Apr 2021 at 07:21, Alex G. wrote:
> >>>
> >>>
> >>>
> >>> On 4/23/21 11:56 PM, Simon
Uhm,
Sorry for CC:ing a stale email address with the patches, t-kri...@ti.com
is no longer functional. Please drop that from any of the replies if you
don't fancy spam replies from server.
-Tero
On 05/05/2021 20:55, Tero Kristo wrote:
Hello,
Resurrecting this series; v2 [1] was sort of
MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.
Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which
From: Tero Kristo
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
board/ti/j721e/README | 9 ++---
1 file changed, 6
From: Dave Gerlach
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
From: Tero Kristo
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/Makefile | 2 +-
From: Dave Gerlach
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
From: Tero Kristo
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 7 ---
1 file changed, 4
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 4
From: Tero Kristo
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 80 +
From: Tero Kristo
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/power/domain/Kconfig
From: Tero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
From: Tero Kristo
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register
From: Tero Kristo
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
From: Tero Kristo
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-sci.c | 6 --
1 file changed, 4 insertions(+), 2
From: Tero Kristo
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero
From: Tero Kristo
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Acked-by: Lukasz Majewski
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/clk.c | 49
From: Tero Kristo
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post
From: Tero Kristo
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Reviewed-by: Peng Fan
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
From: Tero Kristo
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:
dev_get_uclass_priv: null device
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 2 ++
1 file changed, 2
From: Tero Kristo
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
---
From: Tero Kristo
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to
From: Tero Kristo
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this,
From: Tero Kristo
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result
Hello,
Resurrecting this series; v2 [1] was sort of put on hold due to some org
changes at TI. Sorry about the delay caused by this.
Anyways, v3 is mostly just a rebase of this series on top of
2021.07-rc1, and addition of some new data to support new boot modes for
j721e and j7200. This series
On 5/4/21 11:58 AM, Simon Glass wrote:
Hi Alex,
On Thu, 29 Apr 2021 at 10:10, Simon Glass wrote:
Hi Alex,
On Mon, 26 Apr 2021 at 07:21, Alex G. wrote:
On 4/23/21 11:56 PM, Simon Glass wrote:
Hi Tom, Alex,
On Fri, 23 Apr 2021 at 12:47, Tom Rini wrote:
On Fri, Apr 23, 2021 at
On Wed, 5 May 2021 09:15:10 +0200
Stefan Roese wrote:
> Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
> avoid confusion and mixup with DDR3/4 training. This makes it clear,
> that this command is platform specific and handles the COMPHY RX
> training.
>
> Also depend
On Wed, 5 May 2021 11:19:13 +0200
Pali Rohár wrote:
> > "bubt" is special and cannot be changed easily without breaking update
> > scripts using it AFAICT. As it's pretty old and used in the Marvell code
> > base for quite some time - including all the documentation about
> > updating.
>
> I
Adding new DH electronics mailing list.
Signed-off-by: Christoph Niedermaier
---
V2: Correct message tag
---
board/dhelectronics/dh_stm32mp1/MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
Adding new DH electronics mailing list and update list of maintainers.
Signed-off-by: Christoph Niedermaier
---
V2: Correct message tag and update list of maintainers
---
board/dhelectronics/dh_imx6/MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Hi Priyanka,
These changes have been tested and validated .
If no comments, please merge them . Ethernet changes for RevC boards has
dependency on this patch.
Regards,
Wasim
> -Original Message-
> From: Wasim Khan
> Sent: Saturday, April 17, 2021 11:34 PM
> To: Priyanka Jain ; Varun
On 5/5/21 2:51 PM, Andre Przywara wrote:
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.
Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng
---
arch/riscv/dts/binman.dtsi| 70 +++
This updates the make rules to pass OpenSBI blob to binman.
Signed-off-by: Bin Meng
---
Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/Makefile b/Makefile
index a5701f6f9a..c1ddcae22d 100644
--- a/Makefile
+++ b/Makefile
@@ -1287,6 +1287,7 @@ cmd_binman =
When using binman to generate an FIT image, these intermediate files
"*.fit.fit" and "*.fit.itb" are generated from mkimage, which should
be cleaned, and git ignored.
While we are here, clean the map file generated by "binman -m" as well.
Signed-off-by: Bin Meng
---
.gitignore | 4 +++-
Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.
Signed-off-by: Bin Meng
---
tools/binman/entries.rst | 13 +
tools/binman/etype/opensbi.py | 23 +++
tools/binman/ftest.py | 7 +++
tools/binman/test/201_opensbi.dts |
It should be 171_fit_fdt_missing_prop.dts.
Signed-off-by: Bin Meng
---
tools/binman/ftest.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 08f84cd32d..b0daccbc3b 100644
--- a/tools/binman/ftest.py
+++
Currently there are 2 binman test cases using the same 172 number.
It seems that 172_fit_fdt.dts was originally named as 170_, but
commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
changed its name to 172_ for no reason. Let's change it back.
Signed-off-by: Bin Meng
---
This is wrongly referring to Intel ME, which should be ATF.
Signed-off-by: Bin Meng
---
tools/binman/etype/atf_bl31.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/etype/atf_bl31.py b/tools/binman/etype/atf_bl31.py
index 163d714184..2041da416c 100644
---
It needs a space around '-a'.
Signed-off-by: Bin Meng
---
tools/binman/binman.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 1aa2459d50..b3df3a6428 100644
--- a/tools/binman/binman.rst
+++
It should be FDT, not FTD.
Signed-off-by: Bin Meng
---
common/Kconfig.boot | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 5a18d62d78..94d82c27dd 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -204,7 +204,7 @@
This series updates binman to handle creation of u-boot.itb image for
RISC-V SiFive Unleashed board.
QEMU RISC-V remains unchanged, as binman uses a dtb to describe the
image format, but for QEMU RISC-V there is no dtb as dtb is passed
to U-Boot via CONFIG_OF_PRIOR_STAGE.
Not sure how such use
Hello Oliver,
> -Original Message-
> From: U-Boot On Behalf Of Oliver Graute
> Sent: Wednesday, May 5, 2021 2:01 PM
> To: sba...@denx.de
> Cc: feste...@gmail.com; peng@nxp.com;
> oliver.gra...@kococonnector.com; u-boot@lists.denx.de; Simon Glass
> ; uboot-imx
> Subject: [PATCH v1]
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
As not all devices are
A simple prototyping board with one microSD port, one Ethernet port,
2 USB ports, I2C, SPI, GPIO, and UART interfaces.
Signed-off-by: Oleh Kravchenko
---
MAINTAINERS | 2 +
arch/arm/dts/Makefile| 3 +
Board designed for quick prototyping and has one microSD port,
2 Ethernet ports, 2 USB ports, I2C, SPI, CAN, RS-485, GPIO,
UART interfaces, and 2 RGB LEDs.
Signed-off-by: Oleh Kravchenko
---
MAINTAINERS | 10 +
arch/arm/dts/Makefile |
Hi Simon,
On Thu, Apr 29, 2021 at 7:10 PM Simon Glass wrote:
>
> Hi Igor,
>
> On Fri, 16 Apr 2021 at 01:10, Igor Opaniuk wrote:
> >
> > From: Igor Opaniuk
> >
> > Introduce RSA_SOFTWARE_EXP_TINY Kconfig option, which does not require
> > DM to be enabled. This can be handy on devices, where
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.
This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 5200 parent 117600 n 2 m 12 rate 4900
Also the
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.
Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow with every new chip.
Move the quirk
Xilinx TFA is normally placed to OCM at 0xfffea000 with a max size of 88kB.
By adding new and new features to TFA this split is reaching its limit
that there would be a need to change structures a little bit.
The idea is to resort SPL (potentially also Xilinx first stage bootloader
FSBL) that the
fdt_getprop_u32_default_node() promises to take the "cell" number into
account when returning the value of a property array.
However it actually misses out on this, always returning the first cell
only instead. This was so far not a problem, since every user always
asks for cell 0.
Observe the
Unit addresses are not allowed anymore in a FIT image since
commit 3f04db891a35 ("image: Check for unit addresses in FITs")
This caused this error on mkimage creation:
./tools/mkimage: verify_header failed for FIT Image support with exit code 1
Makefile:1393: recipe for target 'u-boot.itb'
Adding new DH electronics mailing list.
Signed-off-by: Christoph Niedermaier
---
board/dhelectronics/dh_stm32mp1/MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
index
Adding new DH electronics mailing list and myself as a maintainer.
Signed-off-by: Christoph Niedermaier
---
board/dhelectronics/dh_imx6/MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS
b/board/dhelectronics/dh_imx6/MAINTAINERS
index
Just an update.
I wrote a test stub, and I did not find any issue with the current u-boot
implementation regarding this command underrun issue.
However, for some unknown reasons, our AST2400/AST2500 u-boot builds had the
command buffer underrun issue that the cursor can be moved back into the
Hi, Stefan,
I think the MAINTAINERS file should be fixed for reflecting the configuration
file name change and moving to single defconfig from 2.
Regards
Kosta
From: Stefan Roese
Sent: Wednesday, May 5, 2021 11:21
To: u-boot@lists.denx.de
Cc: Kostya
On 5/5/21 10:41 AM, Neil Armstrong wrote:
If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.
With that, devices without USB3 supported can have USB working (Odroid-HC4).
Shouldn't you rather specify NOP PHY in the DT ?
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older
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