Re: [EXT] [PATCH] ARM: imx: romapi: Repair FlexSPI NOR boot offset

Hi Marek, On Wed, 2022-03-09 at 17:09 +0100, Marek Vasut wrote: > Caution: EXT Email > > The FlexSPI NOR boot offset does not require any special handling, > the image_offset is correct in either case (0x1000 for FlexSPI NOR > and 0x8000 for SD/eMMC) and the offset of u-boot.itb from the start >

Re: [PATCH] imx: imx8mm/imx8mn_beacon: Remove redundant code

On 2022/2/23 21:50, Adam Ford wrote: The Ethernet controller and PHY use the device tree info to configure themselves, so it's not necessary to manually do it in the board file. This permits the removal of a bunch of headers as well. Signed-off-by: Adam Ford Acked-by: Peng Fan diff

Re: [PATCH 0/2] enable DM_SERIAL on imx8mn-evk and imx8mn-ddr4-evk

On 2022/2/25 21:20, Heiko Thiery wrote: I was only able to test it on a 8MNANOD3L-EVK board. Please help testing this change on the other 2 eval boards (8MNANOLPD4-EVK, 8MNANOD4-EVK). SPL not use DM_SERIAL, only U-Boot proper use DM_SERIAL, right? Not related to your patch, I think we need

Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

On 3/21/22 03:48, Peng Fan (OSS) wrote: On 2022/2/26 11:37, Marek Vasut wrote: Add settings for operating PLL at 933 MHz. This setting is useful in case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s. Is the DDR operation value get from NXP DDR TOOL? No, the DDR RPA supports like

[PATCH v5] wdt: nuvoton: Add support for Nuvoton

Add watchdog controller driver for NPCM7xx/npcm8xx Signed-off-by: Jim Liu Reviewed-by: Stefan Roese Reviewed-by: Simon Glass Changes for v2: - coding style cleanup - change register type from struct Changes for v3: - remove common.h Changes for v4: - add a bit of detail about the

Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

On 2022/2/26 11:37, Marek Vasut wrote: Add settings for operating PLL at 933 MHz. This setting is useful in case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s. Is the DDR operation value get from NXP DDR TOOL? Thanks, Peng. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc:

Re: Pull request for efi-2022-04-rc5

On Sun, Mar 20, 2022 at 06:24:51PM +0100, Heinrich Schuchardt wrote: > Dear Tom, > > The following changes since commit 9776c4e9d00ac49d6388ffe9e084ff03b37ae479: > > Merge tag 'u-boot-rockchip-20220318' of > https://source.denx.de/u-boot/custodians/u-boot-rockchip (2022-03-18 > 16:37:39

Re: [PATCH] mmc: fsl_esdhc_imx: Add i.MX8MP compatible string

On 2022/3/11 4:27, Marek Vasut wrote: Add compatible string for i.MX8MP, which permits i.MX8MP to use HS400ES mode, just like all the other i.MX8M. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Haibo Chen Cc: Peng Fan Cc: Stefano Babic Reviewed-by: Peng Fan ---

Re: [PATCH v2 0/4] IMXRT: Maintnice updates

On 2022/3/18 2:33, Jesse Taube wrote: Updates to the imxrt family include: - Adding missing include in board - Moving pinctrl binding to dts - Reducing SYS_MALLOC_LEN - Using device tree for anatop base address Jesse Taube (4): clk: imxrt: Use dts for anatop base address

Re: [PATCH 2/2] pmic: pca9450: Add regulator driver

On 3/16/22 19:11, Marek Vasut wrote: > On 3/16/22 08:40, Jaehoon Chung wrote: >> Hi Marek, > > Hi, > >> On 3/11/22 05:28, Marek Vasut wrote: >>> Add PCA9450 regulator driver. This is complementary driver for the BUCKn >>> and LDOn regulators provided by the PCA9450 PMIC driver. Currently the >>>

Re: [PATCH] imx8ulp: Disable SPL exception vector

On 2022/3/18 15:50, Ye Li wrote: Disable SPL exception vector which causes issue to ROM patch execution when SPL calling ROM API. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git

Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq

On 2022/3/16 23:55, Heiko Thiery wrote: Hi Angus, [snip] But then something went wrong when probing uart3 ... the baudrate switched for the uart2 (console) and the serial output became broken. Later when the kernel starts the output becomes correct again. So the kernel seems to configure it

Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq

On 2022/3/15 23:35, Heiko Thiery wrote: Hi Angus and all, Am Di., 15. März 2022 um 14:09 Uhr schrieb Angus Ainslie >: This is a DM clock driver based off the imx8mm u-boot driver and the linux kernel driver. All of the PLLs and clocks are

Re: [PATCH 2/2] clk: Use generic CCF ops where possible

On 2022/3/21 4:34, Sean Anderson wrote: This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson For i.MX8M* Reviewed-by: Peng Fan ---

Re: [PATCH 1/2] clk: ccf: Add some helper functions for clock ops

On 2022/3/21 4:34, Sean Anderson wrote: Most CCF drivers follow a common pattern where their clock ops defer the actual operation to the backing CCF clock. Add some generic implementations of these functions to reduce duplication of code. Signed-off-by: Sean Anderson Reviewed-by: Peng Fan

Re: [PATCH v4 4/4] clk: imx8m: remove code duplication

Hi Angus, On 3/15/22 9:08 AM, Angus Ainslie wrote: All of the imx8m[nmpq] use the same clk_ops functions so move them to a common file. Signed-off-by: Angus Ainslie Reviewed-by: Marek Vasut --- drivers/clk/imx/Makefile | 8 +-- drivers/clk/imx/clk-imx8m.c | 108

Re: [PATCH v4 2/4] clk: imx8mq: Add a clock driver for the imx8mq

On 3/15/22 9:08 AM, Angus Ainslie wrote: This is a DM clock driver based off the imx8mm u-boot driver and the linux kernel driver. All of the PLLs and clocks are initialized so the subsystems below are functional and tested. 1) USB host and peripheral 2) ECSPI 3) UART 4) I2C all busses 5)

Re: [PATCH v1 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver

On 3/20/22 6:45 PM, Jesse Taube wrote: On 3/20/22 15:17, Sean Anderson wrote: On 3/17/22 2:32 PM, Jesse Taube wrote: Add clock driver support for i.MXRT1170. Signed-off-by: Jesse Taube ---    drivers/clk/imx/Kconfig |  16 +++    drivers/clk/imx/Makefile    |   1 +   

Re: [PATCH v1 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver

On 3/20/22 15:17, Sean Anderson wrote: On 3/17/22 2:32 PM, Jesse Taube wrote: Add clock driver support for i.MXRT1170. Signed-off-by: Jesse Taube --- drivers/clk/imx/Kconfig | 16 +++ drivers/clk/imx/Makefile| 1 + drivers/clk/imx/clk-imxrt1170.c | 215

A20-OLinuXino-LIME2 network regression [Was: [PATCH v2 1/5] sunxi: move non-essential code out of s_init()]

Andre Przywara [2022-02-01 01:41:12]: Hi Andre, > Since we have an SPL, which is called right after s_init(), move those > calls to our board_init_f() function. As we overwrite this only for > the SPL, this has the added benefit of not doing this setup *again* > shortly afterwards, when running

[PATCH v3] spi: zynq_spi: add chip select decoder support

Since zynq_spi device is compatible with Linux Cadence SPI driver, which supports chip select (CS) decoder, this patch adds the same logic for u-boot Zynq SPI driver. As a reference, I have used Xilinx Linux kernel 93dc4dbd16d (xilinx-v2020.2). The SPI decoder feature has been tested on ZynqMP

[PATCH v3] spi: zynq_spi: add chip select decoder support

Since zynq_spi device is compatible with Linux Cadence SPI driver, which supports chip select (CS) decoder, this patch adds the same logic for u-boot Zynq SPI driver. As a reference, I have used Xilinx Linux kernel 93dc4dbd16d (xilinx-v2020.2). The SPI decoder feature has been tested on ZynqMP

[PATCH 2/2] clk: Use generic CCF ops where possible

This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson --- drivers/clk/at91/pmc.c | 56 ++-- drivers/clk/imx/clk-imx6q.c | 73

[PATCH 1/2] clk: ccf: Add some helper functions for clock ops

Most CCF drivers follow a common pattern where their clock ops defer the actual operation to the backing CCF clock. Add some generic implementations of these functions to reduce duplication of code. Signed-off-by: Sean Anderson --- drivers/clk/clk.c| 65

[PATCH v2] spi: zynq_spi: add chip select decoder support

Since zynq_spi device is compatible with Linux Cadence SPI driver, which supports chip select (CS) decoder, this patch adds the same logic for u-boot Zynq SPI driver. As a reference, I have used Xilinx Linux kernel 93dc4dbd16d (xilinx-v2020.2). The SPI decoder feature has been tested on ZynqMP

Re: [PATCH v3 2/2] cmd/sbi: add missing SBI information

On 3/17/22 2:36 AM, Heinrich Schuchardt wrote: Let the sbi command display: * machine vendor ID * machine architecture ID * machine implementation ID With this patch the output for the HiFive Unmatched looks like => sbi SBI 0.3 OpenSBI 0.9 Machine: Vendor ID 489

Re: [PATCH v3 1/2] riscv: provide missing base extension functions

On 3/17/22 2:36 AM, Heinrich Schuchardt wrote: Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by: Heinrich Schuchardt --- arch/riscv/include/asm/sbi.h | 3 ++ arch/riscv/lib/sbi.c | 65

Re: [PATCH v1 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver

On 3/17/22 2:32 PM, Jesse Taube wrote: Add clock driver support for i.MXRT1170. Signed-off-by: Jesse Taube --- drivers/clk/imx/Kconfig | 16 +++ drivers/clk/imx/Makefile| 1 + drivers/clk/imx/clk-imxrt1170.c | 215 3 files changed, 232

Re: [PATCH v1 4/8] clk: imx: Add i.MXRT11xx pllv3 variant

On 3/17/22 2:32 PM, Jesse Taube wrote: The i.MXRT11 series has two new pll types but are variants of existing. This patch adds the ability to read one of the pll types' frequency as it can't be changed unlike the generic pll it also has the division factors swapped. Signed-off-by: Jesse Taube

Re: [PATCH 1/2] lib: time: Change behaviour of CONFIG_TIMER_EARLY

On 3/11/22 12:11 PM, Johannes Krottmayer wrote: If CONFIG_TIMER_EARLY is selected and the timer driver implements timer_early_get_count() and timer_early_get_rate(), check first if the virtual root driver is running, when it is initialized yet use the virtual timer driver instead. When the

[PATCH v2 1/1] cache: l2x0: Fix incorrect behavior if the latency is 1 cycle

According to the PL310 TRM, 0 in the latency fields(setup/read/write) indicates 1 cycle of latency for Tag and Data RAM latency control registers. If we want to set 1 cycle of latency, we need to clear the field actually. The TRM is as below:

Re: ipq40xx serial driver not working

On 3/19/22 09:22, Florence Riker wrote: Hello everyone, recently I'm trying to port the newest version of u boot to my ipq4019 development board, and I found that the current serial driver for Qualcomm ipq40xx socs at u-boot-2022.01/drivers/serial/serial_msm.c is not compatible to ipq40xx

Re: [PATCH v13 1/2] net: Add TCP protocol

On Wed, Mar 16, 2022 at 8:02 AM Ying-Chun Liu wrote: > > From: "Ying-Chun Liu (PaulLiu)" > > Currently file transfers are done using tftp or NFS both > over udp. This requires a request to be sent from client > (u-boot) to the boot server. > > The current standard is TCP with selective

Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

On 3/20/22 08:17, Heinrich Schuchardt wrote: On 3/18/22 04:54, Samuel Holland wrote: When the DM_I2C driver is loaded, the pin setup is done automatically from the device tree by the pinctrl driver. Clean up the code in the process: remove #ifdefs and recognize that the pin configuration

Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

On 3/18/22 04:54, Samuel Holland wrote: When the DM_I2C driver is loaded, the pin setup is done automatically from the device tree by the pinctrl driver. Clean up the code in the process: remove #ifdefs and recognize that the pin configuration is the same for all sun8i/sun50i SoCs, not just