Hello Sumit,
On Thu, 22 Sept 2022 at 12:15, Sumit Garg wrote:
>
> On Thu, 22 Sept 2022 at 14:22, Etienne Carriere
> wrote:
> >
> > Hello Patrick and all,
> >
> > On Mon, 19 Sept 2022 at 16:49, Patrick DELAUNAY
> > wrote:
> > >
> > >
> > > Hi Simon,
> > >
> > > On 9/12/22 20:31, Simon Glass
Hi Sean,
On Thu, Sep 22, 2022 at 10:35 PM Sean Anderson wrote:
>
>
>
> On 9/19/22 7:49 AM, Kautuk Consul wrote:
> > We add RISC-V semihosting based serial console for JTAG based early
> > debugging.
> >
> > The RISC-V semihosting specification is available at:
> >
Hi Sean,
On Thu, Sep 22, 2022 at 10:30 PM Sean Anderson wrote:
>
>
>
> On 9/19/22 7:49 AM, Kautuk Consul wrote:
> > We factor out the arch-independent parts of the ARM semihosting
> > implementation as a common library so that it can be shared
> > with RISC-V.
> >
> > Signed-off-by: Kautuk
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v4)
Changes in v4:
- Collect r-by from Stefan
drivers/pinctrl/mvebu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
(no changes since v3)
Changes in v3:
- Remove
These patches are based on Marvell's bootloader for the AlleyCat5/5X
which was based on u-boot 2018.03. I've split that code into consumable
chunks and dropped as much unnecessary stuff as I can. I've also tried
to sync the device trees as much as possible with the support that will
land in
In case the regulator-always-on is present in regulator DT node,
the regulator is always reconfigured to the voltage set in DT on
probe, even if regulator_set_value() has been called before. Drop
the property from AV96 U-Boot DT and enable the regulator manually
in code, as the board already
On Thu, Sep 22, 2022 at 5:10 PM Stefan Roese wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > The RD-AC5X-32G16HVG6HLG-A0 development board main components and
> > features include:
> > * Main 12V/54V power supply
> > * 270 Gbps throughput packet processor on the main board
> > * DDR4:
> >
On Thu, Sep 22, 2022 at 5:18 PM Stefan Roese wrote:
>
> On 22.09.22 05:31, Chris Packham wrote:
> > Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
> > block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
> > the fact that the ac5 does not have the mbus
On Thu, 2022-09-22 at 17:36 +0200, Stefano Babic wrote:
> On 22.09.22 17:03, Marcel Ziswiler wrote:
> > Hi Stefano
> >
> > On Mon, 2022-09-19 at 14:39 +0200, Stefano Babic wrote:
> > > On 18.09.22 22:41, sba...@denx.de wrote:
> > > > > From: Marcel Ziswiler
> > > > > - integrate bootcount using
From: Marcel Ziswiler
- enable bootcount command
- enable CRC32 and MD5
- enable time commands
- enable GPIO LED support
- enable further eMMC HS400 functionality
- enable fixed PHY and MDIO driver model
- enable USB host functionality
- enable thermal management unit driver
- enable hexdump
From: Marcel Ziswiler
- enable bootcount command
- integrate bootcount using SNVS_LP general purpose register LPGPR0
- enable link-time optimisation
- explicitly set a boot delay of one second
- enable CRC32 and MD5
- enable command for low-level access to data in a partition
- enable time
From: Marcel Ziswiler
Update the distro config env memory layout for the Verdin iMX8M Mini and
Verdin iMX8M Plus again:
- loadaddr=0x4820 allows for 128MB area for uncompressing (ie FIT
images, kernel_comp_addr_r, kernel_comp_size)
- fdt_addr_r = loadaddr + 128MB - allows for 128MB kernel
From: Marcel Ziswiler
Various additions and improvements for the Verdin iMX8M Mini and Verdin
iMX8M Plus:
- updated env memory layout
- verdin-imx8mm: prepare for optional job ring driver model (already
applied)
- verdin-imx8mm: improve and extend boot devices (already applied)
- various
Hello,
Il giorno gio 22 set 2022 alle ore 18:51 Neil Armstrong
ha scritto:
>
> Hi,
>
> Sorry for the delay...
No problem, don't worry
> Looks good !
>
> If someone can test it ? otherwise I'll take it for next release.
...does it count if I've tested it? I have a radxa zero board (S905Y2
chip),
Hi,
On 9/22/22 13:27, Simon Glass wrote:
Hi Etienne,
On Thu, 22 Sept 2022 at 10:52, Etienne Carriere
wrote:
Hello Patrick and all,
On Mon, 19 Sept 2022 at 16:49, Patrick DELAUNAY
wrote:
Hi Simon,
On 9/12/22 20:31, Simon Glass wrote:
Hi Ilias,
On Wed, 7 Sept 2022 at 15:32, Ilias
On 9/19/22 7:49 AM, Kautuk Consul wrote:
> We add RISC-V semihosting based serial console for JTAG based early
> debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> Signed-off-by: Anup
On 9/19/22 7:49 AM, Kautuk Consul wrote:
> We factor out the arch-independent parts of the ARM semihosting
> implementation as a common library so that it can be shared
> with RISC-V.
>
> Signed-off-by: Kautuk Consul
> ---
> arch/arm/Kconfig | 46 -
>
Hi,
Sorry for the delay...
On 18/09/2022 18:17, Edoardo Tomelleri wrote:
Implement setbrg in amlogic/meson serial device with driver model
similar to how the meson_uart.c driver does it in Linux. Also
configure (probe) the serial device with the new reg5 register.
Signed-off-by: Edoardo
Hello Michal,
On 9/22/2022 12:19 AM, Michal Simek wrote:
Hi,
On 9/22/22 08:39, Jae Hyun Yoo wrote:
Hello Michal,
On 9/21/2022 6:52 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Add product info area parsing support. Custom board fields can be
added dynamically using
Hi,
On 9/22/2022 12:29 AM, Michal Simek wrote:
Hi,
On 9/22/22 08:39, Jae Hyun Yoo wrote:
Hello Michal,
On 9/21/2022 6:40 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Refactor FRU handling support to remove Xilinx customization
dependency.
With this change, single or
On Thu, 22 Sept 2022 at 13:27, Simon Glass wrote:
>
> Hi Etienne,
>
> On Thu, 22 Sept 2022 at 10:52, Etienne Carriere
> wrote:
> >
> > Hello Patrick and all,
> >
> > On Mon, 19 Sept 2022 at 16:49, Patrick DELAUNAY
> > wrote:
> > >
> > >
> > > Hi Simon,
> > >
> > > On 9/12/22 20:31, Simon Glass
On 9/22/22 17:33, Quentin Schulz wrote:
Hi Marek,
Hi,
[...]
+ /*
+ * Since gpio-hog is a U_BOOT_DRIVER and not
+ * a U_BOOT_CLASS, the DM core does not bind
+ * it and therefore it's up to this driver to
+ * set
Hi all,
On 9/22/22 15:45, Quentin Schulz wrote:
From: Quentin Schulz
One needs to set u-boot,dm-pre-reloc in a device Device Tree node so
that it is kept in SPL/TPL variant of the device tree. However, a device
is automatically probed only if it's flagged with DM_FLAG_PRE_RELOC,
regardless of
From: Marek Vasut
The gpio_hog_probe_all() functionality can be perfectly well replaced by
DM_FLAG_PROBE_AFTER_BIND DM flag, which would trigger .probe() callback
of each GPIO hog driver instance after .bind() and thus configure the
hogged GPIO accordingly.
Signed-off-by: Marek Vasut
From: Quentin Schulz
Currently, dm_probe_devices checks that the flags of the device contains
DM_FLAG_PRE_RELOC. However DM_FLAG_PRE_RELOC is a driver - and not a
device - flag. This means that the check in pre_reloc_only mode would
always fail.
Instead, what was aimed to be checked is that
On 22.09.22 17:03, Marcel Ziswiler wrote:
Hi Stefano
On Mon, 2022-09-19 at 14:39 +0200, Stefano Babic wrote:
On 18.09.22 22:41, sba...@denx.de wrote:
From: Marcel Ziswiler
- integrate bootcount using SNVS_LP general purpose register LPGPR0
- enable link-time optimisation
- explicitly set a
Hi Marek,
On 9/22/22 16:29, Marek Vasut wrote:
On 9/22/22 16:13, Quentin Schulz wrote:
[...]
@@ -1503,9 +1480,26 @@ static int gpio_post_bind(struct udevice *dev)
);
if (ret)
return ret;
+
+ /*
+
On 9/22/22 15:14, Pali Rohár wrote:
On Thursday 22 September 2022 13:27:51 Simon Glass wrote:
Hi,
On Wed, 21 Sept 2022 at 15:56, Tom Rini wrote:
On Wed, Sep 21, 2022 at 03:54:13PM +0200, Pali Rohár wrote:
On Wednesday 21 September 2022 09:49:24 Tom Rini wrote:
On Mon, Sep 05, 2022 at
Hi Stefano
On Mon, 2022-09-19 at 14:39 +0200, Stefano Babic wrote:
> On 18.09.22 22:41, sba...@denx.de wrote:
> > > From: Marcel Ziswiler
> > > - integrate bootcount using SNVS_LP general purpose register LPGPR0
> > > - enable link-time optimisation
> > > - explicitly set a boot delay of one
On 22.09.22 13:25, Pali Rohár wrote:
Currently all GPIOs supported by CMD_EXT_CONTROL/CMD_GET_EXT_CONTROL_STATUS
commands (last 16 GPIOs) are available only when FEAT_PERIPH_MCU feature
bit is set. So do not register these GPIOs by U-Boot driver when this
feature bit is not set, so U-Boot 'gpio'
On 9/22/22 16:13, Quentin Schulz wrote:
[...]
@@ -1503,9 +1480,26 @@ static int gpio_post_bind(struct udevice *dev)
);
if (ret)
return ret;
+
+
On 9/22/22 15:59, Quentin Schulz wrote:
Hi Marek,
Hi,
[...]
diff --git a/doc/README.gpio b/doc/README.gpio
index 548ff37b8cc..d253f654fad 100644
--- a/doc/README.gpio
+++ b/doc/README.gpio
@@ -2,10 +2,8 @@
GPIO hog (CONFIG_GPIO_HOG)
-All the GPIO hog are initialized in
://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
tags/u-boot-imx-20220922
for you to fetch changes up to 1d8f4c85e3c04f596b0464542221b3507af0014e:
kontron-sl-mx8mm: Let CONFIG_SPL_FIT_IMAGE_TINY be selected
(2022-09-21 16:19:45 +0200
From: Marek Vasut
The gpio_hog_probe_all() functionality can be perfectly well replaced by
DM_FLAG_PROBE_AFTER_BIND DM flag, which would trigger .probe() callback
of each GPIO hog driver instance after .bind() and thus configure the
hogged GPIO accordingly.
For SPL/TPL, the DM_FLAG_PRE_RELOC
Hi Marek,
On 9/19/22 21:45, Marek Vasut wrote:
The gpio_hog_probe_all() functionality can be perfectly well replaced by
DM_FLAG_PROBE_AFTER_BIND DM flag, which would trigger .probe() callback
of each GPIO hog driver instance after .bind() and thus configure the
hogged GPIO accordingly.
On 9/22/22 13:27, Simon Glass wrote:
Hi,
[...]
It's similar, yes. I think the biggest hang-up for me is that while the
Kconfig help text isn't the best documentation for what is needed when
adding SPL to a board, it's better than code-only comments. I know Simon
asked for a comment on the
On 9/22/22 15:45, Quentin Schulz wrote:
From: Quentin Schulz
One needs to set u-boot,dm-pre-reloc in a device Device Tree node so
that it is kept in SPL/TPL variant of the device tree. However, a device
is automatically probed only if it's flagged with DM_FLAG_PRE_RELOC,
regardless of
From: Quentin Schulz
One needs to set u-boot,dm-pre-reloc in a device Device Tree node so
that it is kept in SPL/TPL variant of the device tree. However, a device
is automatically probed only if it's flagged with DM_FLAG_PRE_RELOC,
regardless of u-boot,dm-pre-reloc DT property presence. This
Hi Michael,
On Thu, Sep 22, 2022 at 3:39 PM Michael Trimarchi
wrote:
>
> Extract the information about ecc strength and ecc step size
> from mtd controller. This information is usefull to check if
> what we think as ecc is what we really configured.
>
> Signed-off-by: Michael Trimarchi
> ---
>
Extract the information about ecc strength and ecc step size
from mtd controller. This information is usefull to check if
what we think as ecc is what we really configured.
Signed-off-by: Michael Trimarchi
---
cmd/nand.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff
> The upstream Linux DSA drivers do not require phy-handle nodes in
> the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
> the mdio nodes to the u-boot.dtsi file so that future dts file
> syncrhonization between Linux and U-Boot don't break networking.
> Fixes: 24a7a3c1c042
> From: Fabio Estevam
> When running the script to sign SPL/U-Boot on a kontron-sl-mx8mm board,
> the fit_block_size was calculated as 0x1000 instead of 0x1020.
> Add an extra parenthesis pair to fix it.
> Signed-off-by: Fabio Estevam
> Reviewed-by: Marek Vasut
Applied to u-boot-imx, master,
> The upstream Linux DSA drivers do not require phy-handle nodes in
> the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
> the mdio nodes to the u-boot.dtsi file so that future dts file
> syncrhonization between Linux and U-Boot don't break networking.
> Fixes: e0caa84ca685
> When CONFIG_IMX_HAB is selected the 'hab_status' command reports several
> error events, indicating that the BootROM failed to authenticate the SPL.
> After inspecting the content of the memory location that corresponds to
> the DTB load address, the content did not match with the DTB binary,
>
> Pull this LPGPR unlock into common code, since it is used in multiple
> systems already.
> Signed-off-by: Marek Vasut
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH,
On Thu, Sep 22, 2022 at 03:26:43PM +0200, Heinrich Schuchardt wrote:
> An upcoming patch set creates a global function flush(). To make debugging
> easier we should not use the same name for a static function.
>
> Rename static functions in the LoadImage() unit test adding an efi_st_
> prefix.
>
An upcoming patch set creates a global function flush(). To make debugging
easier we should not use the same name for a static function.
Rename static functions in the LoadImage() unit test adding an efi_st_
prefix.
Signed-off-by: Heinrich Schuchardt
---
On Fri, Aug 26, 2022 at 03:27:14PM +0530, Sughosh Ganu wrote:
> The Dependable Boot specification[1] describes the structure of the
> firmware accept and revert capsules. These are empty capsules which
> are used for signalling the acceptance or rejection of the updated
> firmware by the OS. Add
On Thursday 22 September 2022 13:27:51 Simon Glass wrote:
> Hi,
>
> On Wed, 21 Sept 2022 at 15:56, Tom Rini wrote:
> >
> > On Wed, Sep 21, 2022 at 03:54:13PM +0200, Pali Rohár wrote:
> > > On Wednesday 21 September 2022 09:49:24 Tom Rini wrote:
> > > > On Mon, Sep 05, 2022 at 11:31:15AM +0200,
On 9/22/22 13:27, Simon Glass wrote:
Hi,
On Wed, 21 Sept 2022 at 15:56, Tom Rini wrote:
On Wed, Sep 21, 2022 at 03:54:13PM +0200, Pali Rohár wrote:
On Wednesday 21 September 2022 09:49:24 Tom Rini wrote:
On Mon, Sep 05, 2022 at 11:31:15AM +0200, Pali Rohár wrote:
On certain places it is
In certain TI SoCs, on the CPSW and ICSS peripherals, there is
a possibility that the MDIO interface returns corrupt data on
MDIO reads or writes incorrect data on MDIO writes. There is also
a possibility for the MDIO interface to become unavailable until
the next peripheral reset.
The workaround
For the TI SoCs affected by errata i2329, enable MDIO manual
mode by default
Signed-off-by: Ravi Gunasekaran
---
drivers/net/ti/am65-cpsw-nuss.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c
This patch series adds the MDIO workaround for the errata i2329.
On certain TI SoC's CPSW and ICSS peripherals, there is a possibility
that the MDIO interface returns corrupt data on MDIO reads or writes
incorrect data on MDIO writes. There is also a possibility for the
MDIO interface to become
When processing USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE, and
USB_REQ_GET_STATUS packets in dwc2_ep0_setup an out of bounds access
can occur. This is caused by the wIndex field of the usb control packet
being used as an index into an array whose size is DWC2_MAX_ENDPOINTS (4).
Signed-off-by:
From: Quentin Schulz
The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip
PX30 in a micro Qseven-compatible form-factor.
PX30-µQ7 features:
* CPU: quad-core Cortex-A35
* DRAM: 2GB dual-channel
* eMMC: onboard eMMC
* SD/MMC
* TI DP83825I
From: Quentin Schulz
This event code represents the firmware source to use at boot.
Value 0 means using "standard" firmware source, value 1 means using
"alternative" firmware source.
For example, some hardware has the ability to force the BOOTROM to load
the bootloader from a secondary firmware
From: Quentin Schulz
Sync include/dt-bindings/input/linux-event-codes.h with
include/uapi/linux/input-event-codes.h from Linux kernel v6.0-rc6.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
include/dt-bindings/input/linux-event-codes.h | 173 +-
1 file changed, 170
From: Quentin Schulz
Sync the px30 dtsi from linux-next tree, commit 483fed3b5dc8c ("Add
linux-next specific files for 20220921").
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/dts/px30.dtsi | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
From: Quentin Schulz
It is possible to boot U-Boot proper from a different storage medium
than the one used by the BOOTROM to load the SPL. This information is
stored in the u-boot,spl-boot-device Device Tree property and is
accessible from U-Boot proper so that it has knowledge at runtime where
From: Quentin Schulz
BOOTROM sets a bit in a CPU register so that the software can know from
where the first stage bootloader was booted. One use case for this is to
specify the default loading medium for U-Boot proper to match the one
used by the BOOTROM to load the SPL (same-as-spl in
From: Quentin Schulz
The IRAM on PX30 (or Int_MEM in datasheet) starts at 0xff0e and not
0xff02 as rightfully stated in the FIXME comment.
Let's fix it so that BROM_BOOTSOURCE_ID_ADDR points to the correct
address for PX30.
Fixes: 46281a76bee3 ("rockchip: add core px30 headers")
Cc:
From: Quentin Schulz
The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230
connector) system-on-module from Theobroma Systems[1], featuring the
Rockchip PX30.
It provides the following feature set:
* up to 4GB DDR4
* up to 128GB on-module eMMC (with 8-bit 1.8V interface)
* SD
On 9/22/22 13:35, Simon Glass wrote:
Hi,
On Thu, 22 Sept 2022 at 12:27, Michal Simek wrote:
On 9/21/22 15:22, Alexander Dahl wrote:
For future DM based FPGA drivers and for now to have a meaningful
logging class for old FPGA drivers.
Suggested-by: Michal Simek
Signed-off-by:
This patch series add support for programming LD eFuse on Armada 385.
I tested it on Turris Omnia board.
Armada 385 LD1 eFuse is for General Purpose Data and is already mapped
to U-Boot fuse word 65.
Pali Rohár (3):
arm: mvebu: Add support for programming LD0 and LD1 eFuse
arm: mvebu: Add
VHV_Enable GPIO is required to enable during eFuse programming on Armada
SoCs not from 3700 family. Add support for enabling and disabling VHV pin
via GPIO during eFuse programming, when specified.
All details are in Marvell AN-389: ARMADA VHV Power document
(Doc. No. MV-S302545-00 Rev. C, August
This patch implements LD eFuse programming support. Armada 385 contains two
LD eFuse lines, each is 256 bit long with one additional lock bit. LD 0
line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. U-Boot
32-bit fuse words 0-8 are mapped to LD eFuse line bits 0-255. U-Boot fuse
VHV gpio is connected to MCU and only on updated board design. Without it
eFUSE programming does not work. Omnia MCU driver exports this GPIO to
U-Boot under name mcu_56 and only when it is supported by MCU. So U-Boot
fuse command refuse eFUSE programming on older board design when VHV gpio
is not
Hi,
On Thu, 22 Sept 2022 at 12:27, Michal Simek wrote:
>
>
>
> On 9/21/22 15:22, Alexander Dahl wrote:
> > For future DM based FPGA drivers and for now to have a meaningful
> > logging class for old FPGA drivers.
> >
> > Suggested-by: Michal Simek
> > Signed-off-by: Alexander Dahl
> > ---
> >
Hi,
On Wed, 21 Sept 2022 at 15:56, Tom Rini wrote:
>
> On Wed, Sep 21, 2022 at 03:54:13PM +0200, Pali Rohár wrote:
> > On Wednesday 21 September 2022 09:49:24 Tom Rini wrote:
> > > On Mon, Sep 05, 2022 at 11:31:15AM +0200, Pali Rohár wrote:
> > >
> > > > On certain places it is required to flush
Hi Tom,
On Wed, 21 Sept 2022 at 15:49, Tom Rini wrote:
>
> On Wed, Sep 21, 2022 at 02:56:29AM +0200, Marek Vasut wrote:
> > On 9/20/22 21:04, Tom Rini wrote:
> > > On Tue, Sep 20, 2022 at 05:56:50PM +0200, Marek Vasut wrote:
> > > > On 9/20/22 17:43, Simon Glass wrote:
> > > > > On Mon, 19 Sept
Hi Etienne,
On Thu, 22 Sept 2022 at 10:52, Etienne Carriere
wrote:
>
> Hello Patrick and all,
>
> On Mon, 19 Sept 2022 at 16:49, Patrick DELAUNAY
> wrote:
> >
> >
> > Hi Simon,
> >
> > On 9/12/22 20:31, Simon Glass wrote:
> > > Hi Ilias,
> > >
> > > On Wed, 7 Sept 2022 at 15:32, Ilias
Hello Michal,
Am Thu, Sep 22, 2022 at 12:30:08PM +0200 schrieb Michal Simek:
>
>
> On 9/21/22 15:22, Alexander Dahl wrote:
> > Instead of using DEBUG or LOG_DEBUG the driver still had its own
> > definition for debug output.
> >
> > Signed-off-by: Alexander Dahl
> > ---
> >
Currently all GPIOs supported by CMD_EXT_CONTROL/CMD_GET_EXT_CONTROL_STATUS
commands (last 16 GPIOs) are available only when FEAT_PERIPH_MCU feature
bit is set. So do not register these GPIOs by U-Boot driver when this
feature bit is not set, so U-Boot 'gpio' command would see only GPIOs which
On 21/09/2022 18:09, Andre Przywara wrote:
Commit c0fce929564f("vexpress64: fvp: enable OF_CONTROL") added code to
consider a potential DTB address being passed in the x0 register, or
revert to the built-in DTB otherwise.
The former case was used when using the boot-wrapper, to which we sell
On 9/21/22 15:22, Alexander Dahl wrote:
Instead of using DEBUG or LOG_DEBUG the driver still had its own
definition for debug output.
Signed-off-by: Alexander Dahl
---
drivers/fpga/virtex2.c | 37 +++--
1 file changed, 15 insertions(+), 22 deletions(-)
On 9/21/22 15:22, Alexander Dahl wrote:
For future DM based FPGA drivers and for now to have a meaningful
logging class for old FPGA drivers.
Suggested-by: Michal Simek
Signed-off-by: Alexander Dahl
---
include/dm/uclass-id.h | 1 +
1 file changed, 1 insertion(+)
diff --git
On Thu, 22 Sept 2022 at 14:22, Etienne Carriere
wrote:
>
> Hello Patrick and all,
>
> On Mon, 19 Sept 2022 at 16:49, Patrick DELAUNAY
> wrote:
> >
> >
> > Hi Simon,
> >
> > On 9/12/22 20:31, Simon Glass wrote:
> > > Hi Ilias,
> > >
> > > On Wed, 7 Sept 2022 at 15:32, Ilias Apalodimas
> > >
hi Ilias,
On Thu, 22 Sept 2022 at 14:29, Ilias Apalodimas
wrote:
>
> Hi Sughosh
>
> On Thu, Sep 15, 2022 at 01:44:42PM +0530, Sughosh Ganu wrote:
> > Add weak functions for getting the update index value and dfu
> > alternate number needed for FWU Multi Bank update
> > functionality.
> >
> > The
This enables armv8 crypto extension usage for SHA1/SHA256.
Which speed up sha1/sha256 operations, about 10x faster with
a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms).
Signed-off-by: Loic Poulain
---
v2: Select ARMV8_CRYPTO in the imx8m common Kconfig
On Mon, Sep 19, 2022 at 05:19:08PM +0530, Kautuk Consul wrote:
> To enable semihosting we also need to enable the following
> configs in defconfigs:
> CONFIG_SEMIHOSTING
> CONFIG_SPL_SEMIHOSTING
> CONFIG_SEMIHOSTING_SERIAL
> CONFIG_SERIAL_PROBE_ALL
> CONFIG_SPL_FS_EXT4
> CONFIG_SPL_FS_FAT
>
>
On Mon, Sep 19, 2022 at 05:19:07PM +0530, Kautuk Consul wrote:
> We add RISC-V semihosting based serial console for JTAG based early
> debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
>
On Mon, Sep 19, 2022 at 05:19:06PM +0530, Kautuk Consul wrote:
> We factor out the arch-independent parts of the ARM semihosting
> implementation as a common library so that it can be shared
> with RISC-V.
>
> Signed-off-by: Kautuk Consul
> ---
> arch/arm/Kconfig | 46 -
>
Hi Sughosh
On Thu, Sep 15, 2022 at 01:44:42PM +0530, Sughosh Ganu wrote:
> Add weak functions for getting the update index value and dfu
> alternate number needed for FWU Multi Bank update
> functionality.
>
> The current implementation for getting the update index value is for
> platforms with
Hello Patrick and all,
On Mon, 19 Sept 2022 at 16:49, Patrick DELAUNAY
wrote:
>
>
> Hi Simon,
>
> On 9/12/22 20:31, Simon Glass wrote:
> > Hi Ilias,
> >
> > On Wed, 7 Sept 2022 at 15:32, Ilias Apalodimas
> > wrote:
> >> Hi Simon,
> >>
> >> On Thu, 8 Sept 2022 at 00:11, Simon Glass wrote:
> >>>
Hi Sughosh
On Thu, Sep 15, 2022 at 01:44:39PM +0530, Sughosh Ganu wrote:
> In the FWU Multi Bank Update feature, the information about the
> updatable images is stored as part of the metadata, on a separate
> partition. Add a driver for reading from and writing to the metadata
> when the
On 9/22/2022 10:44 AM, Marek Vasut wrote:
On 9/21/22 07:45, Peng Fan wrote:
Hi,
[...]
@@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct
event *event)
}
EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
+static void imx8m_setup_snvs(void)
+{
+ /* Enable SNVS clock
Hi,
On 9/22/22 08:39, Jae Hyun Yoo wrote:
Hello Michal,
On 9/21/2022 6:40 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Refactor FRU handling support to remove Xilinx customization dependency.
With this change, single or multiple custom board fields and
multi-records can be
Hi,
On 9/22/22 08:39, Jae Hyun Yoo wrote:
Hello Michal,
On 9/21/2022 6:52 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Add product info area parsing support. Custom board fields can be
added dynamically using linked list so that each board support can
utilize them in their
The meat of my problem. rk3399 has the ability to redirect uart2 to
sdcard pins. This setup half works; I can push input into the uart, but
not see output.
Signed-off-by: Marty E. Plummer
---
arch/arm/dts/rk3399-gru.dtsi | 7 ++-
arch/arm/dts/rk3399.dtsi
Not even used as far as I can see, but still.
Signed-off-by: Marty E. Plummer
---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
Code snagged from rk3188's u-boot implementation and the linux kernel's
implementation of rockchip.usb_uart=1
Tested on rk3288-veyron-speedy
patman/checkpatch.pl doesn't like my indentation here and I can't quite
figure out what it actually wants.
Complaint is:
Trivial change, builds a bootable u-boot.rom properly.
Signed-off-by: Marty E. Plummer
---
arch/arm/mach-rockchip/rk3288/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig
b/arch/arm/mach-rockchip/rk3288/Kconfig
index e8c57843a3..99bf2397e6
I don't intend for the last change to be included in mainline, I just
need some form of serial output to see why archlinuxarm, alpine linux,
and Fedora workstation all fail to boot on this hardware (rk3399-gru-kevin).
Or at least, I think its failing. At the point of booting the kernel the
Hello Michal,
On 9/21/2022 6:54 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Add a usage document for the 'fru' u-boot command.
Add kerneldocs for .
Signed-off-by: Jae Hyun Yoo
---
Changes from v3:
* None.
Changes from v2:
* Added kerneldocs to 'include/fru.h'.
Hello Michal,
On 9/21/2022 6:52 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Add product info area parsing support. Custom board fields can be
added dynamically using linked list so that each board support can
utilize them in their own custom way.
Signed-off-by: Jae Hyun
Hello Michal,
On 9/21/2022 6:40 AM, Michal Simek wrote:
On 8/25/22 18:42, Jae Hyun Yoo wrote:
Refactor FRU handling support to remove Xilinx customization dependency.
With this change, single or multiple custom board fields and
multi-records can be added dynamically using linked list so that
1 - 100 of 101 matches
Mail list logo
