Re: [PATCH v1 3/4] net: rtl8169: Add one more device ID

On Wed, Jun 21, 2023 at 12:05 PM Minda Chen wrote: > > Add the NIC device ID and adjust the PCI bar regions. > > Signed-off-by: Minda Chen > --- > drivers/net/rtl8169.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c >

Re: [PATCH v1 2/4] net: rtl8169: Fix DMA min aligned compile warning in riscv

On Wed, Jun 21, 2023 at 12:05 PM Minda Chen wrote: > > Fix rtl8169 descriptor less the DMA min aligned compile warning > for RISC-V SoC platform. > > Signed-off-by: Minda Chen > --- > drivers/net/rtl8169.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git

Re: [PATCH v1 1/4] net: rtl8169: Fix compile warning in rtl8169 network adapter

On Wed, Jun 21, 2023 at 12:05 PM Minda Chen wrote: > > Fix make pointer from integer without a cast compile warning. > > Signed-off-by: Minda Chen > --- > drivers/net/rtl8169.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/rtl8169.c

Re: [PATCH 2/2] net: phy: Release PHY from GPIO reset if applicable

On Tue, Jun 20, 2023 at 1:46 AM Marek Vasut wrote: > > In case the PHY DT node describes GPIO reset and no other method > of detecting the PHY succeeded, release the PHY from reset using > its reset GPIO before reading out the PHY IDs as a last resort. > This way there is slightly better chance

Re: [PATCH 1/2] net: phy: Factor out PHY GPIO reset code

On Tue, Jun 20, 2023 at 1:46 AM Marek Vasut wrote: > > Pull the PHY GPIO reset code into separate function, since > this is and will be reused multiple times. Set up default > reset assert and deassert timing to generous 20ms and 1ms > for maximum compatibility in case those DT properties are >

Re: [PATCH v1] net: sun8i-emac: Add support for fixed-link phy

On Thu, Jun 15, 2023 at 12:51 AM Maxim Kiselev wrote: > > From: Maksim Kiselev > > Based on dt-specs fixed-link doesn't require phy-handle to be used. > Fix driver to only read phy related setting when phy-handle is found. > > Signed-off-by: Maksim Kiselev > --- > drivers/net/sun8i_emac.c | 7

Re: [PATCH v1 2/2] net: designware: Add bitbang feature for designware driver

On Tue, Jun 13, 2023 at 9:29 AM Jim Liu wrote: > > Hi Ramon > > Thanks for your review. > The udelay timing is defined on our spec . > Does this need to use config to control it or use dts method to set the > timing? dts > > > Best regards, > Jim >

[PATCH] power: add axp313a support (tag added to subject)

Hello, Simon told me that you are maintainer of pmic section. I am trying to add AXP313A support to sunxi/AXP code. Maybe previous mail is CCed but I think you have not read my diff. I attach it again. board/sunxi/board.c looks complex to maintain. We have to think how handle it after AXP313A

Re: [PATCH] arm: mach-k3: am62a7: change some prints to debug prints

On Mon, Jul 17, 2023 at 06:01:33PM -0500, Bryan Brattlof wrote: > There is little need to print the devstat information or when we exit a > function during a typical boot. Remove them to reduce the noise during > typical operation > > Signed-off-by: Bryan Brattlof Applied to u-boot/master,

Re: [PATCH] ram: k3-ddrss: do not touch ctrl regs during training

On Mon, Jul 17, 2023 at 05:15:26PM -0500, Bryan Brattlof wrote: > During LPDDR initialization we will loop through a series of frequency > changes in order to train at the various operating frequencies. During > this training, accessing the DRAM_CLASS bitfield could happen during a > frequency

Re: [PATCH] arm: omap2: Fix warning in force_emif_self_refresh

On Mon, Jul 17, 2023 at 03:26:43PM -0400, Tom Rini wrote: > The function declaration for force_emif_self_refresh takes no parameters > but does not specify this, only the prototype in the headers do. As > clang will warn about this, correct it. > > Signed-off-by: Tom Rini Applied to

Re: [PATCH] configs: k2x_evm: Always include FIT loading support

On Fri, Jul 14, 2023 at 02:00:58PM -0500, Andrew Davis wrote: > Non-HS boards can use FIT images so include the env var commands > for these unconditionally. > > Signed-off-by: Andrew Davis > Reviewed-by: Nishanth Menon Applied to u-boot/master, thanks! -- Tom signature.asc Description:

Re: [PATCH] arm: dts: Fix build of am62a7 dtbs

On Thu, Jul 13, 2023 at 02:40:51PM -0500, Nishanth Menon wrote: > am62a7 should be built with CONFIG_SOC_K3_AM62A7 not CONFIG_SOC_K3_AM625 > > Fixes: 6bdfa69155d8 ("arm: dts: introduce am62a7 u-boot dtbs") > Cc: Bryan Brattlof > Cc: Vignesh Raghavendra > Cc: Francesco Dolcini > Cc: Sjoerd

Re: [PATCH] arm: mach-k3: *: dev-data: Update to use ARRAY_SIZE

On Thu, Jul 13, 2023 at 02:36:34PM -0500, Nishanth Menon wrote: > Instead of hard-coding the count of entries manually, use ARRAY_SIZE > to keep the count updates appropriately. > > Cc: Bryan Brattlof > Suggested-by: Ravi Gunasekaran > Signed-off-by: Nishanth Menon > Reviewed-by: Bryan

Re: [PATCH] arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewall

On Sun, Jul 02, 2023 at 02:46:54PM +0530, Vignesh Raghavendra wrote: > On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that > is present in above 64bit region. Open this up in bootloader to allow > Linux to access OSPI flashes in mmap mode. > > Without this kernel will crash

Re: [PATCH V2 2/2] common: splash_source: Fix type casting errors

On Wed, Jun 21, 2023 at 04:29:53PM +0530, Nikhil M Jain wrote: > During compilation splash_source puts out below warning for type > conversion in splash_load_fit for bmp_load_addr and fit_header. > Change their type to uintptr_t to fix the warnings. > > common/splash_source.c: In function

Re: [PATCH V2 1/2] board: ti: am62x: evm: Include necessary header files

On Wed, Jun 21, 2023 at 04:29:52PM +0530, Nikhil M Jain wrote: > At the time of compilation evm.c gives below warning for implicit > declaration of enable_caches, to mitigate this include cpu_func.h. > > board/ti/am62x/evm.c: In function ‘spl_board_init’: > board/ti/am62x/evm.c:90:9: warning:

Re: [PATCH 1/1] part: check CONFIG_IS_ENABLED(ENV_SUPPORT)

On Fri, Jul 21, 2023 at 05:37:37PM +0200, Heinrich Schuchardt wrote: > In SPL environment variables may not be enabled. > > Suggested-by: Tom Rini > Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature

Re: [PATCH V6 00/10] Update SPL splashscreen framework for AM62x

On Tue, 18 Jul 2023 14:27:26 +0530, Nikhil M Jain wrote: > This patch series aims at updating SPL splashscreen framework for AM62x. > > This patch series depends on > https://lore.kernel.org/u-boot/20230504225829.2537050-1-...@chromium.org/ > > This series: > - Fixes compilation issues in case

Re: [PATCH v2 0/3] arm: mach-k3: am62: Add core number, gpu and pru autodetection FDT fixups

On Fri, 14 Jul 2023 17:23:07 +0200, Francesco Dolcini wrote: > From: Francesco Dolcini > > AM62x SoC is available in multiple variant: > - CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores) > - GPU AM625x with GPU, AM623x without GPU > - PRU (Programmable RT unit) can

Re: data abort when run 'dhcp'

Hi qianfan, qianfangui...@163.com wrote on Fri, 21 Jul 2023 08:31:17 +0800: > 在 2023/7/21 0:39, Miquel Raynal 写道: > > Hello, > > > > qianfangui...@163.com wrote on Fri, 25 Mar 2022 18:04:46 +0800: > > > >> It's very strange. And I can't detect it's a bug of usb or dlmalloc. > >> > >> 1.

[PATCH 2/2] net: tftp: Prevent too early device removal leading to data aborts

All network related commands are executed through a "net loop", which handles the initialization, setup and removal of all the required resources to perform the operation. Aside from the generic network boilerplate, the net loop calls specific helpers provided by the different command

[PATCH 1/2] net: eth-uclass: Prevent data aborts with the Ethernet USB gadget

From: Qianfan Zhao The Ethernet USB gadget driver creates a virtual Ethernet interface on the fly in the ->start() callback. This means, there is no other place than the ->stop() callback to unregister the interface and free all the associated structures. Deleting the interface frees the 'priv'

[PATCH 0/2] Fix network commands w/ USB Eth gadget

Hello, I recently came across serious issues using U-Boot on Beagle Bone Black. The USB Ethernet gadget is behaving in a way that is not compliant with the uclass expectations, leading to use-after-free accesses often producing data aborts. All network commands are affected. There are two

Re: [PATCH v1] HSD #18028953892: usb: xhci-dwc3: Fix USB3.1 controller register access in reset state

On 7/21/23 05:26, Lim, Jit Loon wrote: Hi, Linux: (__dwc3_of_simple_teardown) https://elixir.bootlin.com/linux/latest/source/drivers/usb/dwc3/dwc3-o f-simple.c#L98 U-Boot: (xhci_dwc3_remove) https://elixir.bootlin.com/u-boot/latest/source/drivers/usb/host/xhci- dwc3.c#L227 So we believed

[PATCH v8 04/23] j721e: schema: yaml: Add general schema and J721E board config files

Schema file in YAML must be provided in board/ti/common for validating input config files and packaging system firmware. The schema includes entries for rm-cfg, board-cfg, pm-cfg and sec-cfg. Board config files must be provided in board/ti/ in YAML. These can then be consumed for generation of

Re: data abort when run 'dhcp'

在 2023/7/21 0:39, Miquel Raynal 写道: Hello, qianfangui...@163.com wrote on Fri, 25 Mar 2022 18:04:46 +0800: It's very strange. And I can't detect it's a bug of usb or dlmalloc. 1. Starting u-boot and dhcp via am335x's ethernet(cpsw driver), it's ok. 2. Starting u-boot and dhcp via

[PATCH] sunxi: restore modified memory

On A64 with 2G of RAM words at following addresses were modified with 'aa55aa55' value: - 5000 - 6000 - 8400 - 8800 - 9000 - A000 - A200 That made harder to pick memory range for persistent storage in RAM. Signed-off-by: Andrey Skvortsov ---

Re: [PATCH 3/6] net: ti: am65-cpsw-nuss: Add logic to support MDIO reset

On Sat, Jul 08, 2023 at 04:15:20PM +0530, Siddharth Vadapalli wrote: > From: Suman Anna > > Enhance the AM65 CPSW NUSS driver to perform a MDIO reset using a GPIO > line. Logic is also added to perform a pre and post delay around reset > using the optional 'reset-delay-us' and

[PATCH] docs: boards: ti: add openocd spl debugging docs

Add documentation on how to use OpenOCD to debug U-Boot for TI K3 Generation boards. Signed-off-by: Jason Kacines --- doc/board/ti/am62x_openocd.rst | 248 + doc/board/ti/k3.rst| 20 ++- 2 files changed, 265 insertions(+), 3 deletions(-) create mode

[PATCH v8 23/23] CI: Make use of buildman requirements.txt

From: Tom Rini Now that buildman has a requirements.txt file we need to make use of it. Signed-off-by: Tom Rini Reviewed-by: Simon Glass [n-fran...@ti.com: Adding missing command from .azure-pipelines.yml] Signed-off-by: Neha Malcom Francis --- .azure-pipelines.yml | 4 .gitlab-ci.yml

[PATCH v8 21/23] binman: Overwrite symlink if it already exists

From: Andrew Davis Without this re-building will fail with an error when trying to create the symlink for the second time with an already exists error. Signed-off-by: Andrew Davis [n-fran...@ti.com: Added support for test output dir and testcase] Signed-off-by: Neha Malcom Francis ---

[PATCH v8 22/23] buildman: Create a requirements.txt file

From: Tom Rini At this point, buildman requires a few different modules and so we need a requirements.txt to track what modules are needed. Cc: Simon Glass Cc: Neha Malcom Francis Signed-off-by: Tom Rini Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis ---

[PATCH v8 20/23] doc: board: ti: Update documentation for binman flow

Earlier documentation specified builds for generating bootloader images using an external TI repository k3-image-gen and core-secdev-k3. Modify this to using the binman flow so that user understands how to build the final boot images. Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis

[PATCH v8 18/23] arm: k3-am65x-iot2050: Use binman for tispl.bin for iot2050

Move to using binman to generate tispl.bin which is used to generate the final flash.bin bootloader for iot2050 boards. Cc: Jan Kiszka Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 75 +++- 1 file changed, 74

[PATCH v8 19/23] k3: tools: config.mk: Update makefile and remove scripts

Since binman is used to package bootloader images for all K3 devices, we do not have to rely on the earlier methods to package them. Scripts that were used to generate x509 certificate for tiboot3.bin and generate tispl.bin, u-boot.img have been removed. Reviewed-by: Simon Glass Signed-off-by:

[PATCH v8 17/23] am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img

Support added for HS-SE, HS-FS and GP boot binaries for AM62ax. HS-SE: * tiboot3-am62ax-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62ax-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62ax-gp-evm.bin * tispl.bin_unsigned *

[PATCH v8 16/23] am62a: yaml: Add board configs for AM62ax

Added YAML configs for AM62ax Signed-off-by: Neha Malcom Francis --- board/ti/am62ax/board-cfg.yaml | 36 + board/ti/am62ax/pm-cfg.yaml | 12 + board/ti/am62ax/rm-cfg.yaml | 1151 ++ board/ti/am62ax/sec-cfg.yaml | 379 ++

[PATCH v8 15/23] am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img

Support added for HS-SE, HS-FS and GP boot binaries for AM62. HS-SE: * tiboot3-am62x-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62x-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62x-gp-evm.bin * tispl.bin_unsigned *

[PATCH v8 14/23] am62: yaml: Add board configs for AM62

Added YAML configs for AM62 Signed-off-by: Neha Malcom Francis --- board/ti/am62x/board-cfg.yaml | 36 ++ board/ti/am62x/pm-cfg.yaml| 12 + board/ti/am62x/rm-cfg.yaml| 1088 + board/ti/am62x/sec-cfg.yaml | 379 4 files changed, 1515

[PATCH v8 13/23] j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img

Support has been added for both HS-SE, HS-FS and GP images. HS-SE: * tiboot3-j721s2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j721s2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j721s2-gp-evm.bin * tispl.bin_unsigned *

[PATCH v8 12/23] j721s2: yaml: Add board configs for J721S2

Added YAML configs for J721S2 Signed-off-by: Neha Malcom Francis --- board/ti/j721s2/board-cfg.yaml | 36 + board/ti/j721s2/pm-cfg.yaml| 12 + board/ti/j721s2/rm-cfg.yaml| 2901 board/ti/j721s2/sec-cfg.yaml | 379 + 4 files changed, 3328

[PATCH v8 11/23] am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img

Support added for HS and GP boot binaries for AM64x. HS-SE: * tiboot3-am64x_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am64x_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am64x-gp-evm.bin * tispl.bin_unsigned *

[PATCH v8 10/23] am64x: yaml: Add board configs for AM64x

Added YAML configs for AM64xx Signed-off-by: Neha Malcom Francis --- board/ti/am64x/board-cfg.yaml | 36 + board/ti/am64x/pm-cfg.yaml| 12 + board/ti/am64x/rm-cfg.yaml| 1400 + board/ti/am64x/sec-cfg.yaml | 380 + 4 files changed, 1828

[PATCH v8 09/23] am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img

Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images. HS-SE: * tiboot3-am65x_sr2-hs-evm.bin * sysfw-am65x_sr2-hs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin * sysfw.itb -->

[PATCH v8 08/23] am65x: yaml: Add AM65x board config files

Added YAML configs for AM65x Signed-off-by: Neha Malcom Francis --- board/ti/am65x/board-cfg.yaml | 36 + board/ti/am65x/pm-cfg.yaml| 12 + board/ti/am65x/rm-cfg.yaml| 2068 + board/ti/am65x/sec-cfg.yaml | 379 ++ 4 files changed, 2495

[PATCH v8 07/23] j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img

Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin -->

[PATCH v8 06/23] j7200: yaml: Add J7200 board config files

Added YAML configs for J7200 Signed-off-by: Neha Malcom Francis --- board/ti/j721e/board-cfg_j7200.yaml | 36 + board/ti/j721e/pm-cfg_j7200.yaml| 12 + board/ti/j721e/rm-cfg_j7200.yaml| 2065 +++ board/ti/j721e/sec-cfg_j7200.yaml | 380 + 4 files

[PATCH v8 05/23] j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img

By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate

[PATCH v8 03/23] arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.bin

Board config binary artifacts must be generated to be used by binman to package sysfw.itb and tiboot3.bin for all K3 devices. For devices that follow combined flow, these board configuration binaries must again be packaged into a combined board configuration blobs to be used by binman to package

[PATCH v8 02/23] binman: ti-secure: Add support for TI signing

The ti-secure entry contains certificate for binaries that will be loaded or booted by system firmware whereas the ti-secure-rom entry contains certificate for binaries that will be booted by ROM. Support for both these types of certificates is necessary for booting of K3 devices. Reviewed-by:

[PATCH v8 01/23] binman: ti-board-config: Add support for TI board config binaries

The ti-board-config entry loads and validates a given YAML config file against a given schema, and generates the board config binary. K3 devices require these binaries to be packed into the final system firmware images. Reviewed-by: Simon Glass Signed-off-by: Neha Malcom Francis ---

[PATCH v8 00/23] Migration to using binman for bootloader

This series aims to eliminate the use of additional custom repositories such as k3-image-gen (K3 Image Generation) repo and core-secdev-k3 (K3 Security Development Tools) that was plumbed into the U-Boot build flow to generate boot images for TI K3 platform devices. And instead, we move towards

Re: Pull request: u-boot-sunxi/master for 2023.10

On Fri, Jul 21, 2023 at 02:48:57PM +0100, Andre Przywara wrote: > Hi Tom, > > please pull the first part of the sunxi pull request for this cycle: > > For once this adds USB support for two SoCs: the H616 and the F1C100s > series. The rest is support for LPDDR3 DRAM chips on H616 boards. > >

Re: [GIT PULL] xilinx patches for v2023.10-rc1 v2

On Fri, Jul 21, 2023 at 03:30:54PM +0200, Michal Simek wrote: > Hi Tom, > > please pull these patches to your tree. CI is not reporting any issue. > The biggest part is adding support for versal-net mini configuration for non > volatile memories programming and also DT changes based on our

Re: [PATCH 1/1] spl: boot always fail on CONFIG_SHOW_ERRORS=y

Hi Heinrich, On Fri, 21 Jul 2023 at 09:32, Heinrich Schuchardt wrote: > > Commit 7d84fbb57312 ("spl: Provide more information on boot failure") left > debug code to let boot_from_devices() always fail if CONFIG_SHOW_ERRORS=y. > > Remove the debug code. > > Fixes: 7d84fbb57312 ("spl: Provide more

Re: [PATCH 1/1] spl: boot always fail on CONFIG_SHOW_ERRORS=y

On Fri, Jul 21, 2023 at 05:32:20PM +0200, Heinrich Schuchardt wrote: > Commit 7d84fbb57312 ("spl: Provide more information on boot failure") left > debug code to let boot_from_devices() always fail if CONFIG_SHOW_ERRORS=y. > > Remove the debug code. > > Fixes: 7d84fbb57312 ("spl: Provide more

Re: [PATCH 0/6] binman: Template fixes and improvements

Hi Simon On 21/07/23 21:37, Simon Glass wrote: With the basic template feature in place, some problems have come to light. Firstly, keeping the template around while processing entries seems unnecessary and perhaps confusing, so this is removed. Secondly this series aims to support phandles

Re: [PATCH v2 1/1] riscv: define a cache line size for the generic CPU

On Sat, Jul 22, 2023 at 12:01 AM Heinrich Schuchardt wrote: > > The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. > > Define the cache line size for QEMU on RISC-V to be 64 bytes. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > Select SYS_CACHE_SHIFT_6 for

[PATCH] board_f: Cosmetic style fix

Some coding convention fixes for print_resetinfo(). Signed-off-by: Bin Meng --- common/board_f.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index e5969ec9a2..db37522f61 100644 --- a/common/board_f.c +++ b/common/board_f.c @@

Re: [u-boot-test-hooks PATCH 1/1] qemu_arm64_na: enable semihosting

On Sat, 13 May 2023 00:59:30 +0200, Heinrich Schuchardt wrote: > For testing semihosting we need to pass parameter -semihosting. > > Applied, thanks! [1/1] qemu_arm64_na: enable semihosting commit: 610263e34c6ceba0de5cd69a7c4e5a6205b886f9 Best regards, -- Tom

[PATCH 5/5] x86: Return mtrr_add_request() to its old purpose

From: Simon Glass This function used to be for adding a list of requests to be actioned on relocation. Revert it back to this purpose, to avoid problems with boards which need control of their MTRRs (i.e. those which don't use FSP). The mtrr_set_next_var() function is available when the next

[PATCH 4/5] video: vesa: Use mtrr_set_next_var() for graphics memory

At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in

[PATCH 3/5] video: ivybridge: Use mtrr_set_next_var() for graphics memory

At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in

[PATCH 2/5] video: broadwell: Use mtrr_set_next_var() for graphics memory

At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in

[PATCH 1/5] x86: fsp: Use mtrr_set_next_var() for graphics memory

At present this uses mtrr_add_request() & mtrr_commit() combination to program the MTRR for graphics memory. This usage has two major issues as below: - mtrr_commit() will re-initialize all MTRR registers from index 0, using the settings previously added by mtrr_add_request() and saved in

[PATCH 6/6] WIP: binman: Support templates containing phandles

This provides support for phandles to be copied over from templates. This is not quite safe, since if the template is instantiated twice (i.e. in two different nodes), then duplicate phandles will be found. This patch is provided for some initial experimentation. Signed-off-by: Simon Glass ---

[PATCH 5/6] binman: Remove templates after use

It is not necessary to keep templates around after they have been processed. They can cause confusion and potentially duplicate phandles. Remove them. Use the same means of detecting a template node in _ReadImageDesc so that the two places are consistent. Signed-off-by: Simon Glass ---

[PATCH 4/6] fdt: Allow copying phandles into templates

Allow phandles to be copied over from a template. This can potentially cause duplicate phandles, but we can deal with that later. Signed-off-by: Simon Glass --- tools/dtoc/fdt.py | 2 +- tools/dtoc/test_fdt.py | 15 --- 2 files changed, 9 insertions(+), 8 deletions(-) diff

[PATCH 3/6] dtoc: Add some debugging when copying nodes

Show the operations being performed, when debugging is enabled. Convert a mistaken 'print' in test_copy_subnodes_from_phandles() while we are here. Signed-off-by: Simon Glass --- tools/dtoc/fdt.py | 5 + tools/dtoc/test_fdt.py | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-)

[PATCH 2/6] dtoc: Make properties dirty when purging them

Without the 'dirty' flag properties are not written back to the devicetree when synced. This means that new properties copied over to a node are not always written out. Fix this and add a test. Signed-off-by: Simon Glass --- tools/dtoc/fdt.py | 1 +

[PATCH 1/6] binman: Produce a template-file after processing

This file aids debugging when binman fails to get far enough to write out the final devicetree file. Write it immediate after template processing. Signed-off-by: Simon Glass --- tools/binman/binman.rst | 4 tools/binman/control.py | 14 -- tools/binman/ftest.py | 9

[PATCH 0/6] binman: Template fixes and improvements

With the basic template feature in place, some problems have come to light. Firstly, keeping the template around while processing entries seems unnecessary and perhaps confusing, so this is removed. Secondly this series aims to support phandles in a more intuitive way, rather than just ignoring

Re: [PATCH v5 15/20] binman: Support simple templates

Hi Neha, On Wed, 19 Jul 2023 at 13:11, Simon Glass wrote: > > Hi Neha, > > On Wed, 19 Jul 2023 at 05:08, Neha Malcom Francis wrote: > > > > Hi Simon > > > > On 18/07/23 18:54, Simon Glass wrote: > > > Collections can used to collect the contents of other entries into a > > > single entry, but

[PATCH v2 1/1] riscv: define a cache line size for the generic CPU

The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. Define the cache line size for QEMU on RISC-V to be 64 bytes. Signed-off-by: Heinrich Schuchardt --- v2: Select SYS_CACHE_SHIFT_6 for GENERIC_RISCV and not for TARGET_QEMU_VIRT (as suggested by Bin) ---

[PATCH 1/1] part: check CONFIG_IS_ENABLED(ENV_SUPPORT)

In SPL environment variables may not be enabled. Suggested-by: Tom Rini Signed-off-by: Heinrich Schuchardt --- disk/part.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/disk/part.c b/disk/part.c index 3a9315c0ab..6a30335a48 100644 --- a/disk/part.c +++

[PATCH 1/1] spl: boot always fail on CONFIG_SHOW_ERRORS=y

Commit 7d84fbb57312 ("spl: Provide more information on boot failure") left debug code to let boot_from_devices() always fail if CONFIG_SHOW_ERRORS=y. Remove the debug code. Fixes: 7d84fbb57312 ("spl: Provide more information on boot failure") Signed-off-by: Heinrich Schuchardt ---

Re: [PATCH v3 00/11] Sign Xilinx ZynqMP SPL/FSBL boot images using binman

On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote: From: Lukas Funke This series adds two etypes to create a verified boot chain for Xilinx ZynqMP devices. The first etype 'xilinx-fsbl-auth' is used to create a bootable, signed image for ZynqMP boards using the Xilinx Bootgen tool.

Re: [PATCH v3 09/11] binman: btool: Add Xilinx Bootgen btool

On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote: From: Lukas Funke Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The btool creates a signed version of the SPL. Additionally to signing the key

Re: [PATCH 1/1] riscv: define a cache line size for QEMU

On Fri, Jul 21, 2023 at 8:59 PM Heinrich Schuchardt wrote: > > The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. > > Define the cache line size for QEMU on RISC-V to be 64 bytes. > > Signed-off-by: Heinrich Schuchardt > --- > arch/Kconfig | 1 + >

Re: Please pull u-boot-dm

On Thu, Jul 20, 2023 at 02:13:38PM -0600, Simon Glass wrote: > Hi Tom, > > I am bringing in the binman changes now. There are going to be some > minor tweaks to templating as well as various patches from others, but > most are based on these patches. > > >

Pull request: u-boot-sunxi/master for 2023.10

Hi Tom, please pull the first part of the sunxi pull request for this cycle: For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I

[PATCH 08/20] sunxi: introduce NCAT2 generation model

Allwinner seems to typically stick to a common MMIO memory map for several SoCs, but from time to time does some breaking changes, which also introduce new generations of some peripherals. The last time this happened with the H6, which apart from re-organising the base addresses also changed the

[PATCH 20/20] sunxi: add MangoPi MQ-R board support

This copies the T113s specific DTs from the Linux kernel tree (v6.4-rc1), and adds a defconfig to get the board booted. Signed-off-by: Andre Przywara --- arch/arm/dts/Makefile | 2 + .../arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 +

[PATCH 18/20] riscv: dts: allwinner: Add the D1/D1s SoC devicetree

From: Samuel Holland D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based on a single die, or at a pair of dies derived from the same design. D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and T113 contain a pair of Cortex-A7's. D1 and R528 are the full

[PATCH 19/20] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi

The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with two Arm Cortex-A7 cores. Since the D1 core .dtsi already describes all common peripherals, we just need a DT describing the ARM specific peripherals: the

[PATCH 17/20] sunxi: refactor serial base addresses to avoid asm/arch/cpu.h

At the moment we have each SoC's memory map defined in its own cpu.h, which is included in include/configs/sunxi_common.h. This will be a problem with the introduction of Allwinner RISC-V support. Remove the inclusion of that header file from the common config header, instead move the required

[PATCH 15/20] sunxi: add R528/T113-s3/D1(s) DRAM initialisation code

The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and

[PATCH 16/20] sunxi: add Allwinner R528/T113 SoC support

This adds the remaining code bits to teach U-Boot about Allwinner's newest SoC generation. This was introduced with the RISC-V based Allwinner D1 SoC, which actually shares a die with the ARM cores versions called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM). This adds the new

[PATCH 13/20] sunxi: clock: h6: prepare for PRCM less SoCs

The Allwinner D1/R528/T113 SoCs have a very minimal separate "management" power plane, with almost no device attached to it (so no r_i2c or r_uart). This means we don't need to flip any clock gates in the PRCM block, which in fact those SoCs do not have. Prepare the code for those SoCs by making

[PATCH 14/20] Kconfig: sunxi: prepare for using drivers/ram/sunxi

At the moment all Allwinner DRAM initialisation routines are stored in arch/arm/mach-sunxi, even though those "drivers" are just a giant collection of writel's, without any architectural dependency. The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V cores) share the same die, so

[PATCH 10/20] clk: sunxi: Add support for the D1 CCU

From: Samuel Holland Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Acked-by: Sean Anderson Signed-off-by: Andre Przywara --- drivers/clk/sunxi/Kconfig

[PATCH 12/20] sunxi: clock: support D1/R528 PLL6 clock

The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is new P0 divider at bits [18:16], and the M divider is 1. Add code to support this version of "PLL6". Signed-off-by: Andre Przywara --- .../include/asm/arch-sunxi/clock_sun50i_h6.h | 2 ++

[PATCH 11/20] sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup

The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL. Just enable that when we program that PLL. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 1 + arch/arm/mach-sunxi/clock_sun50i_h6.c | 12 +++- 2 files changed, 8

[PATCH 09/20] pinctrl: sunxi: add Allwinner D1 pinctrl description

Apart from using the new pinctrl MMIO register layout, the Allwinner D1 and related SoCs still need to usual set of mux values hardcoded in U-Boot's pinctrl driver. Add the values we need so far to this list, so that DM based drivers will just work without further ado. Signed-off-by: Andre

[PATCH 07/20] pinctrl: sunxi: add new D1 pinctrl support

For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we cannot use our hardcoded, fixed offsets anymore. Ideally this would all be handled by devicetree and DM drivers, but for the DT-less SPL we still need the legacy

[PATCH 05/20] pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER

U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code to more easily include platform specific GPIO headers. This should not be needed in a DM world anymore, since the generic GPIO framework handles that nicely. For Allwinner boards we still need to deal with non-DM GPIO in the

[PATCH 06/20] pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h

On the Allwinner platform we were describing a quite comprehensive memory map in a per-SoC header unser arch/arm. In the old days that was used by every driver, but nowadays it should only be needed by SPL drivers (not using the DT). Many addresses in there were never used, and some are not needed

[PATCH 04/20] pinctrl: sunxi: remove struct sunxi_gpio

So far every Allwinner SoC used the same basic pincontroller/GPIO register frame, and just differed by the number of implemented banks and pins, plus some special functionality from time to time. However the D1 and successors use a slightly different pinctrl register layout. Use that opportunity

[PATCH 02/20] sunxi: remove CONFIG_MACPWR

The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables the power for the Ethernet "MAC" (mostly PHY, really). In the DT this is described with the phy-supply property in the MAC DT node, pointing to a (GPIO controlled) regulator. Since we need Ethernet only in U-Boot proper, and

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