From: Dinesh Maniyam
This patch is to add SPI clock support for stratix10. Get clock rate
function always returning 0 because the DW-SPI driver get the rate
from clock node in dts but Stratix10 does not support device tree
clock node.To overcome this spi will get the clock_rate directly
from spi
Hi Andrew,
On 10:23-20231206, Andrew Davis wrote:
> On 12/6/23 3:51 AM, Manorit Chawdhry wrote:
> > The following commits adds the configuration of firewalls required to
> > protect ATF and OP-TEE memory region from non-secure reads and
> > writes using master and slave fir
Hi Apurva,
On 06/12/23 18:07, Apurva Nandan wrote:
Add J784S4 initialization files for initial SPL boot.
Signed-off-by: Hari Nagalla
[ add firewall configurations and change the R5 MCU scratchpad ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
On 12/7/2023 2:47 AM, Reid Tonking wrote:
Previously, dynamic frequency scaling supported rates only through fixed
divison.
This virtual clock mux configuration enables more varied rates on A72
clock ID 202 by setting up the required register.
Signed-off-by: Apurva Nandan
Signed-off-by:
On 12/7/2023 2:47 AM, Reid Tonking wrote:
From: Bryan Brattlof
In order for the Cortex-A72s to operate at different frequencies other
than the default 2GHz, add in a new 'virtual' mux (a mux that does not
physically exist in the clock tree) that can be selected.
CC: Vishal Mahaveer
From: Bryan Brattlof
In order for the Cortex-A72s to operate at different frequencies other
than the default 2GHz, add in a new 'virtual' mux (a mux that does not
physically exist in the clock tree) that can be selected.
CC: Vishal Mahaveer
Signed-off-by: Bryan Brattlof
Signed-off-by: Apurva
Previously, dynamic frequency scaling supported rates only through fixed
divison.
This virtual clock mux configuration enables more varied rates on A72
clock ID 202 by setting up the required register.
Signed-off-by: Apurva Nandan
Signed-off-by: Reid Tonking
---
Since the 09.01.00.002 release of ti-linux-firmware [0] upstream uboot
has led to the kernel hanging during boot [1] for the TI J7200 S0C. The
issue was found to be a few patches that had be added to ti-u-boot, but not
yet upstreamed. This series adds the missing two patches to allow upstream
On Tue, Dec 5, 2023 at 11:05 PM Sumit Garg wrote:
>
> On Tue, 5 Dec 2023 at 15:39, Krzysztof Kozlowski
> wrote:
> >
> > On 05/12/2023 10:45, Sumit Garg wrote:
> > > + U-boot custodians list
> > >
> > > On Tue, 5 Dec 2023 at 12:58, Krzysztof Kozlowski
> > > wrote:
> > >>
> > >> On 05/12/2023
Hi Simon,
> The other thing missing here is SPL. The bloblist is designed such
> that it can be set up in any phase of U-Boot, then is passed to
> following phases. So using IS_ENABLED(BLOBLIST) doesn't do what we
> need. As I noted, it breaks sandbox_spl. What happens if a board wants
> to use
Hi Simon,
I am wondering if I shall put in your review tag as you are one of the
authors of many patches...
What is the best approach under this situation in the U-Boot community?
Thanks and regards,
Raymond
On Sat, 2 Dec 2023 at 13:33, Simon Glass wrote:
> On Mon, 27 Nov 2023 at 12:52,
On 09:47-20231205, Kumar, Udit wrote:
>
> On 12/2/2023 3:03 AM, Reid Tonking wrote:
> > From: Bryan Brattlof
> >
> > In order for the Cortex-A72s to operate at different frequencies other
> > than the default 2GHz, add in a new 'virtual' mux (a mux that does not
> > physically exist in the
mctl_mem_matches and mctl_mem_matches_base identical functions. To
avoid code duplication move them to dram_helpers and make
mctl_mem_matches use generic mctl_mem_matches_base.
Signed-off-by: Andrey Skvortsov
---
arch/arm/include/asm/arch-sunxi/dram.h | 1 +
arch/arm/mach-sunxi/dram_helpers.c
On A64 with 2G of RAM words at following addresses were modified with
'aa55aa55' value:
- 5000
- 6000
- 8400
- 8800
- 9000
- A000
- A200
That made harder to pick memory range for persistent storage in RAM.
Signed-off-by: Andrey Skvortsov
---
Changes in v2:
- rename temporary variables
- fix types for temporary variables
Andrey Skvortsov (2):
sunxi: restore modified memory
sunxi: reorganize mctl_mem_matches_* functions
arch/arm/include/asm/arch-sunxi/dram.h | 1 +
arch/arm/mach-sunxi/dram_helpers.c | 32
Hi Andre,
On 23-11-01 09:50, Andre Przywara wrote:
> On Fri, 21 Jul 2023 17:57:21 +0300
> Andrey Skvortsov wrote:
>
> Hi Andrey,
>
> sorry for the late reply!
>
> > On A64 with 2G of RAM words at following addresses were modified with
> > 'aa55aa55' value:
> > - 5000
> > - 6000
> >
Hi Ilias,
I will add both TPM_EVLOG and TPM_CRB_BASE.
Regards,
Raymond
On Wed, 6 Dec 2023 at 05:54, Ilias Apalodimas
wrote:
> On Mon, 4 Dec 2023 at 20:55, Raymond Mao wrote:
> >
> > Hi Ilias,
> >
> > What is the difference between the new added XFERLIST_EVLOG and the
> existing
Hello Andre,
On 2023-12-06 17:24, Andre Przywara wrote:
On Mon, 4 Dec 2023 00:59:52 + Andre Przywara
wrote:
Add support for the zBIT ZB25VQ128 (128M-bit) SPI NOR flash memory
chip,
as used on the Xunlong Orange Pi Zero 3 board.
does anyone have any objections against this patch? I
On 12/6/23 3:51 AM, Manorit Chawdhry wrote:
This commit adds a general flow to explain the usage of firewalls and
the chain of trust in K3 devices.
Signed-off-by: Manorit Chawdhry
---
doc/board/ti/k3.rst | 45 +
1 file changed, 45 insertions(+)
On Mon, 4 Dec 2023 00:59:52 +
Andre Przywara wrote:
Hi,
> Add support for the zBIT ZB25VQ128 (128M-bit) SPI NOR flash memory chip,
> as used on the Xunlong Orange Pi Zero 3 board.
does anyone have any objections against this patch? I wanted to take this
via the sunxi tree, as this blocks
On 12/6/23 3:51 AM, Manorit Chawdhry wrote:
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry
---
Hi Simon,
On Sat, 2 Dec 2023 at 20:28, Simon Glass wrote:
>
> Hi Ilias,
>
> On Wed, 29 Nov 2023 at 23:50, Ilias Apalodimas
> wrote:
> >
> > Hi Simon,
> >
> > [...]
> >
> >> > Changes since v1:
> >> > - Tokenize the DT node entry and use the appropriate value instead of
> >> > the entire
On Tue, Dec 05, 2023 at 11:48:26PM +0100, Jonas Karlman wrote:
> Hi Chris,
>
> On 2023-12-05 22:39, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
> > UART, ADC, eMMC, and SDMMC are tested to work.
> >
> > Signed-off-by:
On Wed, Dec 6, 2023 at 7:12 PM Michal Simek wrote:
>
>
>
> On 12/6/23 14:28, Jagan Teki wrote:
> > On Wed, Dec 6, 2023 at 6:11 PM Michal Simek wrote:
> >>
> >>
> >>
> >> On 12/6/23 13:24, Jagan Teki wrote:
> >>> On Fri, Aug 18, 2023 at 9:51 AM Ashok Reddy Soma
> >>> wrote:
>
> This
The mv88e6xxx driver does not currently initialize the smi_addr field, but
instead keeps the default zero value. This leads to driver being unusable
on devices where the switch is not on address zero of the mdio bus. Fix
this problem by reading the SMI address from device tree.
Signed-off-by:
On 12/6/23 14:28, Jagan Teki wrote:
On Wed, Dec 6, 2023 at 6:11 PM Michal Simek wrote:
On 12/6/23 13:24, Jagan Teki wrote:
On Fri, Aug 18, 2023 at 9:51 AM Ashok Reddy Soma
wrote:
This series adds support for Xilinx qspi parallel and stacked memeories.
In parallel mode, the current
Introduce the basic j784s4 SoC dts from the v6.7-rc1 tag of the
linux kernel.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/k3-j784s4-evm.dts | 981 +++
arch/arm/dts/k3-j784s4-main.dtsi | 2068
On Wed, Dec 6, 2023 at 6:11 PM Michal Simek wrote:
>
>
>
> On 12/6/23 13:24, Jagan Teki wrote:
> > On Fri, Aug 18, 2023 at 9:51 AM Ashok Reddy Soma
> > wrote:
> >>
> >> This series adds support for Xilinx qspi parallel and stacked memeories.
> >>
> >> In parallel mode, the current implementation
On Tue, Dec 05, 2023 at 20:54, Simon Glass wrote:
> Hi Mattijs,
>
> On Tue, 5 Dec 2023 at 02:16, Mattijs Korpershoek
> wrote:
>>
>> Hi Simon,
>>
>> Thank you for your patch.
>>
>> On dim., déc. 03, 2023 at 17:31, Simon Glass wrote:
>>
>> > Given the name of this variable, it should be an
Hi Simon,
- gzip u-boot::
gzip u-boot-nodtb.bin
- Append dtb to gzipped u-boot::
cat u-boot-nodtb.bin.gz
/arch/arm64/boot/dts/qcom/your-board.dtb >
u-boot-nodtb.bin.gz-dtb
>>>
>>> What is this?? Who or what uses a gzipped image with a
On 12/6/23 13:24, Jagan Teki wrote:
On Fri, Aug 18, 2023 at 9:51 AM Ashok Reddy Soma
wrote:
This series adds support for Xilinx qspi parallel and stacked memeories.
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits
Add maintainership for new J784S4 files added.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/MAINTAINERS | 25 +
1 file changed, 25 insertions(+)
create mode 100644 board/ti/j784s4/MAINTAINERS
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
TI K3 J784S4 and AM69 are new additions to the K3 SoC family.
Add documentation about the J784S4 EVM and AM69 SK.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
doc/board/ti/j784s4_evm.rst | 303
doc/board/ti/k3.rst | 1 +
2 files
From: Dasnavis Sabiya
Add config fragments for am69_sk A72 and R5 configuration.
This applies on to:
j784s4_evm_a72_defconfig -> am69_sk_a72.config
j784s4_evm_r5_defconfig -> am69_sk_r5.config
The usage model (with the fragment) would be:
make j784s4_evm_a72_defconfig am69_sk_a72.config
make
Add defconfigs for building R5 U-Boot SPL and A72 U-Boot.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
configs/j784s4_evm_a72_defconfig | 180 +++
configs/j784s4_evm_r5_defconfig | 163
2 files changed, 343 insertions(+)
memory node is used by fdtdec_setup_mem_size_base() and
fdtdec_setup_memory_banksize() during dram_init(), so use
bootph-all to enable for all stages.
Signed-off-by: Apurva Nandan
---
arch/arm/dts/k3-am69-sk-u-boot.dtsi| 6 ++
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 6 ++
2 files
From: Dasnavis Sabiya
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am69-r5-sk.dts |
Add env file with necessary boot variables.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/j784s4.env | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 board/ti/j784s4/j784s4.env
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
new file mode
Add board files for J784S4 EVM.
Signed-off-by: Hari Nagalla
[ add env and board specific yaml files for binman ]
Signed-off-by: Neha Malcom Francis
[ cleaned up the env files ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
Add support for DMA in J784S4 SoC.
Signed-off-by: Jayesh Choudhary
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j784s4.c | 166 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
Add clk and device data which can be used by respective drivers
to configure clocks and PSC.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/r5/j784s4/Makefile| 7 +
arch/arm/mach-k3/r5/j784s4/clk-data.c | 428 +
Add support for J784S4 SoC Identification.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/include/mach/hardware.h | 1 +
drivers/soc/soc_ti_k3.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/hardware.h
Sort JTAG_IDs for K3 SoCs in hardware.h in alphabetical order.
Signed-off-by: Apurva Nandan
Reviewed-by: Nishanth Menon
---
arch/arm/mach-k3/include/mach/hardware.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/include/mach/hardware.h
Add J784S4 initialization files for initial SPL boot.
Signed-off-by: Hari Nagalla
[ add firewall configurations and change the R5 MCU scratchpad ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/Kconfig |
From: Dasnavis Sabiya
Introduce the basic am69-sk evm dts from the v6.7-rc1 tag of the
linux kernel.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am69-sk.dts | 900
2 files changed,
Hello Everyone!
This series will introduce basic support (SD and UART) support for Texas
Instruments J784S4 EVM.
The J784S4 SoC device tree patches are taken from kernel patch submissions
and will be updated as they are accepted and merged to the kernel tree.
All other patches are specific to
On Thu, Jul 27, 2023 at 3:14 AM Jonas Karlman wrote:
>
> Add support for Silicon Kaiser sk25lp128 SPI NOR flash found in Pine64
> PinePhone Pro and PineTab2.
>
> Signed-off-by: Jonas Karlman
> ---
Applied to u-boot-spi/master
On Sat, Aug 12, 2023 at 8:37 AM SSunk wrote:
>
> Add XMC XM25QH128C/XM25QH256C/XM25QU256C/XM25QH512C/XM25QU512C
> site: https://www.xmcwh.com/site/product
>
> Signed-off-by: Kankan Sun
> ---
> configs/evb-ast2600_defconfig | 1 +
> drivers/mtd/spi/spi-nor-ids.c | 4
> 2 files changed, 5
On Sat, Aug 12, 2023 at 7:34 AM William Zhang
wrote:
>
> When build for arm64 target, comipler reports the following warning:
> drivers/spi/bcm63xx_hsspi.c: In function ‘bcm63xx_hsspi_xfer_dummy_cs’:
> include/linux/kernel.h:184:17: warning: comparison of distinct pointer
> types lacks a cast
>
On Fri, Aug 18, 2023 at 9:51 AM Ashok Reddy Soma
wrote:
>
> This series adds support for Xilinx qspi parallel and stacked memeories.
>
> In parallel mode, the current implementation assumes that a maximum of
> two flashes are connected. The QSPI controller splits the data evenly
> between both
On Sun, Nov 19, 2023 at 6:55 PM Mark Kettenis wrote:
>
> > Date: Sat, 18 Nov 2023 23:52:11 +0100
> > From: Heinrich Schuchardt
>
> Hi Heinrich,
>
> > On 11/18/23 22:28, Shantur Rathore wrote:
> > > Hi Heinrich,
> > >
> > > On Fri, Nov 17, 2023 at 3:12 PM Heinrich Schuchardt
> > > wrote:
> > >>
On Thu, Nov 30, 2023 at 2:45 AM Simon Glass wrote:
>
> Hi Ilias,
>
> On Mon, 27 Nov 2023 at 10:11, Ilias Apalodimas
> wrote:
> >
> > In order to fill in the SMBIOS tables U-Boot currently relies on a
> > "u-boot,sysinfo-smbios" compatible node. This is fine for the boards
> > that already
On Mon, Nov 27, 2023 at 5:11 PM Ilias Apalodimas
wrote:
>
> In order to fill in the SMBIOS tables U-Boot currently relies on a
> "u-boot,sysinfo-smbios" compatible node. This is fine for the boards
> that already include such nodes. However with some recent EFI changes,
> the majority of boards
> From: Peter Robinson
> Date: Wed, 6 Dec 2023 10:44:59 +
>
> On Wed, Dec 6, 2023 at 9:31 AM Heinrich Schuchardt
> wrote:
> >
> > On 05.12.23 07:23, Masahisa Kojima wrote:
> > > Hi Heinrich,
> > >
> > > On Tue, 5 Dec 2023 at 11:38, Heinrich Schuchardt
> > > wrote:
> > >>
> > >> * Only
On 06/12/2023 10:44, Ilias Apalodimas wrote:
> Hi Tom,
>
> On Wed, 22 Nov 2023 at 16:28, Tom Rini wrote:
>>
>> On Wed, Nov 22, 2023 at 07:44:09PM +0530, Sumit Garg wrote:
>>> On Wed, 22 Nov 2023 at 19:31, Tom Rini wrote:
On Wed, Nov 22, 2023 at 11:51:29AM +0530, Sumit Garg wrote:
Hi Simon,
On 06/12/2023 03:54, Simon Glass wrote:
> Hi Caleb,
>
> On Tue, 5 Dec 2023 at 06:48, Caleb Connolly wrote:
>>
>> Use the upstream gpio-ranges property instead of gpio-count, and drop
>> the bank-name property for Qualcomm boards.
>>
>> Reviewed-by: Neil Armstrong
>> Reviewed-by:
Hi Mark,
On Wed, 6 Dec 2023 at 13:00, Mark Kettenis wrote:
>
> > From: Ilias Apalodimas
> > Date: Wed, 6 Dec 2023 12:31:15 +0200
> >
> > Hi Caleb,
> >
> > Late to the party, but I'll respond to as much as I can
> >
> > On Tue, 21 Nov 2023 at 19:09, Caleb Connolly
> > wrote:
> > >
> > >
[...]
>
>>
>> > str = "Unknown";
>> >
>> > for (;;) {
>> > @@ -151,8 +151,7 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx,
>> > const char *prop,
>> > const char *str;
>> >
>> > str = ofnode_read_string(ctx->node, prop);
>> > -
> From: Ilias Apalodimas
> Date: Wed, 6 Dec 2023 12:31:15 +0200
>
> Hi Caleb,
>
> Late to the party, but I'll respond to as much as I can
>
> On Tue, 21 Nov 2023 at 19:09, Caleb Connolly
> wrote:
> >
> > Historically, Qualcomm boards in U-Boot have all had their own
> > board/qualcomm/xyz
On Mon, 4 Dec 2023 at 20:55, Raymond Mao wrote:
>
> Hi Ilias,
>
> What is the difference between the new added XFERLIST_EVLOG and the existing
> BLOBLISTT_TPM2_TCG_LOG and BLOBLISTT_TCPA_LOG in U-Boot?
>
I am not really sure what the existing options are supposed to mean.
Having discrete
Hi Tom,
On Wed, 22 Nov 2023 at 16:28, Tom Rini wrote:
>
> On Wed, Nov 22, 2023 at 07:44:09PM +0530, Sumit Garg wrote:
> > On Wed, 22 Nov 2023 at 19:31, Tom Rini wrote:
> > >
> > > On Wed, Nov 22, 2023 at 11:51:29AM +0530, Sumit Garg wrote:
> > > > Hi Caleb,
> > > >
> > > > On Tue, 21 Nov 2023
On Wed, Dec 6, 2023 at 9:31 AM Heinrich Schuchardt
wrote:
>
> On 05.12.23 07:23, Masahisa Kojima wrote:
> > Hi Heinrich,
> >
> > On Tue, 5 Dec 2023 at 11:38, Heinrich Schuchardt
> > wrote:
> >>
> >> * Only generate removable media entries for EFI system partitions.
> >> * Only offer EFI system
On Wed, 6 Dec 2023 at 13:06, Soeren Moch wrote:
> On 05.12.23 21:00, Maxim Uvarov wrote:
>
> On Wed, 6 Dec 2023 at 00:25, Soeren Moch wrote:
>
>> On 05.12.23 17:25, Maxim Uvarov wrote:
>>
>> On Tue, 5 Dec 2023 at 21:49, Soeren Moch wrote:
>>
>>> On 05.12.23 14:15, Maxim Uvarov wrote:
>>>
>>> I
Hi Caleb,
Late to the party, but I'll respond to as much as I can
On Tue, 21 Nov 2023 at 19:09, Caleb Connolly wrote:
>
> Historically, Qualcomm boards in U-Boot have all had their own
> board/qualcomm/xyz directory, their own CONFIG_TARGET_XYZ option, their
> own hardcoded sysmap-xyz.c file,
This commit adds a general flow to explain the usage of firewalls and
the chain of trust in K3 devices.
Signed-off-by: Manorit Chawdhry
---
doc/board/ti/k3.rst | 45 +
1 file changed, 45 insertions(+)
diff --git a/doc/board/ti/k3.rst
The previous documentation had been very crude so refactor it to make it
cleaner and concise.
Signed-off-by: Manorit Chawdhry
---
doc/board/ti/k3.rst | 270 +---
1 file changed, 171 insertions(+), 99 deletions(-)
diff --git a/doc/board/ti/k3.rst
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry
---
arch/arm/dts/k3-j7200-binman.dtsi | 152
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry
---
arch/arm/dts/k3-j721s2-binman.dtsi | 217
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry
---
arch/arm/dts/k3-j721e-binman.dtsi | 196
For readability during configuring firewalls, adding k3-security.h file
and including it in k3-binman.dtsi to be accessible across K3 SoCs
Reviewed-by: Simon Glass
Signed-off-by: Manorit Chawdhry
---
arch/arm/dts/k3-binman.dtsi | 2 ++
arch/arm/dts/k3-security.h | 58
Add test for TI firewalling node in ti-secure.
Reviewed-by: Simon Glass
Signed-off-by: Manorit Chawdhry
---
tools/binman/ftest.py | 23 ++
tools/binman/test/324_ti_secure_firewall.dts | 28 ++
We can now firewall entities while loading them through our secure
entity TIFS, the required information should be present in the
certificate that is being parsed by TIFS.
The following commit adds the support to enable the certificates to be
generated if the firewall configurations are present
K3 devices have firewalls that are used to prevent illegal accesses to
memory regions that are deemed secure. The series prevents the illegal
accesses to ATF and OP-TEE regions that are present in different K3
devices.
AM62X, AM62AX and AM64X are currently in hold due to some firewall
From: Venkatesh Yadav Abbarapu
GIGADEVICE nor flashes provide block protection support using
BP0, BP1, BP2, BP3 & TB bits in status register.
BP(Block Protection) bits defines memory to be software
protected against PROGRAM or ERASE operations. When one or more
block protect bits are set to 1,
From: Venkatesh Yadav Abbarapu
Spansion nor flashes provide block protection support using
BP0, BP1, BP2 bits in status register.
The top/bottom select is instead done via a bit in the configuration
register, which is OTP, so once set to use bottom protect, one cannot
use top. On top of that,
From: Venkatesh Yadav Abbarapu
ISSI chips implements locking in (power-of-two multiple of) 64K
blocks, not as a fraction of the chip's size. Bit 5 in the status
register is not a top/bottom select bit, but instead a fourth value
bit, allowing locking between 2^0 and 2^14 64K blocks (so up to
From: Venkatesh Yadav Abbarapu
Macronix chips implements locking in (power-of-two multiple of) 64K
blocks, not as a fraction of the chip's size. Bit 5 in the status
register is not a top/bottom select bit, but instead a fourth value
bit, allowing locking between 2^0 and 2^14 64K blocks (so up to
From: T Karthik Reddy
Micron nor flashes provide block protection support using
BP0, BP1, BP2, BP3 & TB bits in status register. This patch
supports for micron nor flashes with manufacturer id 0x20
and 0x2c.
Where BP(Block Protection) bits defines memory to be software
protected against PROGRAM
The Cadence driver must switch between SDR and DTR modes based
on commands from the SPI-NOR framework and the configuration
set by SPI_FLASH_DTR_ENABLE. If SPI_FLASH_DTR_ENABLE is enabled,
the driver should transition to DTR mode; if it is not defined,
the driver should avoid switching to DTR
Activate the xSPI Software Reset support, which will be
utilized to transition from octal DTR mode to legacy
mode during shutdown and boot (if enabled).
Signed-off-by: T Karthik Reddy
Signed-off-by: Tejas Bhumkar
---
configs/xilinx_versal_virt_defconfig | 2 ++
1 file changed, 2 insertions(+)
From: Ashok Reddy Soma
Incase of non-aligned length of flash data, ahbbase address is written
directly with byte count. This is causing AHB bus error's sometimes and
resulting in kernel crash while booting linux. To avoid this write 4 byte
aligned byte count to ahbbase address.
Also use a
From: T Karthik Reddy
In DDR mode, current default spi_mem_dtr_supports_op() function does
not allow mixed DTR operation functionality. So implement cadence
specific cadence_spi_mem_dtr_supports_op() function to verifying only
the command buswidth and command opcode bytes which satisfies the DTR
From: Ashok Reddy Soma
Enable ECO bit for Versal for frequencies above 120Mhz
for octal spi to work properly.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/spi/cadence_qspi.h | 1 +
drivers/spi/cadence_qspi_apb.c | 4
2 files changed, 5 insertions(+)
diff
From: Ashok Reddy Soma
tshsl_ns is the clock delay for chip select deassert. This is the delay in
master reference clocks for the length that the master mode chip select
outputs are de-asserted between transactions.
The minimum delay is always SCLK period to ensure the chip select is never
To reduce the CPU load in waiting for the OSPI internal SRAM to
clear in indirect mode, it's better to use the
CQSPI_REG_IRQSTATUS register to check for indirect operation to complete.
Enabled interrupt for Indirect Complete and Transfer Watermark
Breach interrupt status register bits and using
From: Ashok Reddy Soma
Read and Write watermark registers are not initialized. Set read
watermark to half of the FIFO and write watermark to 1/8 of the
FIFO size.
Read watermark indicates if SRAM fill level is above this watermark,
interrupt will be generated and read or DMA can be performed.
From: Ashok Reddy Soma
This patch cleans up the cadence qspi registers in the init.
The register contents may be invalid if this controller is
used in previous boot and comes to uboot after a softreset
(no power on reset). This may cause issues in uboot.
Signed-off-by: Ashok Reddy Soma
From: T Karthik Reddy
Set cmd, address & data buswidth to octal. Handle dummy clock
cycles incase of reads & writes. Convert odd bytes to even
bytes lengths in ddr mode, as we cannot rx/tx odd data in
ddr mode.
Disable the DMA once the transfer is done to avoid disabling
it at other places.
From: T Karthik Reddy
To switch the OSPI controller from SDR to DDR mode, the
RX delay should be configured through flash tuning. Begin
by establishing a constant value for the TX delay and then
increase the RX delay by inspecting the flash IDs. To fine-tune
the RX delay, compare the flash IDs
From: T Karthik Reddy
Cadence driver need to switch from SDR to DTR and vice versa based on
the commands from spi-nor framework and based on SPI_FLASH_DTR_ENABLE
config. If SPI_FLASH_DTR_ENABLE is not defined, do not switch to DTR
mode as it represents that controller does not support DTR. Also
From: Ashok Reddy Soma
With 'commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map")', support
for spi_nor_parse_sccr is added under SFDP. But the flag
SNOR_F_IO_MODE_EN_VOLATILE in spi_nor_octal_dtr_enable is always
checked. Check this flag only if SPI_FLASH_SFDP_SUPPORT enabled.
If the system is in a dual parallel configuration, it's necessary to
halve the erase size since the erase command operates on two flashes
simultaneously. When dealing with a dual-stacked configuration,
determine whether the erase offset refers to the top or bottom flash,
and subsequently, adjust
From: Ashok Reddy Soma
Write enable(06h) command will be sent to a flash device to
set the write enable latch bit before every program, erase,
write command. After that write disable command (04h) needs
to be sent to clear the write enable latch.
This write_disable() is missing at the majority
From: T Karthik Reddy
Added support to program quad enable bit for Winbond flash memory.
Previously, the quad enable function from Spansion was used for
this purpose. However, for Winbond flash memory, the quad
enable bit is configured by programming the Write Status Register-2
(SR-2) rather
From: Venkatesh Yadav Abbarapu
The block protection flags for Gigadevice, Spansion, and ISSI flash
memory have been modified. Additionally, new flags for
SPI_NOR_OCTAL_DTR_READ and octal DTR page programming have been
introduced for Micron OSPI flashes. Furthermore, the flashes mt35xu01g
and
From: Algapally Santosh Sagar
Add support for Winbond 256MB flash W25Q02NW which supports 4byte
opcodes and also dual and quad read.
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-ids.c | 6 ++
1 file
From: T Karthik Reddy
Some flash devices have multiple dies in it & has die cross over
issue. When SPI_NOR_MULTI_DIE flag is set in flash id table use
it to enable split reads to avoid above issue. Define SPI_NOR_MULTI_DIE
new flag to flash id flags. Remove SPI_FLASH_SPLIT_READ config and
From: Ashok Reddy Soma
Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table,
enable octal DTR page program in the framework.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 3 ++-
2
From: Ashok Reddy Soma
In a dual parallel configuration, halve the read offset.
Determine whether the read offset points to the lower or
upper flash in a dual stacked configuration and set the
corresponding flags accordingly.
Include support for cases where the read involves an odd
number of
From: Ashok Reddy Soma
Enable mt35xu512aba_fixups for all mt35 series flashes to work
in DTR mode, and return after nor->fixups is updated, otherwise
it will get overwritten with macronix_octal_fixups.
This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU
is enabled and
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