Hi Francesco,
> On Wed, Sep 10, 2025 at 02:28:21PM +0200, Łukasz Majewski wrote:
> > Hi Francesco,
> >
> > > Hello,
> > >
> > > On Tue, Sep 09, 2025 at 07:08:34PM +0300, Svyatoslav Ryhel wrote:
> > >
> > > > вт, 9 вер. 2025 р. о 18:47 Tom Rini пише:
> > > >
> > > > >
> > > > ...
> Subject: [PATCH v2 3/3] mmc: socfpga_dw_mmc: Enable/disable
> SDMMC clock via API
>
> From: Alif Zakuan Yuslaimi
>
> Update the driver to enable or disable the SDMMC clock via clock
> driver model API instead of doing it in the driver itself.
>
> This allows for scalability of the driver for
> Subject: [PATCH v2 1/3] include: dt-bindings: clk: agilex: Add Agilex
> clock definitions header file
> From: Alif Zakuan Yuslaimi
>
> Introduce header file to define the clock indexes for the Agilex platform.
>
> Signed-off-by: Alif Zakuan Yuslaimi
> ---
> include/dt-bindings/clock/agilex-c
Hi Marek
On 28-Aug-25 8:50 PM, Marek Vasut wrote:
On 8/28/25 8:36 AM, Naresh Kumar Ravulapalli wrote:
Add support for reading data or images from ISSI QSPI flash.
Which part does this implement/fix/.. ? Details please.
We are just adding ISSI QSPI to be supported by SPI NOR tiny; just like
On 9/11/25 05:28, Marek Vasut wrote:
On 9/10/25 9:26 AM, Michal Simek wrote:
In case of ENV_INVALID (uninitialized variables) the first env location
should be used for storing variables.
That's why change the logic how env_valid is setup to be aligned with
offset calculation.
This will also f
On 10/09/25 20:26, Bryan Brattlof wrote:
On June 16, 2025 thus sayeth Hrushikesh Salunke:
This patch series adds support for booting over PCIe on TI AM64X SoC.
AM64X contains single instance of PCIe controller, which can operate in
endpoint mode to support PCIe boot. This series:
- Adds PCIe
Fix the incorrect bit masking and bit shift used to compute EMAC
control which in turn is used to select EMAC clock from EMAC
source A or B.
Signed-off-by: Naresh Kumar Ravulapalli
---
drivers/clk/altera/clk-agilex.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Required configurations for USB 3.1 are enabled for Agilex5
boards. Testing has been successfully carried out on Agilex5
devkits.
Changes in v3:
- Changed commit message to state debounce issue explicitly
Naresh Kumar Ravulapalli (4):
arch: arm: dts: Enable USB3.1 for Agilex5
configs: Enable
FIELD_GET() macro is used during EMAC clock source selection
for better code readability and maintainability.
Signed-off-by: Naresh Kumar Ravulapalli
---
drivers/clk/altera/clk-agilex.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex.c
Changes in v3:
- Revert license change
- Separate fixing mask issue and using FIELD_GET() macro
into two different patches
Naresh Kumar Ravulapalli (2):
drivers: clk: agilex: Fix EMAC clock source selection
drivers: clk: agilex: Use FIELD_GET during EMAC clock selection
drivers/clk/altera/c
This patch addresses silicon errata i2478 [0] "MMCSD0: HS400 Mode not
supported". Where, eMMC HS400 mode is not supported due to bus timing
limitations. As per workaround, use HS200 mode instead.
[0] https://www.ti.com/lit/pdf/sprz575
Signed-off-by: Judith Mendez
---
configs/j722s_evm_a53_defcon
Due to the logic in spl_mmc_boot_mode() for am62p device. Support
for eMMC boot depends on this config option, so enable the config
for now at r5 stage.
Signed-off-by: Judith Mendez
---
configs/am62px_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am62px_evm_r5_defc
For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.
Signed-off-by: Naresh Kumar Ravulapalli
---
.../include/mach/sy
Some legacy USB mass storage devices during connection were
observed to have debounce issues. Hence, increasing the default
USB Hub debounce timeout value to handle this issue for devices
connected to Agilex5 boards.
Signed-off-by: Naresh Kumar Ravulapalli
---
configs/socfpga_agilex5_defconfig |
USB 3.1 node is enabled for Agilex5.
Signed-off-by: Naresh Kumar Ravulapalli
---
arch/arm/dts/socfpga_agilex5_socdk.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts
b/arch/arm/dts/socfpga_agilex5_socdk.dts
index 2ab143e38f8..86e6d374948 100644
On Thu Sep 11, 2025 at 3:15 AM IST, Judith Mendez wrote:
> For all K3 SoC's eMMC boot and MMCSD boot modes are supported. The macros
> however, mix MMC device with the two bootmodes. Decouple the two types
> of macros so that bootmodes can be identified with:
> - BOOT_DEVICE_MMCSD
> - BOOT_DEVICE_E
From: Alice Guo
Define the daisy register offset for i.MX94 at 0x608 within the iomuxc
register space. This enables correct pad selection for daisy chain
configuration on i.MX94 platforms.
Signed-off-by: Jacky Bai
Signed-off-by: Alice Guo
Acked-by: Peng Fan
---
drivers/pinctrl/nxp/pinctrl-im
Anbernic RG353M is hardware compatible with RG353P. Only the form-factor
differs. So only one DTS is created for both machines with
"Anbernic RG353P" as default model. If a RG353M is detected, the model
should be overwritten with the correct name.
Actually, it's overwritten with "Anbernic" only mak
Hey Tom, could I get some feedback on how I can get my patch accepted?
I am a bit new to this, sorry.
--
Thanks,
Sidharth Seela
From: Ye Li
Extend get_imageset_end() to handle i.MX94 family.
Signed-off-by: Ye Li
Signed-off-by: Jacky Bai
Signed-off-by: Alice Guo
Acked-by: Peng Fan
---
arch/arm/mach-imx/image-container.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/image-co
On 9/11/2025 3:15 AM, Judith Mendez wrote:
For all K3 SoC's eMMC boot and MMCSD boot modes are supported. The macros
however, mix MMC device with the two bootmodes. Decouple the two types
of macros so that bootmodes can be identified with:
- BOOT_DEVICE_MMCSD
- BOOT_DEVICE_EMMC
Few devices al
On 9/11/2025 3:15 AM, Judith Mendez wrote:
This patch addresses silicon errata i2478 [0] "MMCSD0: HS400 Mode not
supported". Where, eMMC HS400 mode is not supported due to bus timing
limitations. As per workaround, use HS200 mode instead.
[0] https://www.ti.com/lit/pdf/sprz575
Signed-off-by: J
On Sep 05, 2025 at 13:48:55 +0530, Anshul Dalal wrote:
> In dcache_enable, currently the dcache entries are only invalidated when
> the MMU is not enabled. This causes issues when dcache_enable is called
> with the MMU already configured, in such cases the existing dcache
> entries are not flushed
On 9/10/25 9:26 AM, Michal Simek wrote:
In case of ENV_INVALID (uninitialized variables) the first env location
should be used for storing variables.
That's why change the logic how env_valid is setup to be aligned with
offset calculation.
This will also fix the print about Valid environment is s
> -Original Message-
> From: Yuslaimi, Alif Zakuan
> Sent: Tuesday, September 9, 2025 10:11 AM
> To: u-boot@lists.denx.de
> Cc: Tom Rini ; Lukasz Majewski ;
> Sean Anderson ; Peng Fan ;
> Jaehoon Chung ; Chee, Tien Fong
> ; Simon Glass ; Marek
> Vasut ; Simon Goldschmidt
> ; Yuslaimi, A
> -Original Message-
> From: Yuslaimi, Alif Zakuan
> Sent: Tuesday, September 9, 2025 10:11 AM
> To: u-boot@lists.denx.de
> Cc: Tom Rini ; Lukasz Majewski ;
> Sean Anderson ; Peng Fan ;
> Jaehoon Chung ; Chee, Tien Fong
> ; Simon Glass ; Marek
> Vasut ; Simon Goldschmidt
> ; Yuslaimi, A
Hi Alice,
On 9/1/25 03:48, Alice Guo (OSS) wrote:
> From: Ye Li
>
> - Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94.
> - Introduce common.h with macros of clock IDs, power domains, and CPU
> types for platform-specific replacement (e.g., i.MX94, i.MX95).
> - Extend imx_get_mac
From: Peng Fan
System Manager provides the last booted and shutdown reasons of the
logical machines (LM) and system using the SCMI misc protocol (Protocol
ID: 0x84, Message ID: 0xA). This path adds get_reset_reason() to query
and print these reasons in SPL and U-Boot.
Signed-off-by: Peng Fan
Si
From: Ye Li
Update get_reset_reason() to support i.MX94 to send message to the
System Manager to retrieve the LM/system last booted/shutdown reasons.
Signed-off-by: Ye Li
Signed-off-by: Alice Guo
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx9/scmi/soc.c | 39 +++
From: Ye Li
- Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94.
- Introduce common.h with macros of clock IDs, power domains, and CPU
types for platform-specific replacement (e.g., i.MX94, i.MX95).
- Extend imx_get_mac_from_fuse() to support i.MX94.
Signed-off-by: Ye Li
Signed-o
From: Ye Li
Introduce support for the new i.MX94 processor, including its CPU type
and SoC-level Kconfig entry.
The i.MX94 is a new member of the i.MX9 family. It uses a System Manager
to handle system-level functions such as power, clock, sensor and pin
control. The System Manager runs on a Cor
For all K3 SoC's eMMC boot and MMCSD boot modes are supported. The macros
however, mix MMC device with the two bootmodes. Decouple the two types
of macros so that bootmodes can be identified with:
- BOOT_DEVICE_MMCSD
- BOOT_DEVICE_EMMC
according to devstat parsed boot mode values and on-board devic
This patch series includes some general fixes for MMC on K3 devices.
The first patch fixes the MMC macros used for booting with eMMC boot,
and MMCSD boot.
Subsequent patches fix eMMC boot on AM62P device and fixing eMMC HS400
configs for am62p/j722s devices.
The patch series has been tested with
Update documentation for how to configure Ext4 Write when using large
partitions.
Signed-off-by: Tony Dinh
---
doc/README.ext4 | 11 +++
1 file changed, 11 insertions(+)
diff --git a/doc/README.ext4 b/doc/README.ext4
index 8ecd21eee3b..ca9f19953d2 100644
--- a/doc/README.ext4
+++ b/doc
Hi,
On 8/8/25 17:11, Patrice Chotard wrote:
Octo Memory Manager driver (OMM) manages:
- the muxing between 2 OSPI busses and 2 output ports.
There are 4 possible muxing configurations:
- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
output is on port
On Thu, 28 Aug 2025 14:06:57 +0100
Said Nasibov wrote:
Hi,
> This commit updates vexpress64 configs to default to standard boot, and
> explicitly select bootmeth_smh when standard boot is enabled.
>
> The distro boot related variables are deliberately not removed to preserve
> compatibility wit
On Thu, 28 Aug 2025 14:06:56 +0100
Said Nasibov wrote:
Hi Said,
thanks for posting this!
(quite a long CC: list, but missing the semihosting maintainer! ;-) Adding
Sean)
> This commit introduces a new standard boot method that supports booting
> via semihosting as provided by ARM FVP platforms
Hi,
On 8/8/25 17:11, Patrice Chotard wrote:
Add STM32 OSPI driver, it supports :
- support sNOR / sNAND devices.
- Two functional modes: indirect (read/write) and memory-mapped (read).
- Single-, dual-, quad-, and octal-SPI communication.
- Single data rate (SDR).
Signed-off-by: Pat
Enable the DM_RNG virtio random number generator driver in order to
consume entropy within U-Boot. This allows U-Boot to inject entropy to the
kernel via UEFI, so the kernel can use that early, for instance for
address layout randomisation, or when the kernel does not provide an
entropy driver itse
On 9/10/25 22:14, Ferass El Hafidi wrote:
On Wed Sep 10, 2025 at 7:53 PM UTC, Heinrich Schuchardt wrote:
<...>
+static int meson_serial_getc(void)
+{
+ struct meson_uart *const uart = (struct meson_uart
*)CONFIG_VAL(DEBUG_UART_BASE);
+ uint32_t status = readl(&uart->status);
+
+
On Wed Sep 10, 2025 at 7:53 PM UTC, Heinrich Schuchardt wrote:
> <...>
>> +static int meson_serial_getc(void)
>> +{
>> +struct meson_uart *const uart = (struct meson_uart
>> *)CONFIG_VAL(DEBUG_UART_BASE);
>> +uint32_t status = readl(&uart->status);
>> +
>> +if (status & AML_UART_RX_EMP
On Wed Sep 10, 2025 at 7:42 PM UTC, Heinrich Schuchardt wrote:
> <...>
>>> +Building a bl30_new.bin binary
>>> +--
>>> +
>>> +``bl30_new.bin`` has both ``bl30.bin`` and ``bl301.bin`` binary blobs
>>> +bundled. The former is the proper system control processor firmware
>
On Wed Sep 10, 2025 at 7:36 PM UTC, Heinrich Schuchardt wrote:
> <...>
>> +static void amlimage_print_header(const void *buf,
>> + struct image_tool_params *params)
>> +{
>> +const struct amlimage_header *hdr = buf + HEADER_OFFSET;
>> +uint8_t digest[SHA256_SUM_
On 9/7/25 16:36, Ferass El Hafidi wrote:
It is very limited and minimal, only implements putc/puts.
This minimal driver is intended to be used in SPL, and other
size-constrained situations.
Signed-off-by: Ferass El Hafidi
---
drivers/serial/serial.c | 2 +
drivers/serial/serial_meson
On 9/10/25 09:03, Neil Armstrong wrote:
On 07/09/2025 16:36, Ferass El Hafidi wrote:
Add building and usage instructions for SPL.
Signed-off-by: Ferass El Hafidi
---
doc/board/amlogic/index.rst | 1 +
doc/board/amlogic/pre-generated-fip.rst | 9
doc/board/amlogic/spl.rst
On Wed Sep 10, 2025 at 7:36 PM UTC, Heinrich Schuchardt wrote:
> On 9/7/25 16:36, Ferass El Hafidi wrote:
>> From: Jonas Karlman
>>
>> Add support for creating an Amlogic Boot Image that pass CHK in BL1 on
>> Amlogic AArch64 SoCs.
>>
>> Images can optionally be signed for secure boot scenario, h
On 9/7/25 16:36, Ferass El Hafidi wrote:
From: Jonas Karlman
Add support for creating an Amlogic Boot Image that pass CHK in BL1 on
Amlogic AArch64 SoCs.
Images can optionally be signed for secure boot scenario, however
creation of signed images has not been implemented.
Example of how to use
Select SYSRESET on Vexpress64 to enable system reset to support other
features, such as capsule-on-disk. Select SYSRESET_PSCI if PSCI is
inferred from the firmware (via ARM_PSCI_FW).
Select ARM_SMCCC for Vexpress64 boards which in turn selects
ARM_PSCI_FW.
The sysreset uclass unconditionally imple
Add building and usage instructions for SPL.
Reviewed-by: Neil Armstrong
Signed-off-by: Ferass El Hafidi
---
doc/board/amlogic/index.rst | 1 +
doc/board/amlogic/pre-generated-fip.rst | 9
doc/board/amlogic/spl.rst | 77 +
3 files
Hi,
On Sun Sep 7, 2025 at 2:36 PM UTC, Ferass El Hafidi wrote:
> This RFC/RFT patch series adds support for U-Boot SPL booting on Amlogic
> GX SoCs, replacing the historical "bl2.bin" binary that runs as BL2 on
> these boards.
Superseded by v2:
https://lore.kernel.org/all/2
On Sat, 30 Aug 2025 22:39:54 +0200, Heinrich Schuchardt wrote:
> QEMU allows to specify the logical block size via parameter
> logical_block_size of a virtio-blk-device.
>
> The communication channel via virtqueues remains based on 512 byte blocks
> even if the logical_block_size is larger.
>
>
On Wed, 27 Aug 2025 12:38:36 -0600, Tom Rini wrote:
> Whereas in Linux, on ARM there is the notion of delay operations and
> mdelay and udelay are not the same, here we just have udelay and mdelay
> is a trivial wrapper. Tell checkpatch to not complain here.
>
>
Applied to u-boot/next, thanks!
On Fri, 29 Aug 2025 07:41:29 +0530, Bhimeswararao Matsa wrote:
> Replace uint8_t/uint32_t with u8/u32 to match U-Boot style
> (checkpatch PREFER_KERNEL_TYPES). No functional change.
>
>
Applied to u-boot/next, thanks!
[1/1] i2c: davinci: prefer kernel types (u8/u32)
commit: 5964c6f4ef093
On Tue, 26 Aug 2025 12:45:37 -0700, Tony Dinh wrote:
> Add maximum ext4 journal entries to Kconfig. It is necessary since the
> number of journal entries is proportional to disk capacity. For example,
> an ext4 4TB HDD partition could require approximately 500 entries.
>
>
Applied to u-boot/nex
On Thu, Aug 28, 2025 at 06:49:06AM +0530, Bhimeswararao Matsa wrote:
> checkpatch.pl reports that several parentheses in davinci_i2c.c
> are unnecessary. Remove them to clean up the code and silence
> checkpatch warnings.
>
> Signed-off-by: Bhimeswararao Matsa
> ---
> drivers/i2c/davinci_i2c.c
On Tue, 26 Aug 2025 12:37:17 -0700, Tony Dinh wrote:
> Don't invoke ext4fs_deinit() in ext4fs_write() if the failure occurs
> during initialization. It would result in a crash since ext4fs_init()
> has already done that.
>
>
Applied to u-boot/next, thanks!
[1/1] fs: ext4fs: Add initialization
On Sat, 23 Aug 2025 17:21:09 +0200, Jan Kiszka wrote:
> This cannot work (unless qemu-user is registered in binfmt_misc) as the
> tools will be for a different architecture.
>
> Fixes "make cross_tools" in case CONFIG_VIDEO_LOGO is enabled.
>
>
Applied to u-boot/next, thanks!
[1/1] tools: Do
On Wed, Sep 10, 2025 at 10:24:47PM +0530, Sidharth Seela wrote:
> Hey Tom, could I get some feedback on how I can get my patch accepted?
> I am a bit new to this, sorry.
I've assigned it to Heinrich in patchwork and he'll review it soon.
--
Tom
signature.asc
Description: PGP signature
Add kconfig fragments for building SPL binaries for:
· ODROID-C2
· Videostrong KII Pro
· Libre Computer LePotato (1 GB and 2 GB variants)
Reviewed-by: Neil Armstrong
Signed-off-by: Ferass El Hafidi
---
board/amlogic/p200/spl-odroid-c2.config | 37 ++
board/amlog
Add binman configuration to meson-gx-u-boot.dtsi to automate building
bootable images using amlimage.
Signed-off-by: Ferass El Hafidi
Reviewed-by: Neil Armstrong
---
arch/arm/dts/meson-gx-u-boot.dtsi | 142 ++
1 file changed, 142 insertions(+)
diff --git a/a
Add initial boilerplate for U-Boot SPL support on Amlogic.
Signed-off-by: Ferass El Hafidi
---
arch/arm/include/asm/arch-meson/clock-gx.h | 1 +
arch/arm/include/asm/arch-meson/gx.h | 36 ++
arch/arm/mach-meson/Kconfig| 42 ++-
arch/arm/mach-meson/Makefile
This RFC/RFT patch series adds support for U-Boot SPL booting on Amlogic
GX SoCs, replacing the historical "bl2.bin" binary that runs as BL2 on
these boards.
Boards tested:
- Libre Computer LaFrite (S805X, 512 MB)
- Libre Computer LePotato (S905X, 1 GB)
- Videostrong KII Pro (S905)
- Xiaomi Mi
It is very limited and minimal, only implements putc/puts.
This minimal driver is intended to be used in SPL, and other
size-constrained situations.
Signed-off-by: Ferass El Hafidi
---
drivers/serial/serial.c | 2 +
drivers/serial/serial_meson.c | 110
Add a minimal non-DM MMC driver for use in size-constrained
environments.
Signed-off-by: Ferass El Hafidi
---
arch/arm/include/asm/arch-meson/gx.h | 5 +++
drivers/mmc/meson_gx_mmc.c | 75 +++-
2 files changed, 79 insertions(+), 1 deletion(-)
diff --gi
From: Jonas Karlman
Add support for creating an Amlogic Boot Image that pass CHK in BL1 on
Amlogic AArch64 SoCs.
Images can optionally be signed for secure boot scenario, however
creation of signed images has not been implemented.
Example of how to use it:
# Create an amlogic boot image
too
On Wed, Sep 10, 2025 at 03:37:35PM +, Maarten Brock wrote:
> > From: Tom Rini
> >
> > On Tue, Sep 09, 2025 at 04:23:56PM +0200, Kory Maincent wrote:
> > > On Tue, 9 Sep 2025 12:45:10 +
> > > Maarten Brock wrote:
> > >
> > > > > From: Kory Maincent
> > > > >
> > > > > On Mon, 8 Sep 2025 1
Hi,
On 8/8/25 16:03, Patrice Chotard wrote:
From: Gatien Chevallier
Replace RIFSC check access APIs by grant/release access ones that handle
the RIF semaphores.
Signed-off-by: Gatien Chevallier
minor on comit message: unnecessary line between signed-off
Signed-off-by: Patrice Chotard
Hi,
On 8/8/25 16:03, Patrice Chotard wrote:
From: Gatien Chevallier
Fix RIFSC semaphores acquisition by not returning an error when the
current CID already possess the semaphore. Also fix an incorrect mask
for the CID value in the SEMCR register.
Signed-off-by: Gatien Chevallier
Signed-off-b
On June 16, 2025 thus sayeth Hrushikesh Salunke:
> This patch series adds support for booting over PCIe on TI AM64X SoC.
>
> AM64X contains single instance of PCIe controller, which can operate in
> endpoint mode to support PCIe boot. This series:
>
> - Adds PCIe as a valid boot media for AM64X.
Hi,
On 8/8/25 17:11, Patrice Chotard wrote:
Add resource_overlaps() and resource_contains() helpers.
Code copied from kernel source.
Signed-off-by: Patrice Chotard
---
include/linux/ioport.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/linux/ioport.h b/incl
On August 31, 2025 thus sayeth Steffen Kothe:
> Hi together,
>
> AM64X hereby receives support for reset reason printing during boot.
>
> Unfortunately does the AM64X register mapping slighlty differ from
> the AM62X. WDT and PORZ are not part of the reset source register, but
> the mapping remai
On Wed, Sep 10, 2025 at 02:28:21PM +0200, Łukasz Majewski wrote:
> Hi Francesco,
>
> > Hello,
> >
> > On Tue, Sep 09, 2025 at 07:08:34PM +0300, Svyatoslav Ryhel wrote:
> > > вт, 9 вер. 2025 р. о 18:47 Tom Rini пише:
> > > >
> > > ...
> > > > It's a devkit where I'm pretty sure the watchdog
On 9/10/25 15:26, b...@ti.com wrote:
On September 10, 2025 thus sayeth Sverdlin, Alexander:
Hi Bryan!
On Wed, 2025-09-10 at 07:53 -0500, b...@ti.com wrote:
The watchdog requires to have the MCU ESM error source enabled to
trigger a system reboot. When booting HS-SE (security enforced)
device
On September 10, 2025 thus sayeth Sverdlin, Alexander:
> Hi Bryan!
>
> On Wed, 2025-09-10 at 07:53 -0500, b...@ti.com wrote:
> > > > > > > The watchdog requires to have the MCU ESM error source enabled to
> > > > > > > trigger a system reboot. When booting HS-SE (security enforced)
> > > > > > > d
Hi Alexander,
On 8/21/25 18:21, Sverdlin, Alexander wrote:
Dear Daniel, TI team,
On Fri, 2025-08-15 at 09:02 -0700, Daniel Schultz wrote:
The watchdog requires to have the MCU ESM error source enabled to
trigger a system reboot. When booting HS-SE (security enforced)
devices, the MMR registers
Hello Wadim,
The direction of your patch looks good to me, thanks for taking the time
to refactor!
A few comments below:
On Wed Aug 13, 2025 at 3:59 PM IST, Wadim Egorov wrote:
> The current implementation requires every K3 SoC to provide its own
> get_boot_device()/get_*_bootmedia() functions w
In the qemu-sbsa configuration, the GICv3 definition is disabled due to
a typo. After fixing the typo, GICv3 is enabled, however, the GIC register
base address definitions are missing, resulting in a build failure.
This series enables GICv3 and resolves this build error.
Confirming that U-Boot suc
On Sep 05, 2025 at 13:48:54 +0530, Anshul Dalal wrote:
> The mmu_setup function configures the page tables based on the board
> supplied mem_map struct array. It is called implicitly as part of
> dcache_enable but this limits us to only be able to use APIs such as
> mmu_change_region_attr only afte
On Sep 05, 2025 at 13:48:53 +0530, Anshul Dalal wrote:
> U-Boot's provided enable_caches enforces the following sequence:
> icache_enable -> mmu_setup (as part of dcache_enable) -> dcache_enable
>
> Whereas for K3 devices, we would like to add entries to the provided
> static array (k3_mem_map) as
On 07/09/2025 16:36, Ferass El Hafidi wrote:
Add building and usage instructions for SPL.
Signed-off-by: Ferass El Hafidi
---
doc/board/amlogic/index.rst | 1 +
doc/board/amlogic/pre-generated-fip.rst | 9
doc/board/amlogic/spl.rst | 77 +
The config "GIC_V3" seems to be typo, and currently "GICV3" remains
disabled. This should be removed until needed.
Fixes: 5cd4a355e0f0 ("board: synquacer: Add DeveloperBox 96boards EE support")
Signed-off-by: Kunihiko Hayashi
---
arch/arm/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git
If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at
arch/arm/cpu/armv8/start.S.
Signed-off-by: Kunihiko Hayashi
---
include/configs/qemu-sbsa.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h
index aff78160e12a..669d0fe7c58
Hello,
On Tue, Sep 09, 2025 at 07:08:34PM +0300, Svyatoslav Ryhel wrote:
> вт, 9 вер. 2025 р. о 18:47 Tom Rini пише:
> >
> ...
> > It's a devkit where I'm pretty sure the watchdog exists, so we can
> > enable it there and be done. Just because it doesn't use it today
> > doesn't mean it can't use
On 08/09/2025 18:53, Ferass El Hafidi wrote:
On Mon Sep 8, 2025 at 8:24 AM UTC, Neil Armstrong via groups.io wrote:
On 07/09/2025 16:36, Ferass El Hafidi wrote:
Add initial boilerplate for U-Boot SPL support on Amlogic.
Signed-off-by: Ferass El Hafidi
---
arch/arm/include/asm/arch-meson/cl
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