On Mon, Oct 27, 2008 at 1:16 PM, Kumar Gala [EMAIL PROTECTED] wrote:
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
Applied, thanks
Andy
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are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Andy Fleming (1):
Merge branch 'denx'
Becky Bruce (1):
powerpc: fix pci window initialization to work with 4GB DRAM
Kumar Gala (1):
pci/fsl_pci_init: Removed a bunch pointless trailing
On Mon, Oct 27, 2008 at 4:42 PM, Peter Tyser [EMAIL PROTECTED] wrote:
The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx
processors have a 3-bit wide IO_SEL field but have the most
significant bit is wired to 0 so this change should not affect
them.
Signed-off-by: Peter Tyser
On Oct 23, 2008, at 01:47, Kumar Gala wrote:
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
Grabbed this one and the e500mc one, thanks
Andy
On Oct 23, 2008, at 08:17, Dave Liu wrote:
Signed-off-by: Dave Liu [EMAIL PROTECTED]
Applied, thanks
Andy
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On Oct 23, 2008, at 08:18, Dave Liu wrote:
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.
Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Dave Liu (2):
85xx: remove unused config definition
85xx: Fix the incorrect register used for DDR erratum1
Kumar Gala (12):
85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
And thus have I done so. 1-10 applied, thanks
Andy
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On Thu, Oct 23, 2008 at 5:23 PM, Peter Tyser [EMAIL PROTECTED] wrote:
Initial support for Extreme Engineering Solutions XPedite5370 -
a MPC8572-based 3U VPX single board computer with a PMC/XMC
site.
Signed-off-by: Peter Tyser [EMAIL PROTECTED]
---
MAINTAINERS |
On Tue, Oct 21, 2008 at 9:59 AM, Wolfgang Denk [EMAIL PROTECTED] wrote:
Dear Peter Tyser,
Timestamps are not suitable to provide this type of information. If
you care about which code you are running, than make sure to use git.
I do, but the minor annoyance of having the exact same
. Here is the correct request:
Andy Fleming (1):
Have u-boot pass stashing parameters into device tree
Ed Swarthout (5):
pixis do not print long help if not configured
85xx if NUM_CPUS1, print cpu number
mpc8572 additional end-point mode
fsl_law clear enable before
On Fri, Oct 3, 2008 at 10:46 AM, Haiying Wang
[EMAIL PROTECTED] wrote:
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
Applied 1-3, and they were pulled.
On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
[EMAIL PROTECTED] wrote:
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller
On Wed, Oct 8, 2008 at 3:36 PM, Kumar Gala [EMAIL PROTECTED] wrote:
Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following
compile warnings:
cmd_i2c.c:112: warning: missing braces around initializer
cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]')
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Acked-by: Andy Fleming [EMAIL PROTECTED]
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On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
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On Wed, Oct 8, 2008 at 11:37 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
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On Thu, Oct 9, 2008 at 1:25 AM, Ed Swarthout [EMAIL PROTECTED] wrote:
Debug sessions may have left enabled laws.
Changing lawbar with an unkown enabled tgtid could cause problems.
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
On Thu, Oct 9, 2008 at 1:26 AM, Ed Swarthout [EMAIL PROTECTED] wrote:
This allows a second core to restart without causing a PIC reset.
Internal interupt changes:
Enable L2 error interrupt IIVPR0 and give it vector 0x100.
Use correct interrupt (8) for mpc8572 pcie3.
Add pcie3 interrupt (11)
On Wed, Oct 8, 2008 at 11:38 PM, Ed Swarthout
[EMAIL PROTECTED] wrote:
Signed-off-by: Ed Swarthout [EMAIL PROTECTED]
Applied to 85xx-next
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On Thu, Oct 9, 2008 at 10:40 PM, Jason Jin [EMAIL PROTECTED] wrote:
From: Liu Yu [EMAIL PROTECTED]
This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.
Signed-off-by: Liu Yu [EMAIL PROTECTED]
Applied to 85xx-next
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are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
This supercedes the previous pull request. This includes Wolfgang's and Kumar's
patches.
Haiying Wang (3):
Minor fixes for I2C address on MPC8572DS
Add ID EEPROM support for MPC8572DS
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Haiying Wang (3):
Minor fixes for I2C address on MPC8572DS
Add ID EEPROM support for MPC8572DS
Remove redundant #define for MPC8536DS
Jason Jin (1):
Fix the incorrect DDR clk freq
-by: Jason Jin [EMAIL PROTECTED]
Acked-by: Andy Fleming [EMAIL PROTECTED]
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If Kim and Jon approve, I'll pull these 6 patches into my 85xx-next branch.
On Fri, Oct 3, 2008 at 11:36 AM, Haiying Wang
[EMAIL PROTECTED] wrote:
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set
On Tue, Sep 30, 2008 at 11:27 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
We'll need the exported tsec_info to fix up the phy addresses and
tsecs' flags based on the hardware reset configuration words. Thus
we'll use the tsec_info very early and just once at boot time, so
network code won't
On Mon, Sep 22, 2008 at 3:33 PM, Andrew Dyer [EMAIL PROTECTED] wrote:
On Mon, Sep 22, 2008 at 3:11 PM, Wolfgang Denk [EMAIL PROTECTED] wrote:
Dear Stefan, Kim, Andy, Jon Kumar,
in message [EMAIL PROTECTED]
Nobuhiro Iwamatsu wrote:
I did a simple check.
Only powerpc and i386 and sh seem
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Peter Tyser (1):
Support for multiple SGMII/TBI interfaces for TSEC ethernet
drivers/net/tsec.c |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
On Tue, Sep 9, 2008 at 3:15 PM, Kumar Gala [EMAIL PROTECTED] wrote:
I NAK the CONFIG_SHOW_ACTIVITY patch. Please remove this from your
repo. Please see my [PATCH 3/3] lib_ppc/interrupts.c: make
board_show_activity() a weak function posting instead.
I cherry-picked the other commits, though.
On Mon, Sep 8, 2008 at 8:51 AM, Kumar Gala [EMAIL PROTECTED] wrote:
The e500um says the timebase is volatile out of reset. To ensure
TB sync works we need to make sure its zero.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Swapped mftbl,mftbu at Scott's request.. it doesnt mater since TB
On Sat, Sep 6, 2008 at 6:38 PM, Wolfgang Denk [EMAIL PROTECTED] wrote:
Dear Andy,
I have a couple of unapplied patches in my list which seem to fall
into your area of responsibility. Can you please have a look at
these:
4316 07/18 Timur Tabi [U-Boot-Users] [PATCH] Update Freescale
):
85xx: socrates: Enable Lime support.
Andy Fleming (1):
Merge branch 'denx'
Detlev Zundel (1):
85xx: Socrates: Major code update.
Sergei Poselenov (1):
Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Timur Tabi (1):
Update Freescale 85xx boards
On Wed, Aug 27, 2008 at 12:16 AM, Ajeesh Kumar [EMAIL PROTECTED] wrote:
hi sir/madam,
I'm using a MPC8548E processor(power pc) also, i've interfaced a nor flash
of 128 MB to the processor.
i've read few documents and got to know that the uboot.bin should be
programmed at 0xfff8.
Also,
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Anatolij Gustschin (1):
85xx: socrates: Enable Lime support.
Andy Fleming (1):
Remove CONFIG_SHOW_ACTIVITY from stx boards which don't support it
Detlev Zundel (1):
85xx: Socrates: Major
are available in the git repository at:
git://www.denx.de/git/u-boot-mpc85xx.git master
Jon Loeliger (5):
FSL DDR: Convert MPC8560ADS to new DDR code.
FSL DDR: Convert MPC8555ADS to new DDR code.
FSL DDR: Convert MPC8541CDS to new DDR code.
FSL DDR: Convert MPC8548CDS
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