[U-Boot] [v3 09/30] arm: socfpga: add define for bootinfo bsel bit shift

From: Tien Fong Chee On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by: Dinh

[U-Boot] [v3 08/30] arm: socfpga: arria10: add config option build for arria10

From: Tien Fong Chee Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [v3 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Tien Fong Chee Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut

[U-Boot] [v3 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Tien Fong Chee Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Acked-by: Marek Vasut Cc: Marek Vasut Cc: Dinh

[U-Boot] [v3 04/30] arm: socfpga: arria10: add system manager defines

From: Tien Fong Chee Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 05/30] arm: socfpga: arria10: add misc functions for Arria10

From: Tien Fong Chee Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen Signed-off-by: Tien

[U-Boot] [v3 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Tien Fong Chee Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [v3 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Tien Fong Chee Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Reviewed-by: Stefan Roese Cc: Marek Vasut Cc:

[U-Boot] [v3 02/30] arm: socfpga: arria10: add sdram defines for Arria10

From: Tien Fong Chee Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc:

Re: [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

On Jum, 2016-12-30 at 06:14 -0600, Dinh Nguyen wrote: > > On 12/28/2016 12:34 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This patch adding the Arria10 critical hardware initialization > > be

Re: [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

On Jum, 2016-12-30 at 20:04 +0100, Marek Vasut wrote: > On 12/29/2016 05:54 AM, Chee, Tien Fong wrote: > > > > On Kha, 2016-12-29 at 00:51 +0100, Marek Vasut wrote: > > > > > > On 12/28/2016 07:34 AM, Chee Tien Fong wrote: > > > > > > > >

[U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Dinh Nguyen On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to

[U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10

From: Dinh Nguyen Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Dinh Nguyen There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 9 +++-- 1 file

[U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init

From: Dinh Nguyen These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/socfpga.c | 17 - 1 file changed, 17 deletions(-) diff --git

[U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

From: Dinh Nguyen On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen --- drivers/fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/socfpga.c

[U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Dinh Nguyen The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift

From: Dinh Nguyen On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by:

[U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig

[U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++

[U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Dinh Nguyen The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2

[U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10

From: Dinh Nguyen Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Dinh Nguyen Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- configs/socfpga_arria10_defconfig | 16 1 file

[U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines

From: Tien Fong Chee Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- .../arm/mach-socfpga/include/mach/system_manager.h | 122 + 1 file changed, 122 insertions(+) diff --git

[U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Dinh Nguyen Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- include/configs/socfpga_arria10_socdk.h | 94 + 1 file

[U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Dinh Nguyen Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile | 7 +++

[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Dinh Nguyen Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Reviewed-by: Stefan Roese --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++ 1 file changed, 3

[U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines for Arria10

From: Dinh Nguyen Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 + 1 file changed, 380 insertions(+) create

[U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang

[U-Boot] [PATCH v2 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL.

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - resolved build

[U-Boot] [PATCH v2 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Removed extern

[U-Boot] [PATCH v2 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions. and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [PATCH v2 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee

[U-Boot] [PATCH v2 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [PATCH v2 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro

From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH v2 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- Changes for V2 - Separate patch,

[U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

From: Tien Fong Chee Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH v2 20/30] arm: socfpga: arria10: Enable SPL for Arria 10

From: Tien Fong Chee This patch enables SPL build and implementation for Arria 10. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [PATCH v2 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- changes for v2 - Separate patch for

[U-Boot] [PATCH v2 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH v2 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

From: Chin Liang See Add base address header file for Stratix10 SoC Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen Cc: Ley Foon Tan ---

[U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10

From: Dinh Nguyen On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices. Update the dwmac_deassert_reset function to

[U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10

From: Dinh Nguyen Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits

From: Dinh Nguyen There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 9 +++-- 1 file

[U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices

From: Dinh Nguyen The system manager on Arria10 is not used for pin muxing duties, so wrap these functions for GEN5 devices only. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/system_manager.c | 2 ++ 1 file changed, 2

[U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init

From: Dinh Nguyen These functions are already in arch/arm/mach-socfpga/board.c Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/socfpga.c | 17 - 1 file changed, 17 deletions(-) diff --git

[U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped

From: Dinh Nguyen On the Arria10 device, the bridges are not mapped through the interconnect. Signed-off-by: Dinh Nguyen --- drivers/fpga/socfpga.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/socfpga.c

[U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10

From: Dinh Nguyen The Arria10 device will not be able to re-use the GEN5 SDRAM controller, so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig option in drivers/ddr/altera/Kconfig. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10

From: Dinh Nguyen Add the defines for the reset manager and some basic reset functionality. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++

[U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10

From: Dinh Nguyen Signed-off-by: Dinh Nguyen --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-socfpga/Kconfig | 10 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig

[U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift

From: Dinh Nguyen On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10, the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that the reading the bsel can generic. Suggested-by: Marek Vasut Signed-off-by:

[U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config

From: Dinh Nguyen Add config for the Arria10 SoC Development Kit. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- include/configs/socfpga_arria10_socdk.h | 94 + 1 file

[U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig

From: Dinh Nguyen Add a defconfig file for Arria10, which does not include enabling SPL. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- configs/socfpga_arria10_defconfig | 16 1 file

[U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK

From: Dinh Nguyen Add minimal support for the Arria10 SoCDK. Signed-off-by: Dinh Nguyen --- board/altera/arria10-socdk/Kconfig | 18 ++ board/altera/arria10-socdk/Makefile | 7 +++

[U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10

From: Dinh Nguyen Add arch_early_init_r function. The Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function. Signed-off-by: Dinh Nguyen ---

[U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines

From: Tien Fong Chee Add system manager defines for Arria10. Signed-off-by: Dinh Nguyen --- .../arm/mach-socfpga/include/mach/system_manager.h | 122 + 1 file changed, 122 insertions(+) diff --git

[U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines for Arria10

From: Dinh Nguyen Add the structures for the SDRAM controller on Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 + 1 file changed, 380 insertions(+) create

[U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10

From: Dinh Nguyen Add remaining 3 I2C base addresses for the Arria10. Signed-off-by: Dinh Nguyen Reviewed-by: Stefan Roese --- arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++ 1 file changed, 3

Re: [U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

On Sel, 2016-12-20 at 09:17 -0600, Dinh Nguyen wrote: > > On 12/06/2016 02:11 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This patch adding the Arria10 critical hardware initialization > > be

Re: [U-Boot] [PATCH 08/10] arm: socfpga: arria10: Added drivers for Arria10 clock manager

On Sel, 2016-12-06 at 16:10 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > The drivers is restructured such common functions, gen5 functions, > and arria10 functions are moved to clock_manager.c, cock_manager_gen5 > and clock_manager

Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote: > On 12/19/2016 09:41 AM, Chee, Tien Fong wrote: > > > > On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote: > > > > > > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote: > On 12/19/2016 09:54 AM, Chee, Tien Fong wrote: > > > > On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote: > > > > > > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

On Isn, 2016-12-19 at 08:47 +0100, Marek Vasut wrote: > On 12/19/2016 07:53 AM, Chee, Tien Fong wrote: > > > > On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote: > > > > > > On 12/09/2016 11:04 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote: > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote: > > > > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote: > > > > > > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote: > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote: > > > > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote: > > > > > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote: > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote: > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote: > On 12/09/2016 11:04 AM, Chee, Tien Fong wrote: > > > > On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote: > > > > > > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > This patch adding the Arria10 critical hardware initialization before > enabling console print out in spl. > > Signed-off-by: Tien Fong Chee <tien.fong.c...@i

Re: [U-Boot] [PATCH 09/10] arm: socfpga: arria10: Added drivers for Arria10 pin mux/pins configuration

On Sel, 2016-12-06 at 16:11 +0800, Chee Tien Fong wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > Cc: Marek Vasut <ma...@denx.de> > Cc: Dinh Nguyen <dingu...@kernel.org> > Cc: Chin

Re: [U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

On Rab, 2016-12-07 at 14:52 +0100, Marek Vasut wrote: > On 12/07/2016 11:30 AM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:44 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 08:50 AM, Chee Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote: > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote: > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > > > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

On Rab, 2016-12-07 at 14:58 +0100, Marek Vasut wrote: > On 12/07/2016 12:58 PM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 09:08 AM, Chee Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

On Rab, 2016-12-07 at 14:57 +0100, Marek Vasut wrote: > On 12/07/2016 12:21 PM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 09:07 AM, Chee Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote: > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote: > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > > > > >

Re: [U-Boot] [PATCH 07/10] arm: socfpga: arria10: Added miscellaneous drivers for Arria10

On Sel, 2016-12-06 at 16:26 -0600, dinguyen wrote: > On Tue, 6 Dec 2016, Chee Tien Fong wrote: > > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > The drivers is restructured such common functions, gen5 functions, > > and arria1

Re: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote: > On 12/06/2016 09:08 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Drivers for reset manager is restructured such that common > > functions, > &g

Re: [U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote: > On 12/06/2016 09:07 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > Cc: Marek Vas

Re: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote: > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > These changes to ensure Arria10 SPL build success. > Please reword the commit message, mentio

Re: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote: > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > These compat macros would be used by clock manager and pin mux > > drivers > > to lo

Re: [U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

On Sel, 2016-12-06 at 13:48 +0100, Marek Vasut wrote: > On 12/06/2016 08:52 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > Enhanced defconfig file for Arria10 to enable SPL build and > > supporting > > dev

Re: [U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

On Sel, 2016-12-06 at 13:44 +0100, Marek Vasut wrote: > On 12/06/2016 08:50 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee <tien.fong.c...@intel.com> > > > > This is initial version of device tree for the Intel socfpga > > arria10 > > de

[U-Boot] [PATCH 10/10] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee This patch adding the Arria10 critical hardware initialization before enabling console print out in spl. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang

[U-Boot] [PATCH 09/10] arm: socfpga: arria10: Added drivers for Arria10 pin mux/pins configuration

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong --- arch/arm/mach-socfpga/Makefile

[U-Boot] [PATCH 08/10] arm: socfpga: arria10: Added drivers for Arria10 clock manager

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, cock_manager_gen5 and clock_manager_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek

[U-Boot] [PATCH 07/10] arm: socfpga: arria10: Added miscellaneous drivers for Arria10

From: Tien Fong Chee The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to misc.c, misc_gen5 and misc_arria10 respectively. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

From: Tien Fong Chee These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen

[U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager

From: Tien Fong Chee Drivers for reset manager is restructured such that common functions, gen5 drivers and Arria10 drivers are moved to reset_manager.c, reset_manager_gen5.c and reset_manager_arria10.c respectively. Signed-off-by: Tien Fong Chee

[U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

From: Tien Fong Chee Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong ---

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

From: Tien Fong Chee These changes to ensure Arria10 SPL build success. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See Cc: Tien Fong

[U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

From: Tien Fong Chee Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See

[U-Boot] [PATCH 01/10] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc

From: Tien Fong Chee This is initial version of device tree for the Intel socfpga arria10 development kit with sdmmc. Signed-off-by: Tien Fong Chee Cc: Marek Vasut Cc: Dinh Nguyen Cc: Chin

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