[U-Boot] [PATCH] powerpc/mpc85xx: Serdes protocol 00 is supported

0x00 is a valid serdes protocol for QorIQ parts, and can not be used to test whether the serdes is enabled or disabled. Signed-off-by: Ebony Zhu b45...@freescale.com --- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 5 - 1 file changed, 5 deletions(-) diff --git a/arch/powerpc/cpu

[U-Boot] [PATCH] board/freescale: Move CRC32 offset in NXID v1 data format

According to AN3638, CRC of NXID v1 is at the end of the 256-byte I2C memory. The wrong CRC32 offset prevents Uboot from reading system information from EEPROM. No NXID v0 is being used on Freescale boards. Signed-off-by: Ebony Zhu b45...@freescale.com --- board/freescale/common/sys_eeprom.c | 7