Stephen Warren writes:
> On 01/13/2017 04:48 AM, Brian Masney wrote:
>> On Thu, Jan 12, 2017 at 11:47:48AM -0700, Stephen Warren wrote:
>>> On 01/12/2017 11:32 AM, Brian Masney wrote:
On Thu, Jan 12, 2017 at 11:02:14AM -0700, Stephen Warren wrote:
> On 01/12/2017
Stefan Bruens <stefan.bru...@rwth-aachen.de> writes:
> On Donnerstag, 6. Oktober 2016 12:32:12 CEST Eric Anholt wrote:
>> Alexander Graf <ag...@suse.de> writes:
>> >> Am 05.10.2016 um 18:48 schrieb Fabian Vogt <fv...@suse.com>:
>> >>
>> &
Alexander Graf writes:
>> Am 05.10.2016 um 18:48 schrieb Fabian Vogt :
>>
>> Hi,
>>
>> Am Mittwoch, 5. Oktober 2016, 09:54:46 CEST schrieb Stephen Warren:
>>> On 09/26/2016 06:26 AM, Fabian Vogt wrote:
This patch series modifies the used drivers to work with
the boot process and more reliably get serial
output.
Signed-off-by: Eric Anholt <e...@anholt.net>
---
board/raspberrypi/rpi/rpi.c | 2 +-
drivers/serial/serial_pl01x.c | 10 --
include/dm/platform_data/serial_pl01x.h | 3 +++
3 files changed, 12 insertions
the boot process and more reliably get serial
output.
Signed-off-by: Eric Anholt <e...@anholt.net>
---
board/raspberrypi/rpi/rpi.c | 3 +--
drivers/serial/serial_pl01x.c | 4
include/dm/platform_data/serial_pl01x.h | 1 +
3 files changed, 6 insertions(+), 2 del
Stephen Warren swar...@wwwdotorg.org writes:
On 06/30/2015 05:56 AM, Jonas Jensen wrote:
Hello,
I have found the following issue with RPi 2:
Only 1 CPU is brought up when the kernel is started from script (see [1]).
All 4 CPUs are brought up if started manually typing in environment
Stephen Warren swar...@wwwdotorg.org writes:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals
use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states
that:
0: L1 L2 cached
4: L2 cache coherent (non allocaing)
8: L2 cached only
c: Direct
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