On 25.03.20 21:01, Stephen Warren wrote:
On 3/25/20 1:11 PM, Jan Kiszka wrote:
On 25.03.20 16:00, Tom Rini wrote:
On Wed, Mar 25, 2020 at 07:32:30AM +0100, Jan Kiszka wrote:
On 20.03.20 19:21, Tom Rini wrote:
On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:
Hi all,
=> ls mmc
On 25.03.20 16:00, Tom Rini wrote:
On Wed, Mar 25, 2020 at 07:32:30AM +0100, Jan Kiszka wrote:
On 20.03.20 19:21, Tom Rini wrote:
On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:
Hi all,
=> ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
CACHE: Misaligned operation at ra
On 20.03.20 19:21, Tom Rini wrote:
On Mon, Mar 16, 2020 at 08:09:53PM +0100, Jan Kiszka wrote:
Hi all,
=> ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misalig
Hi all,
=> ls mmc 0:1 /usr/lib/linux-image-4.9.11-1.3.0-dirty
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
CACHE: Misaligned operation at range [bdfff998, bdfffd98]
From: Jan Kiszka
Overlapped with fdt_addr*, thus corrupted the latter when using both.
Signed-off-by: Jan Kiszka
---
include/configs/mx7dsabresd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index
On 14.11.19 17:41, Tom Rini wrote:
On Thu, Nov 14, 2019 at 05:28:06PM +0100, Jan Kiszka wrote:
On 26.08.19 08:43, Fabrice Fontaine wrote:
Le lun. 26 août 2019 à 07:57, Jan Kiszka a écrit :
On 25.08.19 21:11, Fabrice Fontaine wrote:
Le dim. 25 août 2019 à 17:49, Jan Kiszka a écrit
On 26.08.19 08:43, Fabrice Fontaine wrote:
Le lun. 26 août 2019 à 07:57, Jan Kiszka a écrit :
On 25.08.19 21:11, Fabrice Fontaine wrote:
Le dim. 25 août 2019 à 17:49, Jan Kiszka a écrit :
On 25.08.19 17:13, Fabrice Fontaine wrote:
Le dim. 25 août 2019 à 16:11, Jan Kiszka a écrit
On 25.08.19 21:11, Fabrice Fontaine wrote:
Le dim. 25 août 2019 à 17:49, Jan Kiszka a écrit :
On 25.08.19 17:13, Fabrice Fontaine wrote:
Le dim. 25 août 2019 à 16:11, Jan Kiszka a écrit :
On 25.08.19 15:43, Fabrice Fontaine wrote:
Hello,
Le dim. 25 août 2019 à 13:44, Jan Kiszka a écrit
On 25.08.19 17:13, Fabrice Fontaine wrote:
Le dim. 25 août 2019 à 16:11, Jan Kiszka a écrit :
On 25.08.19 15:43, Fabrice Fontaine wrote:
Hello,
Le dim. 25 août 2019 à 13:44, Jan Kiszka a écrit :
On 01.05.19 15:08, Fabrice Fontaine wrote:
When CROSS_BUILD_TOOLS is set, set HOSTCFLAGS
On 25.08.19 15:43, Fabrice Fontaine wrote:
Hello,
Le dim. 25 août 2019 à 13:44, Jan Kiszka a écrit :
On 01.05.19 15:08, Fabrice Fontaine wrote:
When CROSS_BUILD_TOOLS is set, set HOSTCFLAGS to CFLAGS otherwise CC
will be used with HOSTCFLAGS which seems wrong
Signed-off-by: Fabrice Fontaine
On 01.05.19 15:08, Fabrice Fontaine wrote:
When CROSS_BUILD_TOOLS is set, set HOSTCFLAGS to CFLAGS otherwise CC
will be used with HOSTCFLAGS which seems wrong
Signed-off-by: Fabrice Fontaine
---
tools/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/Makefile
On 26.04.19 12:21, Grant Likely wrote:
On 26/04/2019 10:49, Jan Kiszka wrote:
On 26.04.19 11:07, Francois Ozog wrote:
[...]
Here are the guiding principles of our efforts :
0) we want a cross architecture (x86/Arm/...), cross vendor and cross
processor model update solution
1) untrusted world
On 26.04.19 11:07, Francois Ozog wrote:
On Fri, 26 Apr 2019 at 10:30, Christian Storm
wrote:
Hi,
Background: during the last Linaro connect in Bangkok I was told
that Linaro Edge (LEDGE) were working on a secure software update
mechanism based on UEFI capsules that would flash firmware
for the administrator of the Boot Architecture mailing list to accept my subscription request, but it seems it will take a bit more time. I will send this reply and hope it will not be blocked. I have also added the u-boot mailing list to Cc, as Tom suggested (although I'm not a member), the CIP mailing list, Jan
On 20.12.18 09:45, Marek Vasut wrote:
On 12/10/2018 01:28 PM, Tom Rini wrote:
On Mon, Dec 10, 2018 at 05:13:58AM +0100, Marek Vasut wrote:
On 12/09/2018 09:55 AM, Jan Kiszka wrote:
The default settings of the block cache so far only allow to hold single
1K blocks. However, larger filesystems
From: Jan Kiszka
Without CONFIG_LED, we get
cmd/built-in.o: In function `show_led_state':
cmd/led.c:40: undefined reference to `led_get_state'
cmd/built-in.o: In function `do_led':
cmd/led.c:99: undefined reference to `led_get_by_label'
cmd/led.c:108: undefined reference to `led_set_state
On 10.12.18 05:13, Marek Vasut wrote:
On 12/09/2018 09:55 AM, Jan Kiszka wrote:
The default settings of the block cache so far only allow to hold single
1K blocks. However, larger filesystems tend to use 4K. Failing to cache
those massively degrades access performance unless you manually tune
Hi all,
for some distro script [1], I need setexpr enabled. However, lots of defconfigs
have that disabled, although it is default y in kconfig. I strongly suspect that
this propagated via blind copy, rather than intentionally.
Can we remove it from the defconfigs? Does this have to happen
The default settings of the block cache so far only allow to hold single
1K blocks. However, larger filesystems tend to use 4K. Failing to cache
those massively degrades access performance unless you manually tune the
cache first. This is not desirable.
Signed-off-by: Jan Kiszka
---
My "
On 21.11.18 11:14, Simon Goldschmidt wrote:
- What prevents the creation of such a dev package that only builds
the needed lib?
I think Simon wants to prevent to rebuild u-boot.
No, I want to prevent recompiling the u-boot-tools package (fw_setenv)
and Swupdate after changing U-Boot's
On 21.11.18 10:19, Stefano Babic wrote:
Hi Simon,
On 20/11/18 22:11, Simon Goldschmidt wrote:
On 04.09.2018 12:30, Andreas Reichel wrote:
Hi all,
as Stefano Babic was so friendly and pointed out a few things already,
we come the following problematic points:
For SWupdate to access U-Boot's
On 10.11.18 13:35, Marek Vasut wrote:
On 11/10/2018 09:37 AM, Jan Kiszka wrote:
Hi all,
I'm getting significant speed differences while loading kernel and
initrd from an ext4 rootfs on an SD card via the 'load' command:
## Executing script at 8000
54764 bytes read in 296 ms (180.7 KiB/s
Hi all,
I'm getting significant speed differences while loading kernel and
initrd from an ext4 rootfs on an SD card via the 'load' command:
## Executing script at 8000
54764 bytes read in 296 ms (180.7 KiB/s)
12359688 bytes read in 42982 ms (280.3 KiB/s)
4333462 bytes read in 441 ms (9.4
Hi all,
I was playing with upstream u-boot on the ESPRESSObin - what an
entertaining build process... Anyway, I noticed that, when using latest
version of Marvell's ATF, a3700-utils and mv-ddr-marvell (all on 18.06),
I can make u-boot 2018.05 at least boot. However, anything >= 2018.07
will
On 2018-05-31 19:36, Jan Kiszka wrote:
> On 2017-08-11 12:21, Jagan Teki wrote:
>> On Mon, Jul 24, 2017 at 1:44 AM, Clément Bœsch wrote:
>>> Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi
>>> without heatsink results in the following error after
On 2017-08-11 12:21, Jagan Teki wrote:
> On Mon, Jul 24, 2017 at 1:44 AM, Clément Bœsch wrote:
>> Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi
>> without heatsink results in the following error after a few minutes:
>> WRITE FAILURE: 0x0020 != 0xffdf at offset
Hi Dan,
On 2018-03-12 22:29, Friedrich Daniel wrote:
> Hello Jan,
>
> let me quote my mail to Claudio, who asked more or less the same on March
> 7th(see mail below).
> Personally, hoped that someone from Intel/Altera has the guts to answer this
> question or at least the Maintainer of the
Hi all,
just a quick check because I received reports internally that things are
not working: Is latest U-boot able to drive Aria 10 SoC FGPA boards
completely, or are there still some features missing that downstream
SDKs only contain?
We need upstream U-boot features for a target but are
times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
This patch depend on Jan Kiszka jan.kis...@siemens.com patches.
Jan Kiszka patches link:
http://patchwork.ozlabs.org/project/uboot/list/?submitter=710state=*
Dongsheng,
Does this patch depend on your 1/2 in this set
On 2015-05-13 09:21, Wang Dongsheng wrote:
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Jan Kiszka
Sent: Tuesday, April 21, 2015 1:19 PM
To: U-Boot Mailing List; Tom Rini
Cc: Marc Zyngier; Tom Warren; Paul Walmsley; Ian Campbell; Thierry
On 2015-04-21 07:18, Jan Kiszka wrote:
Changes in v7:
- rebased over master
- fixed issue that prevented secure boot with all cores
= replace ap_pm_init with psci_board_init hook
- enable CONFIG_ARMV7_BOOT_SEC_DEFAULT for tegra to avoid problems with
default config of current Linux
On 2015-04-22 16:03, Andre Przywara wrote:
On Tue, 21 Apr 2015 07:18:24 +0200
Jan Kiszka jan.kis...@siemens.com wrote:
Hi Jan,
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC,
Is this Kconfig rule always enforced these days? Or can one get away
without it by using stuff from include
On 2015-04-21 19:58, Ian Campbell wrote:
On Tue, 2015-04-21 at 07:18 +0200, Jan Kiszka wrote:
From: Ian Campbell i...@hellion.org.uk
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE
This is already invoked a few cycles later in monitor mode by
_secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers
_secure_monitor via smc #0). Drop it here, it serves no purpose.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed
From: Ian Campbell i...@hellion.org.uk
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr
commonly done
via ACLTR, the related function can be overloaded.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested-by: Ian
memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/virt-dt.c | 29
Will be used for unpowergating CPUs.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch
This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested
: Steve Rae s...@broadcom.com
CC: Andre Przywara andre.przyw...@linaro.org
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/ls102xa/cpu.c| 2 +-
arch/arm/cpu/armv7/virt-dt.c| 2 +-
arch/arm/cpu/u-boot.lds
From: Ian Campbell i...@hellion.org.uk
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan
Tegra boards will have to initialize power management for the PSCI
support this way.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/virt-v7.c | 6 ++
arch/arm/include/asm/psci.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b
Reding tred...@nvidia.com
CC: York Sun york...@freescale.com
Ian Campbell (3):
tegra124: Add more registers to struct mc_ctlr
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
jetson-tk1: Add PSCI configuration options and reserve secure code
Jan Kiszka (13):
ARM: Clean up
(which can be influenced by an envvar) has been made when booting the
os.
Signed-off-by: Ian Campbell i...@hellion.org.uk
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested
translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch-tegra124/mc.h | 2
Upstream Linux is broken with default configs when PSCI, thus non-secure
mode is enabled. So the user should explicitly enable this mode, e.g.
when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to
use). We can revert this workaround once Linux got fixed.
Signed-off-by: Jan Kiszka
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed
/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help of the Flow Controller. Once the Flow Controller is
in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF
PSCI requests.
Signed-off-by: Jan Kiszka jan.kis
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.
Fixing this resolves problems of KVM with emulating the generic
timer/counter.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred
...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested-by: Ian Campbell i...@hellion.org.uk
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis
On 2015-04-17 16:43, Stephen Warren wrote:
On 04/17/2015 08:20 AM, Jan Kiszka wrote:
On 2015-04-17 16:12, Stephen Warren wrote:
On 04/17/2015 08:02 AM, Jan Kiszka wrote:
On 2015-04-17 15:57, Stephen Warren wrote:
On 04/17/2015 12:47 AM, Jan Kiszka wrote:
On 2015-04-14 16:30, Ian Campbell
On 2015-04-14 16:30, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote:
On 2015-04-14 16:06, Stephen Warren wrote:
On 04/14/2015 07:46 AM, Tom Rini wrote:
On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote:
Changes in v6:
- rebased over master
- included
Upstream Linux is broken with default configs when PSCI is enabled.
So the user should explicitly enable virtualization, e.g. when she
disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to use). We
can revert this workaround once Linux got fixed.
Signed-off-by: Jan Kiszka jan.kis
On 2015-04-17 15:57, Stephen Warren wrote:
On 04/17/2015 12:47 AM, Jan Kiszka wrote:
On 2015-04-14 16:30, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote:
On 2015-04-14 16:06, Stephen Warren wrote:
On 04/14/2015 07:46 AM, Tom Rini wrote:
On Mon, Apr 13, 2015 at 06:48
On 2015-04-17 16:12, Stephen Warren wrote:
On 04/17/2015 08:02 AM, Jan Kiszka wrote:
On 2015-04-17 15:57, Stephen Warren wrote:
On 04/17/2015 12:47 AM, Jan Kiszka wrote:
On 2015-04-14 16:30, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote:
On 2015-04-14 16:06, Stephen
On 2015-04-14 16:40, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:33 +0200, Jan Kiszka wrote:
On 2015-04-14 16:30, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote:
On 2015-04-14 16:06, Stephen Warren wrote:
On 04/14/2015 07:46 AM, Tom Rini wrote:
On Mon, Apr 13, 2015
On 2015-04-14 16:30, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote:
On 2015-04-14 16:06, Stephen Warren wrote:
On 04/14/2015 07:46 AM, Tom Rini wrote:
On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote:
Changes in v6:
- rebased over master
- included
On 2015-04-14 16:06, Stephen Warren wrote:
On 04/14/2015 07:46 AM, Tom Rini wrote:
On Mon, Apr 13, 2015 at 06:48:05AM +0200, Jan Kiszka wrote:
Changes in v6:
- rebased over master
- included Thierry's SMMU enabling patch
- moved activation patch at the end so that it can be held back
On 2015-04-14 16:50, Stephen Warren wrote:
On 04/14/2015 08:45 AM, Jan Kiszka wrote:
On 2015-04-14 16:40, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:33 +0200, Jan Kiszka wrote:
On 2015-04-14 16:30, Ian Campbell wrote:
On Tue, 2015-04-14 at 16:12 +0200, Jan Kiszka wrote:
On 2015-04-14 16:06
marc.zyng...@arm.com
CC: Thierry Reding tred...@nvidia.com
Ian Campbell (3):
tegra124: Add more registers to struct mc_ctlr
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
jetson-tk1: Add PSCI configuration options and reserve secure code
Jan Kiszka (11):
sun7i: Remove duplicate
commonly done
via ACLTR, the related function can be overloaded.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested-by: Ian
/gmane.comp.boot-loaders.u-boot/210881. It
consists of first enabling CPU1..3 via the PMC, just to powergate them
again with the help of the Flow Controller. Once the Flow Controller is
in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF
PSCI requests.
Signed-off-by: Jan Kiszka jan.kis
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed
...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested-by: Ian Campbell i...@hellion.org.uk
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis
From: Ian Campbell i...@hellion.org.uk
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr
This function will be used to initialize CPU power management for Tegra
SOCs. For now it does nothing.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested
From: Ian Campbell i...@hellion.org.uk
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan
This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested
memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Thierry Reding tred
translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding tred...@nvidia.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch-tegra124/mc.h | 2
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.
Fixing this resolves problems of KVM with emulating the generic
timer/counter.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred
(which can be influenced by an envvar) has been made when booting the
os.
Signed-off-by: Ian Campbell i...@hellion.org.uk
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested
Will be used for unpowergating CPUs.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Thierry Reding tred...@nvidia.com
Tested-by: Thierry Reding tred...@nvidia.com
Tested-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch
This is already invoked a few cycles later in monitor mode by
_secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers
_secure_monitor via smc #0). Drop it here, it serves no purpose.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
Reviewed
On 2015-04-11 05:49, Stephen Warren wrote:
On 03/27/2015 11:06 AM, Albert ARIBAUD wrote:
On Fri, 27 Feb 2015 02:40:33 +0900, Masahiro Yamada
yamad...@jp.panasonic.com wrote:
My main motivations for this commit are:
[1] Follow the arch/arm/Makefile style of Linux Kernel
[2] Maintain
into
the mainline, and finally, it was overtaken by commit e02ee2548afe
(kconfig: switch to single .config configuration).
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reported-by: Stephen Warren swar...@nvidia.com
Reported-by: Jan Kiszka jan.kis...@web.de
---
I just did build test
On 2015-03-19 16:02, Thierry Reding wrote:
On Mon, Mar 09, 2015 at 08:00:10AM +0100, Jan Kiszka wrote:
Changes in v4:
- rebased over master
- implemented psci_get_cpu_id as weak function
- implemented psci_disable/enable_smp as weak functions
- adjusted register interface
On 2015-04-08 15:43, Tom Rini wrote:
On Wed, Apr 08, 2015 at 10:37:40AM +0200, Jan Kiszka wrote:
On 2015-03-19 16:02, Thierry Reding wrote:
On Mon, Mar 09, 2015 at 08:00:10AM +0100, Jan Kiszka wrote:
Changes in v4:
- rebased over master
- implemented psci_get_cpu_id as weak function
On 2015-04-08 16:02, Tom Rini wrote:
On Wed, Apr 08, 2015 at 03:55:44PM +0200, Jan Kiszka wrote:
On 2015-04-08 15:43, Tom Rini wrote:
On Wed, Apr 08, 2015 at 10:37:40AM +0200, Jan Kiszka wrote:
On 2015-03-19 16:02, Thierry Reding wrote:
On Mon, Mar 09, 2015 at 08:00:10AM +0100, Jan Kiszka
On 2015-04-08 17:54, Tom Rini wrote:
On Wed, Apr 08, 2015 at 04:12:21PM +0200, Jan Kiszka wrote:
On 2015-04-08 16:02, Tom Rini wrote:
On Wed, Apr 08, 2015 at 03:55:44PM +0200, Jan Kiszka wrote:
On 2015-04-08 15:43, Tom Rini wrote:
On Wed, Apr 08, 2015 at 10:37:40AM +0200, Jan Kiszka wrote
On 2015-03-18 17:54, Ian Campbell wrote:
On Wed, 2015-03-11 at 11:11 -0400, Tom Rini wrote:
On Mon, Mar 09, 2015 at 08:00:10AM +0100, Jan Kiszka wrote:
Changes in v4:
- rebased over master
- implemented psci_get_cpu_id as weak function
- implemented psci_disable/enable_smp as weak
On 2015-03-18 17:54, Ian Campbell wrote:
On Mon, 2015-03-09 at 08:00 +0100, Jan Kiszka wrote:
Will be required for obtaining the ID of the current CPU in shared PSCI
functions. The default implementation requires a dense ID space and only
supports a single cluster. Therefore, the functions can
On 2015-03-11 16:11, Tom Rini wrote:
On Mon, Mar 09, 2015 at 08:00:10AM +0100, Jan Kiszka wrote:
Changes in v4:
- rebased over master
- implemented psci_get_cpu_id as weak function
- implemented psci_disable/enable_smp as weak functions
- adjusted register interface
Am 2015-03-12 um 13:28 schrieb Tom Rini:
On Thu, Mar 12, 2015 at 08:34:34AM +0100, Jan Kiszka wrote:
Am 2015-03-11 um 16:11 schrieb Tom Rini:
On Mon, Mar 09, 2015 at 08:00:11AM +0100, Jan Kiszka wrote:
This is already invoked a few cycles later in monitor mode by
_secure_monitor. Drop
Am 2015-03-11 um 16:12 schrieb Tom Rini:
On Mon, Mar 09, 2015 at 08:00:18AM +0100, Jan Kiszka wrote:
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add
Am 2015-03-11 um 16:11 schrieb Tom Rini:
On Mon, Mar 09, 2015 at 08:00:11AM +0100, Jan Kiszka wrote:
This is already invoked a few cycles later in monitor mode by
_secure_monitor. Drop it here, it serves no purpose.
For clarity, because of the vector tables?
Sorry, didn't get the question
On 2015-02-12 01:40, Angelo Dureghello wrote:
Add generic-board support for the m68k architecture.
Signed-off-by: Angelo Dureghello ang...@sysam.it
---
arch/m68k/config.mk| 3 +++
arch/m68k/include/asm/config.h | 3 +++
arch/m68k/include/asm/u-boot.h | 8
[resent with updated address of Tom]
On 2015-03-09 07:47, Jan Kiszka wrote:
This fixes a regression of e310b93ec1, affecting Ethernet on the Jetson
TK1, e.g.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
common/board_r.c | 11 +++
1 file changed, 11 insertions(+)
diff
...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 8
arch/arm/cpu/armv7/sunxi/psci.S | 12 +++-
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index bf11a34..0df6633
This function will be used to initialize CPU power management for Tegra
SOCs. For now it does nothing.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch-tegra/ap.h | 5 +
board/nvidia/common/board.c | 4
2 files changed, 9 insertions(+)
diff --git
memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/virt-dt.c | 29
On 2015-03-08 21:08, Ian Campbell wrote:
On Fri, 2015-02-27 at 14:27 +0100, Jan Kiszka wrote:
CC: Ian Campbell i...@hellion.org.uk
I've been running with these on my Jetson (and booting Xen on top) just
fine. So, FWIW:
Tested-by: Ian Campbell i...@hellion.org.uk
Great, thanks! I'll
This fixes a regression of e310b93ec1, affecting Ethernet on the Jetson
TK1, e.g.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
common/board_r.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index 38be09b..0335f6b 100644
--- a/common
This is already invoked a few cycles later in monitor mode by
_secure_monitor. Drop it here, it serves no purpose.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/sunxi/psci.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch
This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/cpu/armv7/psci.S | 14 ++
arch/arm/cpu/armv7/sunxi/psci.S | 15
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.
CC: Marc Zyngier marc.zyng...@arm.com
Signed-off-by: Jan Kiszka jan.kis
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.
Fixing this resolves problems of KVM with emulating the generic
timer/counter.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/mach-tegra/psci.S | 13 +
1 file changed, 13
From: Ian Campbell i...@hellion.org.uk
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
arch/arm/include/asm/arch
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