when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsa...@ti.com>
---
Changes since v2:
- Improved the comment in bo
On 12/08/16 16:30, Tom Rini wrote:
> On Thu, Dec 08, 2016 at 12:19:01PM +0200, Jyri Sarha wrote:
>
>> Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
>> and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
>> the default values LC
when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsa...@ti.com>
---
Changes since v2:
- Move board sp
On 12/02/16 15:06, Jyri Sarha wrote:
>>> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> >> index 43e122e..c71cfd0 100644
>>> >> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs
On 12/02/16 15:01, Tom Rini wrote:
> On Fri, Dec 02, 2016 at 09:54:39AM +0200, Jyri Sarha wrote:
>
>> Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
>> and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
>> the default values LC
when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsa...@ti.com>
---
This patch have been part of TI's latest 2016LTS
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