> -Original Message-
> From: York Sun
> Sent: Tuesday, October 31, 2017 2:45 AM
> To: Mingkai Hu <mingkai...@nxp.com>
> Cc: Shengzhou Liu <shengzhou@nxp.com>; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH 1/4] arm64: ls1043ardb: Add sd_bootcmd
> -Original Message-
> From: York Sun
> Sent: Tuesday, October 03, 2017 11:32 PM
> To: Xiaowei Bao <xiaowei@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] Powerpc: Make pcie link state judge more specific
> -Original Message-
> From: Bao Xiaowei [mailto:xiaowei@nxp.com]
> Sent: Monday, September 25, 2017 11:27 AM
> To: M.h. Lian <minghuan.l...@nxp.com>; Z.q. Hou <zhiqiang....@nxp.com>;
> Mingkai Hu <mingkai...@nxp.com>; York Sun <york@nxp.com&g
> -Original Message-
> From: York Sun
> Sent: Friday, September 15, 2017 5:15 AM
> To: Joakim Tjernlund <joakim.tjernl...@infinera.com>; Mingkai Hu
> <mingkai...@nxp.com>; u-boot @ lists . denx . de <u-boot@lists.denx.de>;
> Roy Zang <roy.z...@
> -Original Message-
> From: York Sun
> Sent: Wednesday, September 06, 2017 11:37 PM
> To: Joakim Tjernlund <joakim.tjernl...@infinera.com>; Mingkai Hu
> <mingkai...@nxp.com>
> Cc: Xiaowei Bao <xiaowei@nxp.com>; u-boot@lists.denx.de
> Subj
> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> Sent: Thursday, September 07, 2017 2:55 PM
> To: Mingkai Hu <mingkai...@nxp.com>; Roy Zang <roy.z...@nxp.com>;
> York Sun <york@nxp.com>
> Cc: u-boo
> -Original Message-
> From: Mingkai Hu
> Sent: Wednesday, September 06, 2017 5:37 PM
> To: 'Joakim Tjernlund' <joakim.tjernl...@infinera.com>; Roy Zang
> <roy.z...@nxp.com>; York Sun <york@nxp.com>
> Cc: u-boot@lists.denx.de
> Subject: RE: set
> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> Sent: Tuesday, September 05, 2017 8:45 PM
> To: Mingkai Hu <mingkai...@nxp.com>; Roy Zang <roy.z...@nxp.com>;
> York Sun <york@nxp.com>
> Cc: u-boo
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, April 25, 2017 11:40 PM
> To: u-boot@lists.denx.de
> Cc: Mingkai Hu <mingkai...@nxp.com>; york sun <york@nxp.com>
> Subject: [PATCH 1/2] armv8: ls1046ardb: Make NET indepe
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, April 25, 2017 11:40 PM
> To: u-boot@lists.denx.de
> Cc: Mingkai Hu <mingkai...@nxp.com>; york sun <york@nxp.com>
> Subject: [PATCH 2/2] armv8: ls1043ardb: Make NET indepe
>
> -Original Message-
> From: york sun
> Sent: Wednesday, March 22, 2017 3:13 AM
> To: Mingkai Hu <mingkai...@nxp.com>
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; u-
> b...@lists.denx.de
> Subject: Please separated FMan from generate NET
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, March 28, 2017 1:57 AM
> To: york sun <york@nxp.com>
> Cc: Jagan Teki <ja...@openedev.com>; u-boot@lists.denx.de; Mingkai Hu
> <mingkai...@nxp.com>
> -Original Message-
> From: york sun
> Sent: Friday, December 02, 2016 1:24 AM
> To: Mingkai Hu <mingkai...@nxp.com>
> Cc: Chris Packham <judge.pack...@gmail.com>; Tony O'Brien
> <tony.obr...@alliedtelesis.co.nz>; u-boot <u-boot@lists.denx.de&g
> -Original Message-
> From: york sun
> Sent: Tuesday, October 25, 2016 12:15 AM
> To: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Pratiyush
> Srivastava <pratiyush.srivast...@nxp.com>; u-boot@lists.denx.de; Mingkai
> Hu <mingkai...@nxp.
> -Original Message-
> From: york sun
> Sent: Saturday, September 17, 2016 4:14 AM
> To: Q.Y. Gong <qianyu.g...@nxp.com>; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; S.H. Xie <sha
> -Original Message-
> From: york sun
> Sent: Friday, August 26, 2016 11:00 PM
> To: Qianyu Gong <qianyu.g...@nxp.com>; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; Shaohui Xie
> -Original Message-
> From: york sun
> Sent: Friday, August 26, 2016 11:01 PM
> To: Qianyu Gong <qianyu.g...@nxp.com>; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com>; Shaohui Xie
> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Friday, August 26, 2016 7:29 PM
> To: u-boot@lists.denx.de; york sun <york@nxp.com>
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <mingkai...@nxp.com&g
> -Original Message-
> From: Shengzhou Liu
> Sent: Monday, August 29, 2016 6:53 PM
> To: Qianyu Gong <qianyu.g...@nxp.com>; u-boot@lists.denx.de; york sun
> <york@nxp.com>
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <
> -Original Message-
> From: Shaohui Xie
> Sent: Monday, August 29, 2016 12:45 PM
> To: york sun <york@nxp.com>; Qianyu Gong <qianyu.g...@nxp.com>;
> u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; Mingkai Hu
> <m
> -Original Message-
> From: Edward L Swarthout
> Sent: Saturday, July 02, 2016 5:44 AM
> To: Prabhakar Kushwaha; york sun; Qianyu Gong; albert.u.b...@aribaud.net;
> u-boot@lists.denx.de; s.temerkha...@gmail.com;
> yamada.masah...@socionext.com
> Cc: Mingkai Hu
&
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: Friday, July 01, 2016 7:55 AM
> To: york sun; Qianyu Gong; albert.u.b...@aribaud.net; u-boot@lists.denx.de;
> s.temerkha...@gmail.com; yamada.masah...@socionext.com
> Cc: Mingkai Hu
> Subject: RE: [U-Boot]
From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
Sent: Thursday, June 30, 2016 2:50 PM
To: Qianyu Gong
Cc: Mingkai Hu; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of
CR3V
Hi
On Jun 30, 2016 08:47
> -Original Message-
> From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> Sent: Thursday, June 30, 2016 3:47 PM
> To: Mingkai Hu
> Cc: Qianyu Gong; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
> Subject: Re: [U-Boot] [PATCH] sf: set the Unifo
> -Original Message-
> From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> Sent: Thursday, June 30, 2016 3:33 PM
> To: Mingkai Hu
> Cc: Qianyu Gong; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
> Subject: Re: [U-Boot] [PATCH] sf: set the Unifo
> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Thursday, April 28, 2016 2:05 PM
> To: u-boot@lists.denx.de; york sun; o...@buserror.net
> Cc: Mingkai Hu; Qianyu Gong
> Subject: [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC is a
Qianyu,
The reset command is used to boot from the location set in the hardware switch.
Regards,
Mingkai
> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Monday, April 25, 2016 4:39 PM
> To: u-boot@lists.denx.de; york sun; Mingkai Hu
>
From: Mingkai Hu <mingkai...@nxp.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v3:
- Move the macro check to soc.c.
v2:
-
> -Original Message-
> From: york sun
> Sent: Saturday, January 30, 2016 4:40 AM
> To: Mingkai Hu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/25/2016 10:12 PM, Mingkai Hu wrote:
> >
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 12:28 PM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v4 2/4] QE: add QE support on ls1043ardb
>
From: Mingkai Hu <mingkai...@nxp.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v2:
- Add a check to make sure A009660
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 12:28 PM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v4 4/4] qe: assgin pins to qe-hdlc
>
> qe-hdlc an
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 12:28 PM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v4 3/4] ls1043rdb: move USB mux config to
> config_bo
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 10:51 AM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v3 4/4] qe: assgin pins to qe-hdlc
>
> qe-hdlc an
> -Original Message-
> From: york sun
> Sent: Saturday, January 23, 2016 1:44 AM
> To: Mingkai Hu; Mingkai Hu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/21/2016 11:50 PM, Mingkai Hu wrote:
&g
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Tuesday, January 26, 2016 9:20 AM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v2 3/3] QE: assgin pins to QE-HDLC
>
> qe-hdlc an
> -Original Message-
> From: Mingkai Hu
> Sent: Thursday, January 21, 2016 11:18 AM
> To: york sun; Mingkai Hu; u-boot@lists.denx.de
> Subject: RE: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
>
>
> > -Original Message
> -Original Message-
> From: york sun
> Sent: Thursday, January 21, 2016 12:21 AM
> To: Mingkai Hu; u-boot@lists.denx.de
> Cc: Mingkai Hu
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/19/2016 10:44 PM, Mingkai Hu
From: Mingkai Hu <mingkai...@nxp.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c
> -Original Message-
> From: Wenbin Song [mailto:wenbin.s...@nxp.com]
> Sent: Tuesday, January 19, 2016 2:48 PM
> To: york...@freescale.com; Mingkai Hu; Qianyu Gong; Shaohui Xie; Wenbin
> Song; u-boot@lists.denx.de
> Subject: [PATCH 1/4] armv8/ls1043aqds: added lpuart
> -Original Message-
> From: Wenbin Song [mailto:wenbin.s...@nxp.com]
> Sent: Tuesday, January 19, 2016 2:48 PM
> To: york...@freescale.com; Mingkai Hu; Qianyu Gong; Shaohui Xie; Wenbin
> Song; u-boot@lists.denx.de
> Cc: songwenbin
> Subject: [PATCH 3/4]
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
drivers/net/fm/ls1043.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
index cf2cc95..93ba318 100644
--- a/drivers/net/fm/ls1043.c
+++ b/drivers/net/fm/ls
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
arch/arm/cpu/armv8/fsl-layerscape
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_l
For SD boot and NAND boot.
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg | 4 ++--
board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/fre
For SD boot and NAND boot.
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 4 ++--
board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls10
From: Shaohui Xie <shaohui@freescale.com>
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <shaohui@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++-
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/e1000.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index d5d48b1..e816410 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -4980,8 +4980,8
From: Po Liu po@freescale.com
Add NOR and SPI flash secure boot target for C29XPCIE board.
Signed-off-by: Po Liu po@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
boards.cfg | 2 ++
include/configs/C29XPCIE.h | 2 ++
2 files changed, 4 insertions(+)
From: Po Liu po@freescale.com
Add NOR and SPI flash secure boot target for C29XPCIE board.
Signed-off-by: Po Liu po@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
configs/C29XPCIE_NOR_SECBOOT_defconfig | 4
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 4
From: Po Liu po@freescale.com
Add NOR and SPI flash secure boot target for C29XPCIE board.
Signed-off-by: Po Liu po@freescale.com
Signed-off-by: Mingkai.Hu mingkai...@freescale.com
---
board/freescale/c29xpcie/MAINTAINERS| 2 ++
configs/C29XPCIE_NOR_SECBOOT_defconfig | 4
From: Mingkai Hu mingkai...@freescale.com
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag
From: Mingkai Hu mingkai...@freescale.com
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag
From: Mingkai Hu mingkai...@freescale.com
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x8000), it will be extended to 0x8000
when phys_size_t is type 'unsigned long long'.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Based
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x8000), it will be extended to 0x8000
when phys_size_t is type 'unsigned long long'.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Based
before div64.h, Or else,
the parameters of phys_addr_t type will be passed wrongly when
CONFIG_PHYS_64BIT is defined.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Based on master branch of git://git.denx.de/u-boot.git
Also can apply direcly to git://www.denx.de/git/u-boot-mpc85xx.git
Tested
LAN8720 PHY is used on Freescale C2X0QDS board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
diff --git a/include/config_phylib_all_drivers.h
b/include/config_phylib_all_drivers.h
index 1db7cec..12828c6 100644
--- a/include/config_phylib_all_drivers.h
+++ b/include
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
include/configs/P2041RDB.h | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 63c8123..918f1b9 100644
--- a/include/configs/P2041RDB.h
module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v2:
- Fix some warning of checkpatch.pl, such as line over 80 characters.
board/freescale/p2040rdb/Makefile | 56
module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Based on
http://git.denx.de/?p=u-boot/u-boot-mpc85xx.git;a=shortlog;h=refs/heads/next
board/freescale/p2040rdb
This patchset add support for the P4080's datapath accelation architecture
in independent mode, and do some code refactor of the file tsec.c.
1. Add the releated MAC controller support, includeing dTSEC and 10GEC
2. Add support for FMan ethernet in Independent mode
3. Add PHY support (VSC8244 and
From: Kumar Gala ga...@kernel.crashing.org
Also rename serdes_get_bank() to serdes_get_bank_by_lane().
Signed-off-by: Emil Medve emilian.me...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/cpu/mpc85xx
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/include/asm/fsl_enet.h | 12 ++
drivers/net/fm/dtsec.c | 168 +++
drivers/net/fm/dtsec.h
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/fm/tgec.c | 104
drivers/net/fm/tgec.h | 230 +
drivers/net
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
board/freescale/corenet_ds/Makefile |1 +
board/freescale/corenet_ds/corenet_ds.c | 11 +-
board/freescale/corenet_ds/eth_p4080.c
From: Kumar Gala ga...@kernel.crashing.org
Add VSC8244 and VSC8234 phy support, this will be reused
by etsec code.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/include/asm/fsl_enet.h | 10 +
drivers/net/fsl_phy.c
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/tsec.c | 232 ++-
include/tsec.h |6 +-
2 files changed, 121 insertions(+), 117 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9c8fe62..910cf9e
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/tsec.c | 857 +---
1 files changed, 416 insertions(+), 441 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 910cf9e..40f1c76 100644
--- a/drivers/net/tsec.c
This will pave the way to move the PHY code to fsl_phy.c which
will be reused by all other code.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/tsec.c | 10 +-
include/tsec.h | 35 +++
2 files changed, 16 insertions(+), 29
Port from tsec.c file to add support for m88e1011s, m88es, m88e1118,
m88e1121r, m88e1145, m88e1149s.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/fsl_phy.c | 299 +
drivers/net/fsl_phy.h | 36 ++
2 files changed
Port from tsec.c file to add support for cis8201, cis8204, dm9161,
dp83865, ksz804, lxt971, rtl8211b.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/fsl_phy.c | 356 -
drivers/net/fsl_phy.h | 57
drivers/net/tsec.c
Also remove the PHY code which will be added by the
following patches.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/Makefile |2 +-
drivers/net/tsec.c | 1483 +++---
include/tsec.h | 246 +-
3 files changed
Port from tsec.c file to add support for vsc8221, vsc8211, vsc8601, vsc8641.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/fsl_phy.c | 119 +
drivers/net/fsl_phy.h | 21 +
2 files changed, 140 insertions(+), 0
Port from tsec.c file to add support for bcm5461, bcm5464, bcm5482s.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/fsl_phy.c | 245 +
drivers/net/fsl_phy.h | 22 +
2 files changed, 267 insertions(+), 0 deletions(-)
diff
The default value of the prescaler of eSDHC clock frequency
is 0x80, so we need to mask the MSB to set a different clock,
or else it maybe make the behavior of this prescaler undefined.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
include/fsl_esdhc.h |2 +-
1 files changed, 1
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
board/freescale/mpc8536ds/mpc8536ds.c | 252 +
1 files changed, 64
The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c |4
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand
Take advantage of the latest full relocation commit of PPC platform
for boot from NAND.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Changelog:
- according to Scott's comments to seperate this patch.
cpu/mpc85xx/u-boot-nand.lds |1 -
1 files changed, 0 insertions(+), 1
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Changelog:
According to Woflgang's comments, fixed the line length of
the board config file.
include/configs/MPC8536DS.h | 147 +++
1 files changed, 79 insertions(+), 68 deletions(-)
diff --git
that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Change over v3:
- Intergrated Scott's comments.
- Intergrated Wolfgang's comments.
MAKEALL
image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Change over
Add boot from NAND/eSDHC/eSPI description
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
No change over v3.
doc/README.mpc8536ds | 127 ++
1 files changed, 127 insertions(+), 0 deletions(-)
create mode 100644 doc/README.mpc8536ds
diff
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
ChangeLog:
- move from board specific directory to cpu/mpc85xx/*,
make
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
ChangeLog:
- move the board specific config for br/or to board init file, i.e.
nand_spl/board/freescale
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
include/asm-ppc/immap_85xx.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..39fdb8e 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include
image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Change over
that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Change over v2:
- Intergrated Kumar's comments.
- Aligned to the leatest git tree
MAKEALL
Add boot from NAND/eSDHC/eSPI description
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
No change over v2, it comes here for the pick up convience.
doc/README.mpc8536ds | 127 ++
1 files changed, 127 insertions(+), 0 deletions
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Makefile|4 +---
include/configs/MPC8536DS.h |2 +-
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index 0b61d05..99837a3 100644
--- a/Makefile
+++ b/Makefile
@@ -2448,9 +2448,7
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Sorry for the spam, ingnor the [PATCH] mpc8536: simplify the top makefile for
36-bit config,
this is the new version.
Makefile|4 +---
include/configs/MPC8536DS.h |2 +-
2 files changed, 2 insertions(+), 4
of the bootup methods above is selected.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
- Move u-boot-nand.lds from board directory to cpu/mpc85xx, which make it
avalible for 85xx platform
- Some modification on u-boot-nand.lds accoring to u-boot.lds
cpu/mpc85xx/cpu_init.c | 19
that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Makefile |1 +
board/freescale/mpc8536ds/config.mk|7 ++
board
These patches implement boot from NAND/eSDHC/eSPI in a unified way - all of
these use the general file cpu/mpc85xx/start.S and load the image into L2SRAM.
Modification over v1:
- Align to the latest tree: http://git.denx.de/u-boot-mpc85xx.git
- Align the NAND board make config to the latest
of the bootup methods above is selected.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
cpu/mpc85xx/cpu_init.c | 19 +++
cpu/mpc85xx/start.S| 23 ++-
cpu/mpc85xx/tlb.c |6 ++
drivers/misc/fsl_law.c |2 ++
4 files changed, 49 insertions(+), 1
So that we can set the NAND loader's relocate stack pointer
to the value other than the relocate address + 0x1.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
board/freescale/mpc8313erdb/mpc8313erdb.c |2 +-
board/sheldon/simpc8313/simpc8313.c |2 +-
include/configs
image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM. But save
the env variables to NOWHERE.
Signed-off-by: Mingkai Hu
that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
Makefile |1 +
board/freescale/mpc8536ds/config.mk|7 +
board
Add boot from NAND/eSDHC/eSPI description
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
doc/README.mpc8536ds | 127 ++
1 files changed, 127 insertions(+), 0 deletions(-)
create mode 100644 doc/README.mpc8536ds
diff --git a/doc
of the bootup methods above is selected.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
cpu/mpc85xx/cpu_init.c | 19 +++
cpu/mpc85xx/start.S| 23 ++-
cpu/mpc85xx/tlb.c |6 ++
drivers/misc/fsl_law.c |2 ++
4 files changed, 49 insertions(+), 1
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