Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
changes for v2 : None
arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm
Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085A
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2 :
- Descriptive commit message
arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++
1 file changed, 3
Add USB XHCI support for ls2085rdb platform
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2: None
include/configs/ls2085ardb.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index a0f0f6c
Add USB XHCI support for ls2085qds platform
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2 : None
include/configs/ls2085aqds.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index
Remove LS102XA immap header inclusion from xhci fsl driver.
It removes redefinition warnings when built for platforms
other than LS102XA
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/xhci-fsl.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host
Map USB XHCI controller base addresses for LS2085A SOC
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/linux/usb/xhci-fsl.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index b07bf19..602a413 100644
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/xhci-dwc3.c | 6 ++
drivers/usb/host/xhci-fsl.c | 3 +++
include/linux/usb/dwc3.h | 22
Replace uint32_t with uintptr_t to remove compilation
warnings for 64-bit architectures.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on commit ec3faf7e2c0671b906018b3c481be2a490bf2bb3
in u-boot-usb/next
drivers/usb/host/xhci-fsl.c | 8
1 file changed, 4
Add USB XHCI support for ls2085qds platform
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/configs/ls2085aqds.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 731eca2..7b77fb4 100644
Add USB XHCI support for ls2085rdb platform
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/configs/ls2085ardb.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index a0f0f6c..a81653c 100644
Define base address of usb xhci controllers for LS2085A SOC
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch
Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
This patchset depends on a patchset sent to u-boot-usb/next
http://patchwork.ozlabs.org/patch/487462/
arch/arm/include/asm/arch-fsl-lsch3
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller
to be initialised is incorrect
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2
- Added space between tags in Subject
- Replaced return value from -1 to -EINVAL
drivers/usb/host/ehci
Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm
Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller
to be initialised is incorrect
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on fsl/usb: Add USB XHCI support
http://patchwork.ozlabs.org/patch/373593/
drivers/usb/host/xhci-fsl.c | 9
Check if USB Erratum A005697 is applicable on BSC913x and
add corresponding property in the device tree via device
tree fixup which is used by linux driver
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on drivers:usb:fsl: Add affected SOCs for USB Erratum A007792
http
Define base address of usb xhci controller
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
include/linux/usb/xhci-fsl.h | 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa
Add support for two USB XHCI controllers for fsl platforms
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on fsl/usb: Add USB XHCI support
drivers/usb/host/xhci-fsl.c | 17 ++---
include/linux/usb/xhci-fsl.h | 5 -
2 files changed, 14 insertions(+), 8
Identify soc(s) having dual phy so as to add utmi_dual as phy_mode
for all these socs. This is required for supporting deel-sleep feature
in linux for usb driver
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb
Add following affected SOCs and their personalities for USB
Erratum A007792 :
T1040 Rev 1.1
T1024 Rev 1.0
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/fsl_usb.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/fsl_usb.h b
Change CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS value to 2 for LS102XAQDS
and LS102XATWR. The XHCI controller has 2 ports; one for 2.0 and
the other for 3.0 USB transactions
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on patch https://patchwork.ozlabs.org/patch/401448
Add a delay of 1 microsecond before issuing soft reset to the
controller to let ongoing ULPI transaction complete.
This prevents corruption of ULPI Function Control Register which
eventually prevents phy clock from entering to low power mode
Signed-off-by: Nikhil Badola nikhil.bad
Check USB Erratum A007792 applicability. If applicable, add
corresponding property in the device tree via device tree fixup
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on http://patchwork.ozlabs.org/patch/400407/
drivers/usb/host/ehci-fsl.c | 9
Add complete USB EHCI support for MPC837XEMDS and MPC837XERDB
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/configs/MPC837XEMDS.h | 5 +
include/configs/MPC837XERDB.h | 5 +
2 files changed, 10 insertions(+)
diff --git a/include/configs/MPC837XEMDS.h b/include
move usb device tree fixup code from arch/powerpc/ to drivers/usb/
so that it works independent of architecture it is running on
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2 :
- Fixed compilation
Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 4
include/usb/ehci-fsl.h | 3 +++
2 files changed, 7 insertions
Enable USB EHCI Host on LS1021AQDS
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/configs/ls1021aqds.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..fd43a3e 100644
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large
usb writes
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on patch https://patchwork.ozlabs.org/patch/394797/
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4
arch/powerpc/include/asm/config_mpc85xx.h
move usb device tree fixup code from arch/powerpc/ to drivers/usb/
so that it works independent of architecture it is running on
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 104
-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 1 +
arch/powerpc/include/asm/fsl_errata.h | 55 -
drivers/usb/host/ehci-fsl.c | 2 +-
include/fsl_usb.h | 66 +++
4 files
...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 64 +
1 file changed, 64 insertions(+)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 295250a..c125e2c 100644
--- a/drivers/usb
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2:
- Using
Introduce new APIs to write fsl usb registers that have w1c bits.
Existing API framework do not take care of w1c bits
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 17
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Dependency on patch http
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Dependency on patch http
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 20
include/usb/ehci-fsl.h | 7 +++
2 files changed, 27 insertions(+)
diff --git a/drivers/usb/host/ehci-fsl.c b
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0
Signed-off-by: Nikhil Badola nikhil.bad
along with length limited to 4
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
or ulpi, strncmp() should be used so that a comparison
of utmi;fsl_ddr:bank_intlv=auto with utmi will succeed.
Signed-off-by: Shaohui Xie shaohui@freescale.com
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Changes for v2:
- Changed patch heading
- Changed patch commit
Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
phy in t1040
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/powerpc/include/asm/config_mpc85xx.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b
From: Ramneek Mehresh ramneek.mehr...@freescale.com
Defines get_svr() for 83xx devices
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Changes for v2:
- Changed patch heading
arch/powerpc/cpu/mpc83xx/start.S | 5 +
1 file changed, 5 insertions(+)
diff --git
From: Ramneek Mehresh ramneek.mehr...@freescale.com
Defines get_svr() for 83xx devices
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/powerpc/cpu/mpc83xx/start.S | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/cpu/mpc83xx/start.S
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phy
Signed-off-by: Nikhil Badola b46...@freescale.com
---
drivers/usb/host/ehci-fsl.c | 8 ++--
1 file changed, 6
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