Re: [PATCH v2] phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift

On May 22, 2025 11:03:33 AM GMT+02:00, Michal Simek wrote: > > >On 5/22/25 10:17, Rutherther wrote: >> Michal Simek writes: >> >>> On 5/21/25 20:16, Rutherther wrote: >>>> The bitshift in GEM_CLK_CTRL register is five bits, not two. There ar

Re: [PATCH v2] phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift

Michal Simek writes: > On 5/21/25 20:16, Rutherther wrote: >> The bitshift in GEM_CLK_CTRL register is five bits, not two. There are >> four bits for each GEM, and one bit reserved in between. >> >> This has caused that using more than one GEM is impossible, >>

[PATCH v2] phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift

The bitshift in GEM_CLK_CTRL register is five bits, not two. There are four bits for each GEM, and one bit reserved in between. This has caused that using more than one GEM is impossible, additionally corrupting the GEM0's configuration, leaving GEM0 unusable as well (ie. if GEM0 and GEM1 are used

[PATCH] phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift

The bitshift in GEM_CLK_CTRL register is five bits, not two. There are four bits for each GEM, and one bit reserved in between. This bug has caused that using more than one GEM is impossible, additionally corrupting the GEM0's configuration, leaving GEM0 unusable as well (ie. if GEM0 and GEM1 are