Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove
it, along with the rest of the support for AXP virtual GPIOs.
Signed-off-by: Samuel Holland
---
drivers/gpio/axp_gpio.c | 75
Now that the USB PHY driver uses the device tree to get VBUS supply
regulators, these Kconfig symbols are unused. Remove them.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 29
configs/A10s-OLinuXino-M_defconfig | 1 -
configs
uino3-nano (PD2)
- icnova-a20-swac_defconfig (PG10) / sun7i-a20-icnova-swac (PH6)
Finally, this board has conflicting pins given for its USB2 VBUS:
- Lamobo_R1_defconfig (PH3) / sun7i-a20-lamobo-r1 (PH12)
Signed-off-by: Samuel Holland
---
drivers/phy/allwinner/phy-sun4i-usb.c | 41 +
On many boards, the USB ports are powered by the PMIC's "drivevbus"
regulator. In preparation for switching the USB PHY driver to use the
regulator uclass instead of a virtual GPIO pin, ensure these boards
have AXP PMIC regulator support enabled.
Signed-off-by: Samuel Holland
---
c
AXP PMICs have a pin which can either report the USB VBUS state, or
driving a regulator that supplies USB VBUS. Add a regulator driver for
controlling this pin. The selection between input and output is done via
the x-powers,drive-vbus-en pin on the PMIC (parent) node.
Signed-off-by: Samuel
...@sholland.org/
Samuel Holland (5):
power: regulator: Add a driver for the AXP PMIC drivevbus
sunxi: Enable PMIC drivevbus regulator support for USB supplies
phy: sun4i-usb: Control supplies via the regulator uclass
sunxi: Remove obsolete USBx_VBUS_PIN Kconfig symbols
gpio: axp: Remove
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().
Signed-off-by: Samuel Holland
---
arch/riscv/lib/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
ha
Signed-off-by: Samuel Holland
---
arch/riscv/cpu/mtrap.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index 6eb3ed1d5a8..5cad7b41ff7 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -26,7 +26,7 @@
Clean things up for the next time somebody adds a target.
Signed-off-by: Samuel Holland
---
arch/riscv/Kconfig | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8fc81fb284c..6d0d812ddb5 100644
--- a/arch/riscv
DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this
driver is never enabled in SPL, so the condition is always true.
Signed-off-by: Samuel Holland
---
drivers/net/sun8i_emac.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net
changed.
Signed-off-by: Samuel Holland
---
arch/arm/include/asm/arch-sunxi/mmc.h | 139 +-
drivers/mmc/sunxi_mmc.c | 4 +
drivers/mmc/sunxi_mmc.h | 138 +
3 files changed, 146 insertions(+), 135 deletions(-)
create
commit 95168d77d391 ("sunxi: add Allwinner R528/T113 SoC support") added
the new entry out of order.
Signed-off-by: Samuel Holland
---
drivers/mmc/sunxi_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4
Now that 32-bit SoCs can load U-Boot proper (and possibly other
firmware) from a FIT, use this method by default. SPL_FIT_IMAGE_TINY is
required to stay within the 24 or 32 KiB SPL size limit on early SoCs;
for consistency, enable it everywhere.
Signed-off-by: Samuel Holland
---
(no changes
on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly.
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- Rely on binman min-size instead of using explicit offsets
- Use Kconfig for firmware addresses instead of an #ifdef staircase
arch
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.
Reviewed-by: Simon Glass
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- New
do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.
Signed-off-by: Samuel Holland
---
(no changes since v2)
Changes in v2:
- New patch for v2
:
- Disable padding from SPL_PAD_TO
- Rely on binman min-size instead of using explicit offsets
- Use Kconfig for firmware addresses instead of an #ifdef staircase
Samuel Holland (4):
sunxi: spl: Disable padding from SPL_PAD_TO
sunxi: binman: Move BL31 and SCP firmware addresses to Kconfig
If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Reviewed-by: Stefan Roese
Signed-off-by: Samuel Holland
---
Changes in v3:
- Switch back to the original patch, now that the phycore-rk3288 build
is fixed by enabling LTO.
Changes in v2:
- Only
sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.
Signed-off-by: Samuel Holland
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
CONFIG_ARCH_SUNXI will not be enabled for RISC-V SoCs using this driver.
Use the symbol for the driver itself instead.
Signed-off-by: Samuel Holland
---
drivers/clk/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index
Hi Andre,
On 10/22/23 17:40, Andre Przywara wrote:
> On Sat, 21 Oct 2023 22:52:06 -0500
> Samuel Holland wrote:
>> On 9/28/23 16:54, Andre Przywara wrote:
>>> The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
>>> same DRAM initialisation c
clrsetbits_le32(0x3202004, 0xffc, 0x6f0);
> + }
> + /* store rank1 config in upper half of para1 */
> + offs += 16;
> + mc_work_mode += 4; /* move to MC_WORK_MODE2 */
> + }
> + }
> + if (maxrank == 2) {
> + config->dram_para2 &= 0xf0ff;
> + /* note: rval is equal to para->dram_para1 here */
> + if ((rval & 0x) == (rval >> 16)) {
> + debug("rank1 config same as rank0\n");
> + } else {
> + config->dram_para2 |= BIT(8);
> + debug("rank1 config different from rank0\n");
> + }
> + }
> +
> + return 1;
> +}
> [...]
> +static int sunxi_ram_probe(struct udevice *dev)
> +{
> + struct sunxi_ram_priv *priv = dev_get_priv(dev);
> + unsigned long dram_size;
> +
> + debug("%s: %s: probing\n", __func__, dev->name);
> +
> + dram_size = sunxi_dram_init();
> + if (!dram_size) {
> + printf("DRAM init failed: %d\n", ret);
There is no ret variable anymore, so this fails to compile. With this
line and the variable size issue fixed, this driver works on my Nezha
board, so with those fixes:
Tested-by: Samuel Holland
> + return -ENODEV;
> + }
> +
> + priv->size = dram_size;
> +
> + return 0;
> +}
Hi Andre,
On 9/28/23 16:54, Andre Przywara wrote:
> At the moment all Allwinner DRAM initialisation routines are stored in
> arch/arm/mach-sunxi, even though those "drivers" are just a giant
> collection of writel's, without any architectural dependency.
>
> The R528/T113-s SoC (with ARM cores)
default 0x2 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
> default 0x0
> ---help---
> Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
> @@ -189,6 +189,14 @@ config SUN50I_GEN_H6
> Select this for sunxi SoCs which have H6 like peripherals, clocks
> and memory map.
>
> +config SUNXI_GEN_NCAT2
> + bool
> + select MMC_SUNXI_HAS_NEW_MODE
> + select SUPPORT_SPL
> + ---help---
> + Select this for sunxi SoCs which have D1 like peripherals, clocks
> + and memory map.
This will eventually need to go in board/sunxi/Kconfig, so it can be
selected by D1 (ARCH_SUNXI=n). For now:
Tested-by: Samuel Holland
On 10/21/23 18:27, Andre Przywara wrote:
> On Thu, 19 Oct 2023 18:51:30 -0500
> Samuel Holland wrote:
>
> Hi Samuel,
>
> thanks for having a look!
>
>> On 9/28/23 16:54, Andre Przywara wrote:
>>> The CONFIG_SATAPWR Kconfig symbol was used to point
ALTERNATIVE
> config SUNXI_A64_TIMER_ERRATUM
> bool
>
> +config SUNXI_NEW_PINCTRL
Please put this in drivers/gpio/Kconfig so it can be selected on RISC-V
(ARCH_SUNXI=n). With that:
Tested-by: Samuel Holland
Regards,
Samuel
> + bool
> + ---help---
> + The Allwinner
eletions(-)
> rename arch/arm/include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h (100%)
Tested-by: Samuel Holland
GPIO_CFG_REG_OFFSET 0x00
> #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
> #define GPIO_CFG_OFFSET(pin) pin) & 0x1f) & 0x7) << 2)
>
> +#define GPIO_DAT_REG_OFFSET 0x10
> +
> +#define GPIO_DRV_REG_OFFSET 0x14
> #define GPIO_DRV_IN
> @@ -231,13 +232,8 @@ int sunxi_name_to_gpio(const char *name)
> static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
> {
> struct sunxi_gpio_plat *plat = dev_get_plat(dev);
> - u32 num = GPIO_NUM(offset);
> - unsigned dat;
> -
| 1 -
> arch/arm/mach-sunxi/pinmux.c | 78 ---
> drivers/gpio/sunxi_gpio.c | 102 -
> 4 files changed, 105 insertions(+), 96 deletions(-)
> delete mode 100644 arch/arm/mach-sunxi/pinmux.c
Many thanks! This works perfec
Hi Andre,
On 9/28/23 16:54, Andre Przywara wrote:
> The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> the power for the Ethernet "MAC" (mostly PHY, really).
> In the DT this is described with the phy-supply property in the MAC DT
> node, pointing to a (GPIO controlled)
Hi Andre,
On 9/28/23 16:54, Andre Przywara wrote:
> Apart from using the new pinctrl MMIO register layout, the Allwinner D1
> and related SoCs still need to usual set of mux values hardcoded in
> U-Boot's pinctrl driver.
> Add the values we need so far to this list, so that DM based drivers
>
dev *priv = dev_get_priv(dev);
> + struct ofnode_phandle_args args;
> + ofnode mdio_node;
> + int ret;
>
> pdata->iobase = dev_read_addr(dev);
>
> + /* The PHY regulator is in the MDIO node, not the EMAC or PHY node. */
> + ret = dev
On 9/28/23 16:54, Andre Przywara wrote:
> From: Samuel Holland
>
> Since the D1 CCU binding is defined, we can add support for its
> gates/resets, following the pattern of the existing drivers.
>
> Signed-off-by: Samuel Holland
> Reviewed-by: Andre Przywara
> Acked-by:
On 9/28/23 16:54, Andre Przywara wrote:
> The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> enables the power for a SATA harddisk.
> In the DT this is described with the target-supply property in the AHCI
> DT node, pointing to a (GPIO controlled) regulator. Since we need SATA
>
_NDS
> imply CPU
> imply CPU_RISCV
> imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
> + imply ANDES_PLMT_TIMER if RISCV_MMODE
> + imply SPL_ANDES_PLMT_TIMER if SPL_RISCV_MMODE
You don't need the "if RISCV_MMODE" condition since the imply statement
will
On 2/20/23 10:11, Sean Anderson wrote:
> On 2/20/23 00:59, Samuel Holland wrote:
>> clk_get_rate() can return an error value. Recompute the rate if the
>> cached value is an error value.
>>
>> Fixes: 4aa78300a025 ("dm: clk: Define clk_get_parent_rate() for c
On 2/20/23 04:39, Michal Suchánek wrote:
> On Sun, Feb 19, 2023 at 11:59:36PM -0600, Samuel Holland wrote:
>> Do not return both NULL and error pointers. The function is only
>> documented as returning error pointers.
>>
>> Fixes: 8a1661f20e6c ("drivers: clk:
On 2/20/23 13:42, Michal Suchánek wrote:
> On Mon, Feb 20, 2023 at 10:57:17AM -0500, Sean Anderson wrote:
>>
>> On 2/20/23 05:46, Michal Suchánek wrote:
>>> On Sun, Feb 19, 2023 at 11:59:34PM -0600, Samuel Holland wrote:
>>>> Some clk uclass functions, such
This fixes an error with trying to link against do_bootm() when
CONFIG_CMD_BOOTM is disabled.
Signed-off-by: Samuel Holland
---
drivers/fastboot/fb_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index
This removes code that abused the device's platform data, interpreting
the driver platform data as if it was the uclass platform data.
Signed-off-by: Samuel Holland
---
.../driver-model/remoteproc-framework.rst | 29 ---
drivers/remoteproc/rproc-uclass.c | 18
There is only one possible value for this field, it is unused except for
debugging, and the devicetree property is not documented.
Signed-off-by: Samuel Holland
---
cmd/remoteproc.c | 12 +---
doc/develop/driver-model/remoteproc-framework.rst | 1
This array is private to the IPU driver, so it should be declared there.
Signed-off-by: Samuel Holland
---
drivers/remoteproc/ipu_rproc.c | 4 +++-
include/remoteproc.h | 1 -
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers
This series cleans up some misplaced and dead code that I ran in to
while writing a new remoteproc driver for the Bouffalo Lab BL808.
Samuel Holland (3):
remoteproc: Move rproc_cfg_arr out of the uclass header
remoteproc: Remove unused mem_type platform data
remoteproc: Remove legacy
Add flags to tell objcopy what kind of ELF to create.
Signed-off-by: Samuel Holland
---
arch/riscv/config.mk | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index a8ed3faf28c..e5f4af22bcb 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv
This allows clk_get_parent() to work with non-CCF clock drivers.
Signed-off-by: Samuel Holland
---
drivers/clk/clk-uclass.c | 18 --
include/clk-uclass.h | 2 ++
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk
There is no need to check the parent clock's ops. The following call to
clk_get_rate() does that already.
Signed-off-by: Samuel Holland
---
drivers/clk/clk-uclass.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 9d052e5a814
log_ret() cannot work with unsigned values, and the assignment to 'ret'
incorrectly truncates the rate from long to int.
Fixes: 5c5992cb90cf ("clk: Add debugging for return values")
Signed-off-by: Samuel Holland
---
drivers/clk/clk-uclass.c | 7 +--
1 file changed, 1 inser
clk_get_rate() can return an error value. Recompute the rate if the
cached value is an error value.
Fixes: 4aa78300a025 ("dm: clk: Define clk_get_parent_rate() for clk operations")
Signed-off-by: Samuel Holland
---
drivers/clk/clk-uclass.c | 3 ++-
1 file changed, 2 insertions(+),
Do not return both NULL and error pointers. The function is only
documented as returning error pointers.
Fixes: 8a1661f20e6c ("drivers: clk: Handle gracefully NULL pointers")
Signed-off-by: Samuel Holland
---
drivers/clk/clk-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
it to implement PLL rate setting on sunxi.
Samuel Holland (6):
clk: Handle error pointers in clk_valid()
clk: Fix error handling in clk_get_rate()
clk: Fix error handling in clk_get_parent()
clk: Fix rate caching in clk_get_parent_rate()
clk: Remove an unneeded check from clk_get_parent_rate
Some clk uclass functions, such as devm_clk_get() and clk_get_parent(),
return error pointers. clk_valid() should not consider these pointers
to be valid.
Fixes: 8a1661f20e6c ("drivers: clk: Handle gracefully NULL pointers")
Signed-off-by: Samuel Holland
---
include/clk.h | 2
ent if there is anything I've missed that should
> be mentioned in the document. Thanks.
> ---
> doc/arch/index.rst | 1 +
> doc/arch/riscv.rst | 43 +++
> 2 files changed, 44 insertions(+)
> create mode 100644 doc/arch/riscv.rst
Reviewed-by: Samuel Holland
On 2/1/23 14:20, Simon Glass wrote:
> This is not used and appears to be associated with the faraday board which
> has been removed. Drop the driver and Kconfig options.
>
> Signed-off-by: Simon Glass
> ---
>
> (no changes since v1)
>
> drivers/usb/gadget/Makefile | 3 +-
>
Hi Simon,
On 1/23/23 12:42, Simon Glass wrote:
> HI Samuel,
>
> On Sun, 22 Jan 2023 at 14:16, Samuel Holland wrote:
>>
>> This is easier to read than the #ifdef staircase, provides better
>> visibility into the memory map (alongside the other Kconfig
>> definit
t in Linux.
Signed-off-by: Samuel Holland
---
arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
index dde9bdf2f9..bd98fb3e6a 100644
--- a/arch/arm/dts
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.
Signed-off-by: Samuel Holland
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
drivers/gpio/axp_gpio.c| 21 -
drivers
ys enabled:
- Nintendo_NES_Classic_Edition_defconfig /
sun8i-r16-nintendo-nes-classic
The PHY driver already assumes VBUS is enabled when no detection method
is available, so again this will not cause any problems.
Signed-off-by: Samuel Holland
---
configs/A33-OLinuXino_defconfig| 2 +-
configs/Ainol_AW1
This driver reports the presence/absence of voltage on the PMIC's USB
VBUS pin. This information is used by the USB PHY driver. The
corresponding Linux driver uses the power supply class, which does not
exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
Signed-off-by: Samuel Holland
this regulator device when present[2]. The net result is removing
some ugly hacks from a couple of GPIO drivers.
[1]: https://lore.kernel.org/u-boot/20230121231307.42628-1-sam...@sholland.org/
[2]: commit 6fa41cdd19b9 ("phy: sun4i-usb: Support VBUS detection via power
supply")
Samuel
On 1/22/23 17:37, Jesse Taube wrote:
>
>
> On 1/22/23 16:15, Samuel Holland wrote:
>> Some 32-bit SoCs can use SCP firmware to implement additional PSCI
>> functionality, such as system suspend. In order to load this firmware
>> from SPL, we need to generate and us
Now that all differences in functionality are covered by individual
flags, remove the enumeration of SoC variants.
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch for v2
drivers/net/sun8i_emac.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/net
beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Add a structure for driver data
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch for v2
drivers/net/sun8i_emac.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index f232b8f087
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch for v2
drivers/net/sun8i_emac.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index
:
- Add a structure for driver data, and put the syscon offset there
Samuel Holland (5):
net: sun8i-emac: Add a structure for variant data
net: sun8i-emac: Add a flag for RMII support
net: sun8i-emac: Add a flag for the internal PHY switch
net: sun8i-emac: Use common syscon setup for R40
net
Currently, EMAC variants are distinguished by their identity, but this
gets unwieldy as more overlapping variants are added. Add a structure so
we can describe the individual feature differences between the variants.
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch for v2
drivers
This more closely matches the U-Boot driver to the Linux version.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/mtd/nand/raw/sunxi_nand.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c
y: Michael Trimarchi
Signed-off-by: Samuel Holland
---
(no changes since v1)
board/sunxi/board.c | 5 +-
drivers/mtd/nand/raw/sunxi_nand.c | 81 ++-
2 files changed, 49 insertions(+), 37 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/boa
-by: Samuel Holland
---
(no changes since v1)
drivers/mtd/nand/raw/sunxi_nand.c | 73 +++
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
3 files changed, 26 insertions(+), 49 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c
b
Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Reviewed-by: Michael Trimarchi
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/mtd/nand/raw/sunxi_nand.c | 10
NAND is always at function 2 on port C.
Pin lists and mux values were taken from the Linux drivers.
Reviewed-by: Andre Przywara
Reviewed-by: Jagan Teki
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +
1 file changed, 13
Signed-off-by: Samuel Holland
---
Changes in v2:
- Fix A80 bus clock/reset bit positions
drivers/clk/sunxi/clk_a10.c | 2 ++
drivers/clk/sunxi/clk_a10s.c | 2 ++
drivers/clk/sunxi/clk_a23.c | 3 +++
drivers/clk/sunxi/clk_a31.c | 6 ++
drivers/clk/sunxi/clk_a64.c | 3 +++
drivers/clk/sun
bus clock/reset bit positions
Samuel Holland (6):
clk: sunxi: Add NAND clocks and resets
pinctrl: sunxi: Add NAND pinmuxes
mtd: nand: sunxi: Remove an unnecessary check
mtd: nand: sunxi: Convert from fdtdec to ofnode
mtd: nand: sunxi: Convert to the driver model
mtd: nand: sunxi: Pass
Now that 32-bit SoCs can load U-Boot proper (and possibly other
firmware) from a FIT, use this method by default. SPL_FIT_IMAGE_TINY is
required to stay within the 24 or 32 KiB SPL size limit on early SoCs;
for consistency, enable it everywhere.
Signed-off-by: Samuel Holland
---
Changes in v2
on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Rely on binman min-size instead of using explicit offsets
- Use Kconfig for firmware addresses instead of an #ifdef staircase
arch/arm/dts/sunxi-u
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch for v2, split from the .dtsi changes
.
[1]: https://lore.kernel.org/u-boot/20230121232518.49723-1-sam...@sholland.org/
Changes in v2:
- Disable padding from SPL_PAD_TO
- Rely on binman min-size instead of using explicit offsets
- Use Kconfig for firmware addresses instead of an #ifdef staircase
Samuel Holland (4):
sunxi: spl
do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.
Signed-off-by: Samuel Holland
---
Changes in v2:
- New patch for v2
common/spl/Kconfig | 3
ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI"
is impossible to satisfy.
Signed-off-by: Samuel Holland
---
Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig
index a75cce7e28..f810646e8a 100644
--- a/Kco
- LDOs shared with GPIO pins => not supported.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Dual-license the driver
- Add a comment about the requirements for the voltage table
- Fix AXP22x ALDO3 enable bit position
drivers/power/regulator/Kconfig | 14 ++
drivers/power/
Now that a regulator driver exists for this PMIC, hook it up to the
device tree "regulators" subnodes.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/power/pmic/axp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/power/pmic/axp.c
If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Reviewed-by: Stefan Roese
Signed-off-by: Samuel Holland
---
Changes in v3:
- Switch back to the original patch, now that the phycore-rk3288 build
is fixed by enabling LTO in patch 1.
Changes in v2
From: Wadim Egorov
The phycore-rk3288 SPL binary is reaching the limits of 32KB very often.
Enable CONFIG_LTO to reduce the size of the SPL and make the board more
future proof for changes increasing the SPL size.
Signed-off-by: Wadim Egorov
Signed-off-by: Samuel Holland
---
Changes in v3
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Move index error check inside if statement
- Update function comment
- Add unit test
drivers/reset/reset
This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Move index error check inside if statement
- Update function comment
- Add unit test
drivers/clk/clk-uclass.c | 12
Use a more accurate check for determining if the full format string will
be handled correctly, since SPL_USE_TINY_PRINTF can be disabled.
Signed-off-by: Samuel Holland
---
drivers/core/dump.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/dump.c b/drivers/core
, SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, and SYS_SPI_U_BOOT_OFFS)
are guaranteed to be defined in all cases.
Fixes: cfa3db602caf ("sunxi: Convert 64-bit boards to use binman")
Signed-off-by: Samuel Holland
---
arch/arm/dts/sunxi-u-boot.dtsi | 6 +-
1 file changed, 5 insertions(+),
This property sets the minimum size of an entry, including padding but
not alignment. It can be used to reserve space for growth of an entry,
or to enforce a minimum offset for later entries in the section.
Signed-off-by: Samuel Holland
---
tools/binman/binman.rst | 8
his response to my original
series[1].
[0]: https://lore.kernel.org/u-boot/20211013023022.58829-1-sam...@sholland.org/
[1]:
https://lore.kernel.org/u-boot/capnjgz1_ee7uodlt36ls5gqa12a2zswrqxwtem5g-opitjn...@mail.gmail.com/
Samuel Holland (2):
binman: Add 'min-size' entry property
sunxi: binman
a comment about the requirements for the voltage table
- Fix AXP22x ALDO3 enable bit position
Samuel Holland (3):
power: pmic: axp: Provide a variant ID in the driver data
power: regulator: Add a driver for AXP PMIC regulators
power: pmic: axp: Bind regulators from the DT
drivers/power/pmic
Subordinate regulator drivers can use this enumerated ID instead of
matching the compatible string again.
Reviewed-by: Andre Przywara
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/power/pmic/axp.c | 18 +-
include/axp_pmic.h | 12
2 files
> boot enabled, like the Remix Mini PC.
>
> Signed-off-by: Andre Przywara
> ---
> Changelog v2 .. v1:
> - use struct members instead of indexing buffer array
>
> arch/arm/mach-sunxi/board.c | 11 +++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
Reviewed-by: Samuel Holland
Hi Andre,
On 1/4/23 19:58, Andre Przywara wrote:
> To determine whether we have been booted from an eMMC boot partition, we
> replay some of the checks that the BROM must have done to successfully
> load the SPL. This involves a checksum check, which currently relies on
> the SPL being wrapped in
onfig")
> Signed-off-by: Andre Przywara
> ---
> Hi,
>
> this is not critical (so nothing for 2023.01), reset works either way.
> But we should fix it anyway.
>
> Cheers,
> Andre
>
> configs/licheepi_nano_defconfig | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Samuel Holland
d that alias with a preprocessor macro.
>
> Now the F1C100s family has gained MMC nodes, so we don't need the
> special treatment anymore. Just remove this guard.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/dts/sunxi-u-boot.dtsi | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Samuel Holland
is the same for SPI NOR and NAND.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/board.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Samuel Holland
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> in
ooks fine to me. I verified that NOR booting still works when
SPL_SPI_SUNXI_NAND is enabled, so:
Tested-by: Samuel Holland # Orange Pi Zero Plus
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/Kconfig | 16 +++
> arch/arm/mach-sunxi
o allow booting without valid magic number when
> booting with SPI NOR.
So the issue is that when CONFIG_SPL_RAW_IMAGE_SUPPORT=y, then
spl_parse_image_header() will return 0 even when using the wrong NAND
parameters? I don't see a better solution, so:
Reviewed-by: Samuel Holland
Tested-by: Samuel
real address. As the address is sent out
> in bit endian, this makes it not compatible with usual 3 byte address.
typo: big
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/spl_spi_sunxi.c | 20 +---
> 1 file changed, 13 insertions(+), 7 deletions(-)
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